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[RISCV] Eliminate unnecessary masking of promoted shift amounts

Description

[RISCV] Eliminate unnecessary masking of promoted shift amounts

SelectionDAGBuilder::visitShift will always zero-extend a shift amount when it
is promoted to the ShiftAmountTy. This results in zero-extension (masking)
which is unnecessary for RISC-V as the shift operations only read the lower 5
or 6 bits (RV32 or RV64).

I initially proposed adding a getExtendForShiftAmount hook so the shift amount
can be any-extended (D52975). @efriedma explained this was unsafe, so I have
instead eliminate the unnecessary and operations at instruction selection time
in a manner similar to X86InstrCompiler.td.

Differential Revision: https://reviews.llvm.org/D53224

Details

Committed
asbOct 12 2018, 4:18 PM
Differential Revision
D53224: [RISCV] Eliminate unnecessary masking of promoted shift amounts
Parents
rL344431: Add REQUIRES: lld to SymbolFileNativePDB tests.
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