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[RISCV] Codegen support for RV32F floating point comparison operations

Description

[RISCV] Codegen support for RV32F floating point comparison operations

This patch also includes extensive tests targeted at select and br+fcmp IR
inputs. A sequence of br+fcmp required support for FPR32 registers to be added
to RISCVInstrInfo::storeRegToStackSlot and
RISCVInstrInfo::loadRegFromStackSlot.

Details

Committed
asbMar 21 2018, 8:11 AM
Parents
rL328103: [ELF][PPC64] Fix getRelExpr for R_PPC64_REL16_LO and R_PPC64_REL16_HA
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