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[PowerPC] MachineSSA pass to reduce the number of CR-logical operations

Description

[PowerPC] MachineSSA pass to reduce the number of CR-logical operations

The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).

Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.

Differential Revision: https://reviews.llvm.org/D30431

Details

Committed
nemanjaiDec 13 2017, 6:47 AM
Differential Revision
D30431: [PowerPC] MachineSSA pass to reduce the number of CR-logical operations
Parents
rL320583: [X86] Add ENTER/LEAVE schedule tests
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