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[RISCV] Implement assembler pseudo instructions for RV32I and RV64I

Description

[RISCV] Implement assembler pseudo instructions for RV32I and RV64I

Adds the assembler pseudo instructions of RV32I and RV64I which can
be mapped to a single canonical instruction. The missing pseudo
instructions (e.g., call, tail, ...) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

Currently, alias emission is disabled by default to keep the patch
minimal. Alias emission by default will be enabled in a subsequent
patch which also updates all affected tests. Note that this patch
should actually break the floating point MC tests. However, the
used FileCheck configuration is not tight enought to detect the
breakage.

Differential Revision: https://reviews.llvm.org/D40902

Patch by Mario Werner.

Details

Committed
asbDec 12 2017, 7:46 AM
Differential Revision
D40902: [RISCV] implemented assembler pseudo instructions for RV32I and RV64I
Parents
rL320486: [clangd] Introduce a "Symbol" class.
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