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[RISCV] MC layer support for the standard RV32D instruction set extension

Description

[RISCV] MC layer support for the standard RV32D instruction set extension

As the FPR32 and FPR64 registers have the same names, use
validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an
FPR64 when necessary. The rest of this patch is very similar to the RV32F
patch.

Differential Revision: https://reviews.llvm.org/D39895