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[RISCV] Codegen for conditional branches

Description

[RISCV] Codegen for conditional branches

A good portion of this patch is the extra functions that needed to be
implemented to support the test case. e.g. storeRegToStackSlot,
loadRegFromStackSlot, eliminateFrameIndex.

Setting ISD::BR_CC to Expand may appear non-obvious on an architecture with
branch+cmp instructions. However, I found it much easier to deal with matching
the expanded form.

I had to change simm13_lsb0 and simm21_lsb0 to inherit from the
Operand<OtherVT> class rather than Operand<i32> in order to keep tablegen
happy. This isn't a big deal, but it does seem a shame to lose the uniformity
across immediate types when there's not an obvious benefit (I'm hoping a
tablegen expert will educate me on what I'm missing here!).

Differential Revision: https://reviews.llvm.org/D29935

Details

Committed
asbNov 8 2017, 5:31 AM
Differential Revision
D29935: [RISCV 13/n] Codegen for conditional branches
Parents
rL317689: [clang-tidy] Add a note about modernize-replace-random-shuffle
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