[CodeGenPrepare] Move sign/zero extensions near loads using type promotion.

This patch extends the optimization in CodeGenPrepare that moves a sign/zero

extension near a load when the target can combine them. The optimization may

promote any operations between the extension and the load to make that possible.

Although this optimization may be beneficial for all targets, in particular

AArch64, this is enabled for X86 only as I have not benchmarked it for other

targets yet.

- Context **

Most targets feature extended loads, i.e., loads that perform a zero or sign

extension for free. In that context it is interesting to expose such pattern in

CodeGenPrepare so that the instruction selection pass can form such loads.

Sometimes, this pattern is blocked because of instructions between the load and

the extension. When those instructions are promotable to the extended type, we

can expose this pattern.

- Motivating Example **

Let us consider an example:

define void @foo(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {

%ld = load i8* %addr1 %zextld = zext i8 %ld to i32 %ld2 = load i32* %addr2 %add = add nsw i32 %ld2, %zextld %sextadd = sext i32 %add to i64 %zexta = zext i8 %a to i32 %addza = add nsw i32 %zexta, %zextld %sextaddza = sext i32 %addza to i64 %addb = add nsw i32 %b, %zextld %sextaddb = sext i32 %addb to i64 call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb) ret void

}

As it is, this IR generates the following assembly on x86_64:

[...]

movzbl (%rdi), %eax # zero-extended load movl (%rsi), %es # plain load addl %eax, %esi # 32-bit add movslq %esi, %rdi # sign extend the result of add movzbl %dl, %edx # zero extend the first argument addl %eax, %edx # 32-bit add movslq %edx, %rsi # sign extend the result of add addl %eax, %ecx # 32-bit add movslq %ecx, %rdx # sign extend the result of add

[...]

The throughput of this sequence is 7.45 cycles on Ivy Bridge according to IACA.

Now, by promoting the additions to form more extended loads we would generate:

[...]

movzbl (%rdi), %eax # zero-extended load movslq (%rsi), %rdi # sign-extended load addq %rax, %rdi # 64-bit add movzbl %dl, %esi # zero extend the first argument addq %rax, %rsi # 64-bit add movslq %ecx, %rdx # sign extend the second argument addq %rax, %rdx # 64-bit add

[...]

The throughput of this sequence is 6.15 cycles on Ivy Bridge according to IACA.

This kind of sequences happen a lot on code using 32-bit indexes on 64-bit

architectures.

Note: The throughput numbers are similar on Sandy Bridge and Haswell.

- Proposed Solution **

To avoid the penalty of all these sign/zero extensions, we merge them in the

loads at the beginning of the chain of computation by promoting all the chain of

computation on the extended type. The promotion is done if and only if we do not

introduce new extensions, i.e., if we do not degrade the code quality.

To achieve this, we extend the existing “move ext to load” optimization with the

promotion mechanism introduced to match larger patterns for addressing mode

(r200947).

The idea of this extension is to perform the following transformation:

ext(promotableInst1(...(promotableInstN(load))))

## >

promotedInst1(...(promotedInstN(ext(load))))

The promotion mechanism in that optimization is enabled by a new TargetLowering

switch, which is off by default. In other words, by default, the optimization

performs the “move ext to load” optimization as it was before this patch.

- Performance **

Configuration: x86_64: Ivy Bridge fixed at 2900MHz running OS X 10.10.

Tested Optimization Levels: O3/Os

Tests: llvm-testsuite + externals.

Results:

- No regression beside noise.
- Improvements:

CINT2006/473.astar: ~2%

Benchmarks/PAQ8p: ~2%

Misc/perlin: ~3%

The results are consistent for both O3 and Os.

rdar://problem/18310086