[mips] Rewrite MipsAsmParser and MipsOperand.

Press ? to show keyboard shortcuts.
Status
Audited
Auditors
dsanders
H39 MIPS Backend Audit Triggered Audit
Committed
dsandersApr 1 2014, 3:35 AM
Reviewer
matheusalmeida
Differential Revision
D3222: [mips] Rewrite MipsAsmParser and MipsOperand.
Parents
rL205291: Add FreeBSD support to sanitizers' procmaps facilities
Branches
Unknown
Tags
Unknown
Description

[mips] Rewrite MipsAsmParser and MipsOperand.

Summary:
Highlights:

  • Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything.
  • All registers are parsed the same way everywhere (even when handling symbol aliasing)
    • One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved.
  • Removes the need for the hasConsumedDollar hack
  • Parenthesis and Bracket suffixes are handled generically
  • Micromips instructions are parsed directly instead of going through the standard encodings first.
  • rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
  • Diagnostics involving registers point at the correct character (the $)
  • There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer.

Lowlights:

  • Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets.
  • I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example).
  • insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

Apr 11 2014, 9:18 AM ยท #1
dsanders accepted this commit.

Changes (23)

HistoryBrowseChangePath
HistoryBrowseModifiedllvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
HistoryBrowseModifiedllvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
HistoryBrowseModifiedllvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
HistoryBrowseModifiedllvm/trunk/lib/Target/Mips/MipsISelLowering.h
HistoryBrowseModifiedllvm/trunk/lib/Target/Mips/MipsInstrInfo.td
HistoryBrowseModifiedllvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
HistoryBrowseModifiedllvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
HistoryBrowseModifiedllvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
HistoryBrowseAddedllvm/trunk/test/MC/Mips/cfi.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips-register-names-invalid.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips3/valid-xfail.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips3/valid.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips32r2/valid.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips4/valid-xfail.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips4/valid.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips5/valid-xfail.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips5/valid.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips64/valid-xfail.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips64/valid.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/mips64r2/valid.s
HistoryBrowseModifiedllvm/trunk/test/MC/Mips/set-at-directive-explicit-at.s

rL205292

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Loading...

llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Loading...

llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Loading...

llvm/trunk/lib/Target/Mips/MipsISelLowering.h

Loading...

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Loading...

llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td

Loading...

llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td

Loading...

llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp

Loading...

llvm/trunk/test/MC/Mips/cfi.s

Loading...

llvm/trunk/test/MC/Mips/mips-register-names-invalid.s

Loading...

llvm/trunk/test/MC/Mips/mips3/valid-xfail.s

Loading...

llvm/trunk/test/MC/Mips/mips3/valid.s

Loading...

llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s

Loading...

llvm/trunk/test/MC/Mips/mips32r2/valid.s

Loading...

llvm/trunk/test/MC/Mips/mips4/valid-xfail.s

Loading...

llvm/trunk/test/MC/Mips/mips4/valid.s

Loading...

llvm/trunk/test/MC/Mips/mips5/valid-xfail.s

Loading...

llvm/trunk/test/MC/Mips/mips5/valid.s

Loading...

llvm/trunk/test/MC/Mips/mips64/valid-xfail.s

Loading...

llvm/trunk/test/MC/Mips/mips64/valid.s

Loading...

llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s

Loading...

llvm/trunk/test/MC/Mips/mips64r2/valid.s

Loading...

llvm/trunk/test/MC/Mips/set-at-directive-explicit-at.s

Loading...

Add Comment