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[RISCV] Support vslide1up/down intrinsics for SEW=64 on RV32.

Authored by craig.topper on Wed, Apr 7, 10:14 AM.

Description

[RISCV] Support vslide1up/down intrinsics for SEW=64 on RV32.

This can't use our normal strategy of splatting the scalar and using
a .vv operation instead of .vx.

Instead this patch bitcasts the vector to the equivalent SEW=32
vector and inserts the scalar parts using two vslide1up/down. We
do that unmasked and apply the mask separately at the end with
a vmerge.

For vslide1up there maybe some other options here like getting
i64 into element 0 and using vslideup.vi with this vector as
vd and the original source as vs1. Masking would still need to
be done afterwards.

That idea doesn't work for vslide1down. We need to slidedown and
then insert a single scalar at vl-1 which we could do with a
vslideup, but that assumes vl > 0 which I don't think we can assume.

The i32 double slide1down implemented here is the best I could come
up with and I just made vslide1up consistent.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D99910

Details

Committed
craig.topperWed, Apr 7, 10:44 AM
Reviewer
frasercrmck
Differential Revision
D99910: [RISCV] Support vslide1up/down intrinsics for SEW=64 on RV32.
Parents
rGdf59850038d8: [HIP] Fix rocm-detect.hip test path
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