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[RISCV] When custom iseling masked stores, copy the mask into V0 instead of…
cb1028a0b95f
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Authored by craig.topper on Mon, Apr 5, 9:25 PM.

Description

[RISCV] When custom iseling masked stores, copy the mask into V0 instead of virtual register.

I missed a few intrinsics in 3dd4aa7d09599507d1f801ffe4bec4c9eebbb8da
when I did this for masked loads and masked segment loads/stores.

Found while trying to share more code between these custom isel
functions.

Details

Committed

craig.topper

Mon, Apr 5, 9:28 PM

Parents

rG58ccbd0d08fe: Comment adjustments for a rename

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craig.topper committed rGcb1028a0b95f: [RISCV] When custom iseling masked stores, copy the mask into V0 instead of… (authored by craig.topper).Mon, Apr 5, 9:28 PM

Herald added a subscriber: HsiangKai. · View Herald TranscriptMon, Apr 5, 9:30 PM

Changes (3)

Path

Size

llvm/

lib/

Target/

RISCV/

RISCVISelDAGToDAG.cpp

test/

CodeGen/

RISCV/

rvv/

fixed-vectors-masked-store-fp.ll

fixed-vectors-masked-store-int.ll

rGcb1028a0b95f

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llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll

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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll

[RISCV] When custom iseling masked stores, copy the mask into V0 instead of…cb1028a0b95fActions

Description

Details

Event Timeline

Changes (3)

rGcb1028a0b95f

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll

[RISCV] When custom iseling masked stores, copy the mask into V0 instead of…
cb1028a0b95f
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