[Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute
This patch implements parsing support for the 'arm_sve_vector_bits' type
attribute, defined by the Arm C Language Extensions (ACLE, version 00bet5,
section 3.7.3) for SVE .
The purpose of this attribute is to define fixed-length (VLST) versions
of existing sizeless types (VLAT). For example:
#if __ARM_FEATURE_SVE_BITS==512 typedef svint32_t fixed_svint32_t __attribute__((arm_sve_vector_bits(512))); #endif
Creates a type 'fixed_svint32_t' that is a fixed-length version of
'svint32_t' that is normal-sized (rather than sizeless) and contains
exactly 512 bits. Unlike 'svint32_t', this type can be used in places
such as structs and arrays where sizeless types can't.
Implemented in this patch is the following:
- Defined and tested attribute taking single argument.
- Checks the argument is an integer constant expression.
- Attribute can only be attached to a single SVE vector or predicate type, excluding tuple types such as svint32x4_t.
- Added the -msve-vector-bits=<bits> flag. When specified the __ARM_FEATURE_SVE_BITS__EXPERIMENTAL macro is defined.
- Added a language option to store the vector size specified by the -msve-vector-bits=<bits> flag. This is used to validate N == __ARM_FEATURE_SVE_BITS, where N is the number of bits passed to the attribute and __ARM_FEATURE_SVE_BITS is the feature macro defined under the same flag.
The __ARM_FEATURE_SVE_BITS macro will be made non-experimental in the final
patch of the series.
This is patch 1/4 of a patch series.
Reviewers: sdesmalen, rsandifo-arm, efriedma, ctetreau, cameron.mcinally, rengolin, aaron.ballman
Reviewed By: sdesmalen, aaron.ballman
Differential Revision: https://reviews.llvm.org/D83550