HomePhabricator

[AMDGPU] Correct DWARF register defintions

Authored by t-tye on Aug 19 2020, 6:09 PM.

Description

[AMDGPU] Correct DWARF register defintions

  • Rename AMDGPU SCC DWARF register to STATUS since the scalar condition code is a bit within the STATUS register.
  • Correct bit size of the VCC_64 register to 64 which is the size in wave64 mode.

Differential Revision: https://reviews.llvm.org/D86259

Details