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[X86][SSE] Start shuffle combining from ANY_EXTEND_VECTOR_INREG on SSE targets

Authored by RKSimon on Aug 3 2020, 4:18 AM.

Description

[X86][SSE] Start shuffle combining from ANY_EXTEND_VECTOR_INREG on SSE targets

We already do this on AVX (+ for ZERO_EXTEND_VECTOR_INREG), but this enables it for all SSE targets - we attempted something similar back at rL357057 but hit issues with the ZERO_EXTEND_VECTOR_INREG handling (PR41249).

I'm still looking at the vector-mul.ll regression - which is due to 32-bit targets performing the load as a f64, resulting in the shuffle combiner thinking it has to create a shuffle in the float domain.

Details

Committed
RKSimonAug 3 2020, 5:41 AM
Parents
rGd8ef1d1251e3: AMDGPU/GlobalISel: Fix selecting broken copies for s32->s64 anyext
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