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[AMDGPU] Define DWARF encoding for condition code registers

Authored by t-tye on Jun 24 2020, 1:11 AM.

Description

[AMDGPU] Define DWARF encoding for condition code registers

Summary:

  • Define DWARF register numbers for vector and scalar condition codes.
  • Document intended purpose of reserved DWARF register numbers.

Reviewers: yaxunl, kzhuravl, arsenm, rampitec, b-sumner

Subscribers: jvesely, wdng, nhaehnle, aprantl, dstuttard, tpr, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82519

Details

Committed
t-tyeJun 26 2020, 2:53 PM
Differential Revision
D82519: [AMDGPU] Define DWARF encoding for condition code registers
Parents
rGb10bd6dfc621: [NFC] Bump ObjCOrBuiltinIDBits to 15
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