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[ARM] Add predicated add reduction patterns

Authored by dmgreen on Wed, Jul 22, 9:30 AM.

Description

[ARM] Add predicated add reduction patterns

Given a vecreduce.add(select(p, x, 0)), we can convert that to a
predicated vaddv, as the else value for the select is the identity
value, a zero. That is what this patch does for the vaddv, vaddva,
vaddlv and vaddlva instructions, copying the existing patterns to also
handle predication through a select.

Differential Revision: https://reviews.llvm.org/D84101

Details

Committed
dmgreenWed, Jul 22, 9:30 AM
Differential Revision
D84101: [ARM] Add predicated add reduction patterns
Parents
rG89e61e782b73: [Sema][AArch64] Add semantics for arm_sve_vector_bits attribute
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