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[RISCV] Add SiFive cores to the CPU option
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Authored by evandro on Oct 2 2020, 2:44 PM.

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Description

[RISCV] Add SiFive cores to the CPU option

Add the SiFive cores E76 and U74 using the SiFive 7 series microarchitecture.

Differential Revision: https://reviews.llvm.org/D88759

Details

Committed

Oct 5 2020, 1:50 PM

Differential Revision

D88759: [RISCV] Add SiFive cores to the CPU option

Parents

rGed88d962953c: [RISCV] Use the extensions in the canonical order (NFC)

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Event Timeline

evandro added an edge: D88759: [RISCV] Add SiFive cores to the CPU option.Oct 5 2020, 1:58 PM

evandro committed rG5d6d8a2769b3: [RISCV] Add SiFive cores to the CPU option (authored by evandro).Oct 5 2020, 1:50 PM

Herald added a subscriber: HsiangKai. · View Herald TranscriptOct 5 2020, 1:58 PM

evandro mentioned this in rGa48d480e1f7e: [RISCV] Fix broken test.Oct 5 2020, 5:39 PM

Changes (4)

Path

Size

clang/

test/

Driver/

Misc/

target-invalid-cpu-note.c

llvm/

include/

llvm/

Support/

RISCVTargetParser.def

lib/

Target/

RISCV/

rG5d6d8a2769b3

clang/test/Driver/riscv-cpus.c

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clang/test/Misc/target-invalid-cpu-note.c

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llvm/include/llvm/Support/RISCVTargetParser.def

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llvm/lib/Target/RISCV/RISCV.td

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