[ARM] Fix Asm/Disasm of TBB/TBH instructions

Authored by DavidSpickett on Jul 16 2020, 7:29 AM.


[ARM] Fix Asm/Disasm of TBB/TBH instructions

This fixes Bugzilla #46616 in which it was reported
that "tbb [pc, r0]" was marked as SoftFail
(aka unpredictable) incorrectly.

Expected behaviour is:

  • ARMv8 is required to use sp as rn or rm (tbb/tbh only have a Thumb encoding so using Arm mode is not an option)
  • If rm is the pc then the instruction is always unpredictable

Some of this was implemented already and this fixes the
rest. Added tests cover the new and pre-existing handling.

Reviewers: ostannard

Reviewed By: ostannard

Subscribers: kristof.beyls, hiraditya, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D84227