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xiangzhangllvm (Xiang Zhang)
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User Since
Dec 25 2018, 11:14 PM (90 w, 4 d)

Recent Activity

Tue, Sep 8

xiangzhangllvm added a comment to D87320: [X86] Check if call is indirect before emitting NT_CALL.

Should we add a test here ?

Tue, Sep 8, 5:51 PM · Restricted Project

Thu, Aug 27

xiangzhangllvm added inline comments to D86673: [StackColoring] Conservatively merge &&Variable for catch(Variable).
Thu, Aug 27, 10:17 PM · Restricted Project
xiangzhangllvm added a comment to D86673: [StackColoring] Conservatively merge &&Variable for catch(Variable).
Thu, Aug 27, 10:13 PM · Restricted Project
xiangzhangllvm updated the summary of D86673: [StackColoring] Conservatively merge &&Variable for catch(Variable).
Thu, Aug 27, 1:28 AM · Restricted Project

Wed, Aug 26

xiangzhangllvm added a reviewer for D86673: [StackColoring] Conservatively merge &&Variable for catch(Variable): wxiao3.
Wed, Aug 26, 11:18 PM · Restricted Project
xiangzhangllvm added a comment to D86673: [StackColoring] Conservatively merge &&Variable for catch(Variable).

Hello efriedma, first thanks for your suggestion.
I agree with"specific load instruction isn't good approach", I just don't know how to easily identify the catch variable in Machine IR.
So I choose the first Load in landing-pad. (I think this can be checked in catch's lowering)

Wed, Aug 26, 11:03 PM · Restricted Project
xiangzhangllvm updated the summary of D86673: [StackColoring] Conservatively merge &&Variable for catch(Variable).
Wed, Aug 26, 10:48 PM · Restricted Project
xiangzhangllvm added a reviewer for D86673: [StackColoring] Conservatively merge &&Variable for catch(Variable): annita.zhang.
Wed, Aug 26, 10:44 PM · Restricted Project
xiangzhangllvm added reviewers for D86673: [StackColoring] Conservatively merge &&Variable for catch(Variable): craig.topper, LuoYuanke, pengfei, MaskRay.
Wed, Aug 26, 10:41 PM · Restricted Project
xiangzhangllvm requested review of D86673: [StackColoring] Conservatively merge &&Variable for catch(Variable).
Wed, Aug 26, 8:24 PM · Restricted Project

Jul 30 2020

xiangzhangllvm added a comment to D84862: [X86] Make ENDBR instruction a scheduling boundary.

+1

Jul 30 2020, 1:59 AM · Restricted Project

Jul 28 2020

xiangzhangllvm abandoned D58102: Support X86 Control-flow Enforcement Technology (CET) in LLD.
Jul 28 2020, 6:11 PM · Restricted Project, lld

Jul 7 2020

xiangzhangllvm added a comment to D83366: [MC] Simplify the logic of applying fixup for fragments, NFCI.

That is really more clear than old code. I +1 for this refine.

Jul 7 2020, 10:53 PM · Restricted Project

Jul 6 2020

xiangzhangllvm added a comment to D83111: [X86-64] Support Intel AMX Intrinsic.

LGTM with all instances of "pointer point" replace with just "pointer"

Jul 6 2020, 7:15 PM · Restricted Project, Restricted Project
xiangzhangllvm committed rG939d8309dbd4: [X86-64] Support Intel AMX Intrinsic (authored by xiangzhangllvm).
[X86-64] Support Intel AMX Intrinsic
Jul 6 2020, 7:14 PM
xiangzhangllvm closed D83111: [X86-64] Support Intel AMX Intrinsic.
Jul 6 2020, 7:14 PM · Restricted Project, Restricted Project
xiangzhangllvm updated the diff for D83111: [X86-64] Support Intel AMX Intrinsic.

Fix some missed change last time.
1 doxygen comments: amxintrin.h --> x86intrin.h

refine ldtilecfg and sttilecfg comment.

2 replace tile reg num 8 with TileRegHigh+1

Jul 6 2020, 6:27 PM · Restricted Project, Restricted Project

Jul 4 2020

xiangzhangllvm updated the diff for D83111: [X86-64] Support Intel AMX Intrinsic.
Jul 4 2020, 9:34 PM · Restricted Project, Restricted Project
xiangzhangllvm added inline comments to D83111: [X86-64] Support Intel AMX Intrinsic.
Jul 4 2020, 9:02 PM · Restricted Project, Restricted Project
xiangzhangllvm added inline comments to D83111: [X86-64] Support Intel AMX Intrinsic.
Jul 4 2020, 9:02 PM · Restricted Project, Restricted Project

Jul 3 2020

xiangzhangllvm updated the diff for D83111: [X86-64] Support Intel AMX Intrinsic.
Jul 3 2020, 11:15 PM · Restricted Project, Restricted Project
xiangzhangllvm added inline comments to D83111: [X86-64] Support Intel AMX Intrinsic.
Jul 3 2020, 10:52 PM · Restricted Project, Restricted Project

Jul 2 2020

xiangzhangllvm updated the diff for D83111: [X86-64] Support Intel AMX Intrinsic.
Jul 2 2020, 10:07 PM · Restricted Project, Restricted Project
xiangzhangllvm created D83111: [X86-64] Support Intel AMX Intrinsic.
Jul 2 2020, 8:29 PM · Restricted Project, Restricted Project

Jul 1 2020

xiangzhangllvm added a comment to D82705: [X86-64] Support Intel AMX instructions.

I tried it, it just remove tags, not tags with their info, I miss-understand at first, thank you!

Jul 1 2020, 10:43 PM · Restricted Project
xiangzhangllvm committed rGaded4f0cc070: [X86-64] Support Intel AMX instructions (authored by xiangzhangllvm).
[X86-64] Support Intel AMX instructions
Jul 1 2020, 6:23 PM
xiangzhangllvm closed D82705: [X86-64] Support Intel AMX instructions.
Jul 1 2020, 6:23 PM · Restricted Project
xiangzhangllvm added a comment to D82705: [X86-64] Support Intel AMX instructions.

Hello, Craig, can I commit it now?

Jul 1 2020, 12:29 AM · Restricted Project

Jun 30 2020

xiangzhangllvm added a comment to D82705: [X86-64] Support Intel AMX instructions.

check-llvm passed.
LGTM

Jun 30 2020, 7:32 PM · Restricted Project
xiangzhangllvm accepted D82705: [X86-64] Support Intel AMX instructions.
Jun 30 2020, 7:00 PM · Restricted Project
xiangzhangllvm added a comment to D82705: [X86-64] Support Intel AMX instructions.

-Fix the previously noted missing break
-Prevent trying to create a register encoding past tmm7

Jun 30 2020, 5:55 PM · Restricted Project
xiangzhangllvm added a comment to D82705: [X86-64] Support Intel AMX instructions.

3 case failed

LLVM :: MC/Disassembler/X86/simple-tests.txt
LLVM :: MC/Disassembler/X86/x86-16.txt
LLVM :: MC/Disassembler/X86/x86-32.txt
Jun 30 2020, 1:35 AM · Restricted Project

Jun 29 2020

xiangzhangllvm updated the diff for D82705: [X86-64] Support Intel AMX instructions.

Change VTILE to TILE

Jun 29 2020, 7:29 PM · Restricted Project
xiangzhangllvm added a comment to D82705: [X86-64] Support Intel AMX instructions.

Done, but I find the last llvm code can not pass "make check-all", no relation with this patch.

Jun 29 2020, 3:44 AM · Restricted Project

Jun 28 2020

xiangzhangllvm updated the diff for D82705: [X86-64] Support Intel AMX instructions.
Jun 28 2020, 7:48 PM · Restricted Project

Jun 27 2020

xiangzhangllvm created D82705: [X86-64] Support Intel AMX instructions.
Jun 27 2020, 11:59 PM · Restricted Project

May 19 2020

xiangzhangllvm added a comment to D79617: Add cet.h for writing CET-enabled assembly code.

Hello rsmith,
first, very sorry for have committed this patch before your reply, I waited 10 days, I thought you have agreed it.
I think the linux-ABI can be the specification of this head file. The context of this cet.h is according to the linux ABI about CET.
We explained in which case we should use this cet.h file. (line 2-4)
tks

May 19 2020, 6:43 PM · Restricted Project

May 18 2020

xiangzhangllvm committed rGbcc0c894f38f: Add cet.h for writing CET-enabled assembly code (authored by xiangzhangllvm).
Add cet.h for writing CET-enabled assembly code
May 18 2020, 11:18 PM
xiangzhangllvm closed D79617: Add cet.h for writing CET-enabled assembly code.
May 18 2020, 11:18 PM · Restricted Project
xiangzhangllvm committed rG62a9eca859d6: Test asm-cet.S fail for window clang (authored by xiangzhangllvm).
Test asm-cet.S fail for window clang
May 18 2020, 10:45 PM
xiangzhangllvm added a reverting change for rGe7e84ff24a5f: Add cet.h for writing CET-enabled assembly code: rG62a9eca859d6: Test asm-cet.S fail for window clang.
May 18 2020, 10:45 PM
xiangzhangllvm added a comment to D79617: Add cet.h for writing CET-enabled assembly code.

@rsmith

May 18 2020, 10:45 PM · Restricted Project
xiangzhangllvm committed rGe7e84ff24a5f: Add cet.h for writing CET-enabled assembly code (authored by xiangzhangllvm).
Add cet.h for writing CET-enabled assembly code
May 18 2020, 8:05 PM
xiangzhangllvm closed D79617: Add cet.h for writing CET-enabled assembly code.
May 18 2020, 8:04 PM · Restricted Project

May 12 2020

xiangzhangllvm added a comment to D79617: Add cet.h for writing CET-enabled assembly code.

Hello @rsmith if you feel OK too, could you help accept it. Thank you!
Hello every friends, I plan to commit it in these days, if you do not oppose it, thank you!

May 12 2020, 5:48 PM · Restricted Project

May 11 2020

xiangzhangllvm added a comment to D79617: Add cet.h for writing CET-enabled assembly code.

! In D79617#2029228, @hjl.tools wrote:
Works for me.

Hello, H.J., could you help accept this patch, I hope it can go to llvm 10.0.1.
Thank you!!

May 11 2020, 5:52 AM · Restricted Project

May 10 2020

xiangzhangllvm updated the diff for D79617: Add cet.h for writing CET-enabled assembly code.

Refine the Macro _CET_ENDBR

May 10 2020, 10:20 PM · Restricted Project
xiangzhangllvm added inline comments to D79617: Add cet.h for writing CET-enabled assembly code.
May 10 2020, 8:19 PM · Restricted Project
xiangzhangllvm updated the diff for D79617: Add cet.h for writing CET-enabled assembly code.

Add #undef _CET_ENDBR

May 10 2020, 8:18 PM · Restricted Project
xiangzhangllvm added inline comments to D79617: Add cet.h for writing CET-enabled assembly code.
May 10 2020, 8:13 PM · Restricted Project
xiangzhangllvm added inline comments to D79617: Add cet.h for writing CET-enabled assembly code.
May 10 2020, 7:41 PM · Restricted Project
xiangzhangllvm updated the diff for D79617: Add cet.h for writing CET-enabled assembly code.
May 10 2020, 5:37 PM · Restricted Project
xiangzhangllvm added inline comments to D79617: Add cet.h for writing CET-enabled assembly code.
May 10 2020, 5:33 PM · Restricted Project

May 9 2020

xiangzhangllvm added a comment to D79617: Add cet.h for writing CET-enabled assembly code.

I want to put this patch to llvm10.0.1, could you help review and then accept this patch?

May 9 2020, 1:33 AM · Restricted Project

May 8 2020

xiangzhangllvm updated the diff for D79617: Add cet.h for writing CET-enabled assembly code.

Good thing is that: CET is already defined to 1/2/3 according to -fcf-protection=xxx at front end, So we directly used it for preprocessor.

May 8 2020, 11:57 PM · Restricted Project
xiangzhangllvm added inline comments to D79617: Add cet.h for writing CET-enabled assembly code.
May 8 2020, 6:17 PM · Restricted Project
xiangzhangllvm added inline comments to D79617: Add cet.h for writing CET-enabled assembly code.
May 8 2020, 6:17 PM · Restricted Project
xiangzhangllvm created D79617: Add cet.h for writing CET-enabled assembly code.
May 8 2020, 1:01 AM · Restricted Project

Apr 19 2020

xiangzhangllvm committed rG0980038a5e44: Handle CET for -exception-model sjlj (authored by xiangzhangllvm).
Handle CET for -exception-model sjlj
Apr 19 2020, 8:17 PM
xiangzhangllvm closed D77124: Handle CET for -exception-model sjlj.
Apr 19 2020, 8:17 PM · Restricted Project

Apr 16 2020

xiangzhangllvm added a comment to rG2c36c23f3476: Recommit "[Driver] Default to -fno-common for all targets".

OK, I see GCC10 also defaults to -fno-common and so we get consistent behaviour with GCC.

Apr 16 2020, 7:30 PM
xiangzhangllvm updated subscribers of rG2c36c23f3476: Recommit "[Driver] Default to -fno-common for all targets".
Apr 16 2020, 6:57 PM
xiangzhangllvm added a comment to rG2c36c23f3476: Recommit "[Driver] Default to -fno-common for all targets".

why "Default to -fno-common for all target" ?
this is a bug change. It make different action with other compilers. e.g GCC
So some common project or tests for both GCC and LLVM need to change to build files.

Apr 16 2020, 6:23 PM

Apr 15 2020

xiangzhangllvm updated the diff for D77124: Handle CET for -exception-model sjlj.

Add a test to enhance the patch.

Apr 15 2020, 3:14 AM · Restricted Project
xiangzhangllvm added a comment to D77124: Handle CET for -exception-model sjlj.

Add a test to enhance the patch.

Apr 15 2020, 3:14 AM · Restricted Project
xiangzhangllvm added inline comments to D77124: Handle CET for -exception-model sjlj.
Apr 15 2020, 3:14 AM · Restricted Project
xiangzhangllvm updated the diff for D77124: Handle CET for -exception-model sjlj.

Update test about endbr checking for sjlj model.
And from the test you can see the endbr is not add before catchpad, total 3 endbr, one at the entry of function, 2nd one before "old landpad" (line62) and last one at the begin of BB (new landpad without name) generated before "old landpad"(line 51)

Apr 15 2020, 1:02 AM · Restricted Project
xiangzhangllvm added inline comments to D77124: Handle CET for -exception-model sjlj.
Apr 15 2020, 12:30 AM · Restricted Project

Apr 14 2020

xiangzhangllvm added inline comments to D77124: Handle CET for -exception-model sjlj.
Apr 14 2020, 11:22 PM · Restricted Project
xiangzhangllvm abandoned D77780: Remove -implicit-check-not=foo from X86/disassemble-functions.test.

Done

Apr 14 2020, 2:04 AM · Restricted Project

Apr 9 2020

xiangzhangllvm added inline comments to D77124: Handle CET for -exception-model sjlj.
Apr 9 2020, 6:12 PM · Restricted Project
xiangzhangllvm added a comment to D77780: Remove -implicit-check-not=foo from X86/disassemble-functions.test.

All things clear:
The test have been changed from --implicit-check-not=foo to --implicit-check-not=<foo>: last month.
Sorry for I didn't noticed that.
All my misunderstanding is base on the old check "--implicit-check-not=foo" :

Apr 9 2020, 5:58 PM · Restricted Project
xiangzhangllvm added a comment to D77780: Remove -implicit-check-not=foo from X86/disassemble-functions.test.

OK, I'll recheck the --disassemble-symbols, that is really strange for me the "--disassemble-symbols=main" will mask the other symbols in "main".

Apr 9 2020, 2:40 AM · Restricted Project
xiangzhangllvm added a comment to D77780: Remove -implicit-check-not=foo from X86/disassemble-functions.test.

I guess we want to test dumping different symbols here. If we specify --disassemble-symbols=main, we don't want llvm-objdump to dump the content of foo here. So, we should ensure llvm-objdump will not print foo. At least, I think we should not remove --implicit-check-not="<foo>:", but improve the robustness of checking?

Apr 9 2020, 2:40 AM · Restricted Project
xiangzhangllvm added a comment to D77780: Remove -implicit-check-not=foo from X86/disassemble-functions.test.

Can you double check the non-determinism after D77640?

Apr 9 2020, 2:40 AM · Restricted Project
xiangzhangllvm updated the diff for D77124: Handle CET for -exception-model sjlj.
Apr 9 2020, 2:40 AM · Restricted Project
xiangzhangllvm added inline comments to D77124: Handle CET for -exception-model sjlj.
Apr 9 2020, 12:30 AM · Restricted Project

Apr 8 2020

xiangzhangllvm added a comment to D77780: Remove -implicit-check-not=foo from X86/disassemble-functions.test.
 5 Disassembly of section .text:
 6
 7 0000000000000000 foo:
 8        0: 55                            pushq   %rbp
 9        1: 48 89 e5                      movq    %rsp, %rbp
10        4: 8b 04 25 a8 00 00 00          movl    168, %eax
11        b: 5d                            popq    %rbp
12        c: c3                            retq
13        d: 0f 1f 00                      nopl    (%rax)
14
15 Disassembly of section .anothertext:
16
17 0000000000000010 main:
18       10: 55                            pushq   %rbp
19       11: 48 89 e5                      movq    %rsp, %rbp
20       14: 48 83 ec 20                   subq    $32, %rsp
21       18: 48 8d 04 25 a8 00 00 00       leaq    168, %rax
22       20: c7 45 fc 00 00 00 00          movl    $0, -4(%rbp)
23       27: 48 89 45 f0                   movq    %rax, -16(%rbp)
24       2b: 48 8b 45 f0                   movq    -16(%rbp), %rax
25       2f: 8b 08                         movl    (%rax), %ecx
26       31: 89 4d ec                      movl    %ecx, -20(%rbp)
27       34: e8 c7 ff ff ff                callq   -57 </tmp/a.c>        // =call 0x00000000,   someone reflected there will be <foo> // objdump will dump "foo" here
28       39: 8b 4d ec                      movl    -20(%rbp), %ecx
29       3c: 01 c1                         addl    %eax, %ecx
30       3e: 89 c8                         movl    %ecx, %eax
31       40: 48 83 c4 20                   addq    $32, %rsp
32       44: 5d                            popq    %rbp
Apr 8 2020, 11:57 PM · Restricted Project
xiangzhangllvm added a comment to D77780: Remove -implicit-check-not=foo from X86/disassemble-functions.test.

@jhenderson I find the test is changed by you. Why you do not want to check "foo" here. Thank you.

Apr 8 2020, 11:57 PM · Restricted Project
xiangzhangllvm added a reviewer for D77780: Remove -implicit-check-not=foo from X86/disassemble-functions.test: MaskRay.
Apr 8 2020, 11:57 PM · Restricted Project
xiangzhangllvm updated the summary of D77780: Remove -implicit-check-not=foo from X86/disassemble-functions.test.
Apr 8 2020, 11:57 PM · Restricted Project
xiangzhangllvm created D77780: Remove -implicit-check-not=foo from X86/disassemble-functions.test.
Apr 8 2020, 11:57 PM · Restricted Project
xiangzhangllvm committed rGa3dc9490004c: [X86] Add TSXLDTRK instructions. (authored by tianqing).
[X86] Add TSXLDTRK instructions.
Apr 8 2020, 10:40 PM
xiangzhangllvm closed D77205: [X86] Add TSXLDTRK instructions..
Apr 8 2020, 10:40 PM · Restricted Project

Apr 6 2020

xiangzhangllvm committed rG01a32f2bd3fa: Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement… (authored by xiangzhangllvm).
Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement…
Apr 6 2020, 7:06 PM

Apr 2 2020

xiangzhangllvm committed rGfef2dab100df: Bugix for buildbot failure at commit 43f031d31264d20cfb8f1ebd606c66e57c231d4d… (authored by xiangzhangllvm).
Bugix for buildbot failure at commit 43f031d31264d20cfb8f1ebd606c66e57c231d4d…
Apr 2 2020, 10:46 PM
xiangzhangllvm committed rG43f031d31264: Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement… (authored by xiangzhangllvm).
Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement…
Apr 2 2020, 9:09 PM
xiangzhangllvm closed D76900: Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement Technology).
Apr 2 2020, 9:09 PM · Restricted Project
xiangzhangllvm added inline comments to D76900: Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement Technology).
Apr 2 2020, 8:36 PM · Restricted Project
xiangzhangllvm added a comment to D76900: Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement Technology).

It looks very confusing. Can you create a diff against master branch, not your last change?

Never mind. I couldn't read :-).

This is the whole diff against the master. :-)

Apr 2 2020, 5:54 PM · Restricted Project
xiangzhangllvm committed rGd08fadd6628a: [X86] Add SERIALIZE instruction. (authored by tianqing).
[X86] Add SERIALIZE instruction.
Apr 2 2020, 1:36 AM
xiangzhangllvm closed D77193: [X86] Add SERIALIZE instruction..
Apr 2 2020, 1:36 AM · Restricted Project

Apr 1 2020

xiangzhangllvm updated the diff for D76900: Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement Technology).
  1. Sync with HJ's large code changes in https://github.com/hjl-tools/llvm-project/commit/6a85ba472143c91e5686e1f0faf7fea7b4f0e350
  2. Add Eli's test in https://bugs.llvm.org/show_bug.cgi?id=45364 to llc test and JIT test.
Apr 1 2020, 11:23 PM · Restricted Project

Mar 31 2020

xiangzhangllvm added a comment to D76900: Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement Technology).

I find your patch will not deal with internal function.
I tested GCC, It really will generate endbr for static functions:

Mar 31 2020, 7:18 PM · Restricted Project
xiangzhangllvm updated the diff for D77124: Handle CET for -exception-model sjlj.
Mar 31 2020, 6:44 PM · Restricted Project
xiangzhangllvm created D77124: Handle CET for -exception-model sjlj.
Mar 31 2020, 2:42 AM · Restricted Project

Mar 30 2020

xiangzhangllvm updated the diff for D76900: Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement Technology).

@efriedma Put the https://bugs.llvm.org/show_bug.cgi?id=45364 test into X86/indirect-branch-tracking.ll @test5

Mar 30 2020, 10:55 PM · Restricted Project
xiangzhangllvm added a comment to D76900: Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement Technology).

Yes, please add that as a test.

The current patch works, but it's emitting endbrs for small code model examples where they shouldn't be necessary. Maybe someone else can chime in on how important that is in practice.

Mar 30 2020, 7:41 PM · Restricted Project
xiangzhangllvm added a comment to D76900: Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement Technology).
Mar 30 2020, 6:02 PM · Restricted Project
xiangzhangllvm updated the diff for D76900: Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement Technology).

Let me first update the patch self.

Mar 30 2020, 5:55 AM · Restricted Project