- User Since
- Dec 14 2020, 7:16 AM (10 w, 4 d)
Mon, Feb 8
Wed, Feb 3
I extracted the corresponding parts into a separate lambda and improved the logic to only apply the combine in the corresponding cases where either a min-max or max-min pattern exists in the MIR.
As @Flakebi reverted the changes to prevent the sanitizer from failing, I re-added the changes to this revision.
[AMDGPU] Re-adding the changes from D93708 and fixing the clamp selection pattern.
This patch intends to re-add the changes from D93708 which were removed in d49efdc9696afee4b972c54bc3678b28c5700047 and should fix the issue adressed in this update.
This should fix the sanitizer builds and prevent applying the clamp in unwanted cases.
Tue, Feb 2
Mon, Feb 1
Reverted whitespace changes, added missing includes.
Sun, Jan 31
I investigated the problem and it seems, there were some includes missing in PostLegalizerCombiner as there were changes in terms of how the instructions are made available to the TU.
I will fix this and upload a new patch.
Jan 27 2021
Requested access. Thanks.
Hi, it seems, I am not permitted to commit this patch. Could somebody please do the commit for me? Thanks!
Jan 26 2021
Renamed the G_MED3 opcode and removed a superfluous copy.
Jan 25 2021
Removes the generic createVirtualRegister invocations and the manual setting of the VGPR32 register class.
Jan 18 2021
Added the new MED3 pseudo.
This adds an additional G_MED3_S32 GIR opcode and uses it in the PreLegalizerCombiner.
Jan 13 2021
Implemented a GMIR instruction for the V_CVT opcode and did some changes to the implementation according to the code reviews.
No, I doubt there is support for this in the other path.
Jan 12 2021
Various changes according to the code review. I don't know why the formatting changes in the PostLegalizer keep showing up as they are already reverted to HEAD...
Previously this was implemented in the PostLegalizer. The SMAX / SMIN MIR gets lowered to a pattern of G_SELECT / G_ICMP, so the state after PostLegalizing is equivalent to what I've implemented in the tests before matching this to the min/max instructions. Disabling the optimization in the implementation here yields a result similar to the following:
Jan 11 2021
This moves the implementation to the PreLegalizer and is based on LLVM max/min intrinsics.
Jan 5 2021
Renamed the identifiers in the lit test.
Jan 4 2021
Refactored the pattern matching algorithm. I removed the construct from MIPatternMatch and implemented it directly in the PostLegalizerCombiner.