- User Since
- Dec 4 2018, 6:02 AM (116 w, 1 d)
Rebased, changed strictwqm to strict_wqm and updated tests.
Added missing dot in the intrinsic name.
Mon, Feb 22
Rebased and updated tests.
Fri, Feb 19
Wed, Feb 17
Looks go to me (with two nits inline).
Commoned up the SI and GFX10-WAVE64 checks.
Tue, Feb 16
Updated commit message with more details and pasted the original error message.
Mon, Feb 15
Add the underscore between strict and wwm. Restored the old tests for amdgcn_wwm.
Thu, Feb 11
This is the intended patch, no need to change AMDGPUISelDAGToDAG.cpp in the most recent version. Here, due to the updated check in isBoolSGPR the problematic combines that would strip zext will not happen (see SITargetLowering::performAddCombine/performSubCombine). This is similar to the very first approach I put up for a review.
Following the suggesstions of updating isBoolSGPR.
Wed, Feb 10
Tue, Feb 9
Is it worth adding a test to ensure old intrinsic still works?
Mon, Feb 8
See also D96258.
Wed, Jan 27
Jan 25 2021
LGTM with a few nits - feel free to ignore them.
Jan 21 2021
Sorry for the lack of activity lately - I plan to get back to this patch in the near future.
Jan 20 2021
Jan 18 2021
LGTM with a few more nits (inline).
Jan 15 2021
Dec 16 2020
Nov 18 2020
I asked myself the same question - this was tried before - see https://reviews.llvm.org/D24544. I do not know any more details.
Added two more instructions: trunc and freeze (thanks @foad).
As Matt pointed out in D91633, extractvalue and insertvalue were also missing, so I am adding them here (the new tests are taken from D24543). Also the tests added earlier in D91633 are being moved to spec-other.ll.
Nov 17 2020
Nov 13 2020
Rebased to retrigger the buildbot checks.
Nov 12 2020
Oct 22 2020
Oct 21 2020
Oct 20 2020
Hi! This commit causes problems for AMDGPU backend - see attached file. Any ideas before I start investigating this in detail?
Oct 19 2020
Oct 16 2020
Related to D78091.
Oct 15 2020
Renamed variable to avoid a multiline assignment.
Good spot - I looked at the shader database and indeed the pattern with two connected setcc is frequent enough to special case it so I updated the patch.
Oct 9 2020
Invert the condition.
Oct 6 2020
Ah now I see what you meant, sorry.
Sep 23 2020
Sep 22 2020
bb.1: .. TO_inst (inits m0) ... (uses m0) FROM_inst (clobbers m0) ... S_CBRANCH_VCCZ %bb.1, undef S_BRANCH %bb.2
Simplified test and added 5 more.
Sep 20 2020
Sep 18 2020
Sep 17 2020
Sep 11 2020
I think you are right - I moved the fix to the better place.