• Reverted previous change to restrict the concat_vectors marked as custom. The extra check added to LowerCONCAT_VECTORS (isTypeLegal(Op.getOperand(0)...) will cover cases where the result is a two element vector.

• Restricted the concat_vectors marked as 'custom' to those with result types of 4+ elements only
• Removed unused patterns for reinterpret_cast
• Moved additional isTypeLegal check to the if statement in LowerCONCAT_VECTORS

• Simplified the LowerCONCAT_VECTORS function so that it returns Op if the number of operands is 2.
• Added ISel patterns for lowering floating-point concat_vectors, making this consistent with how we lower concats of predicate types.

Changes made to the LowerCONCAT_VECTORS function:

• Replaced OpVT.getVectorElementCount()*2 condition with Op.getNumOperands() != 2
• Moved the isFloatingPoint() check into the assert

• Removed isScalableVector() check from PromoteIntRes_FP_TO_XINT
• Updated fptoui tests where the result type is promoted to check for fcvtzu

• Renamed ISD nodes to FCVTZ[S|U]_MERGE_PASSTHRU
• Renamed AArch64fcvtz[s|u]_p to AArch64fcvtz[s|u]_mt & moved their definitions to the block containing other _mt nodes in AArch64SVEInstrInfo.td

LGTM

• Renamed ISD nodes to FP_TO_[S|U]INT_MERGE_PASSTHRU
• Lower only the llvm.aarch64.sve.fcvtz[u|s] intrinsics to these nodes and not those with a type suffix (e.g. llvm.aarch64.sve.fcvtzs.i32f64)
• Removed combineSVEConversionFP() and added the new nodes to the list in isMergePassthruOpcode()

Thank you @paulwalker-arm, @eli.friedman and @david-arm for the reviews!

LGTM

• Removed DAGCombine for UNPKHI/LO and added a new case for UZP1, so that we can check for the more specific case of uzp1(unpklo(uzp1(x, y)), z)
• Removed an unnecessary check that InVT is an integer in LowerINSERT_SUBVECTOR
• Renamed Idx in PromoteIntOp_EXTRACT_SUBVECTOR to OpNumElts

• Removed the restriction from PromoteIntOp_EXTRACT_SUBVECTOR which prevented concatenating more than 2 scalable vectors
• Added a case to PerformDAGCombine for UNPKHI/LO which combines the following: unpk(undef) -> undef & unpk(uzp1(x)) -> x

LGTM

• Set EXTRACT_SUBVECTOR to Custom for the illegal types nxv8i8, nxv4i16 & nxv2i32 only.
• Changed LowerINSERT_SUBVECTOR to apply the same checks for both the low & high cases.

In D85220#2211659, @arichardson wrote:

This will cause compilation failures in our downstream fork. Is there any reason for replacing the integer overload instead of adding a TypeSize overload?
I think adding TypeSize::Fixed( to all call sites is not ideal since it's overly verbose and also confusing since it's an offset and not a type size.
It would have also been nice to add a motivation for the change in the commit message rather than just explaining what's changing.

Thanks for reviewing this patch, @efriedma & @david-arm!

• Replaced call to getMemBasePlusOffset in LegalizeVectorTypes.cpp with IncrementPointer

• Additionally refactored getObjectPtrOffset to accept a TypeSize as the Offset argument

• Rebased and made this patch dependent on D85220, which changes the type of the Offset argument passed to getMemBasePlusOffset() to TypeSize

• Replaced uses of getKnownMinSize() with getFixedSize() where appropriate

Thanks for reviewing this patch, @efriedma & @david-arm

LGTM

Changes to IncrementMemoryAddress:

• Changed the assert added for scalable vectors to a report_fatal_error
• Replaced Addr.getValueSizeInBits().getFixedSize() with AddrVT.getSizeInBits().getFixedSize()
• Use DataVT.getStoreSize() instead of DataVT.getSizeInBits()

Thanks for reviewing this change, @efriedma & @david-arm!

LGTM

• Use sextOrTrunc in getVScale() to ensure that MulImm matches the return type of the vscale
• Add an assertion to getNode() which checks that the operand and return types of vscale match

LGTM!

• Split the addressing mode changes into a separate patch (D82893)
• Changed MPI to MachinePointerInfo(LD->getPointerInfo()->getAddrSpace()) in SplitVecRes_LOAD
• Use getFixedSize when creating the APInt in SplitVecRes_LOAD

Thanks for reviewing this again, @fpetrogalli!

• Added HasSVE to Predicates in AArch64SVEInstrInfo.td
• Removed unnecessary indentation changes in AArch64SVEInstrInfo.td
• Removed hasBF16 variable from performST1Combine/performSTNT1Combine

• Moved hasBF16() check into the assert in performLDNT1Combine
• Added HasSVE to the Predicates
• Added a function attribute for the bfloat tests

• Added [HasBF16] predicate to new store pattern in AArch64SVEInstrInfo.td
• Check hasBF16() is true for bfloat16 types in performST1Combine/performSTNT1Combine
• Added bfloat16 test to sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll

• Added an assert in performLDNT1Combine to check hasBF16() is true where the type is a bfloat16