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ftynse (Alex Zinenko)
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User Since
Jun 28 2018, 2:24 AM (145 w, 5 d)

Recent Activity

Yesterday

ftynse accepted D100327: [MLIR] PresburgerSet emptiness check: remove assertions that there are no symbols.
Mon, Apr 12, 10:33 AM · Restricted Project
ftynse committed rG8508a63b887e: [mlir] Rename AVX512 dialect to X86Vector (authored by cota).
[mlir] Rename AVX512 dialect to X86Vector
Mon, Apr 12, 10:20 AM
ftynse closed D100119: [mlir] Rename AVX512 dialect to X86Vector.
Mon, Apr 12, 10:20 AM · Restricted Project, Restricted Project
ftynse added a comment to D100119: [mlir] Rename AVX512 dialect to X86Vector.

I have expressed by concerns about the dialect AVX here and in the previous discussion. We will have to rename it the moment somebody wants SSE! I don't understand what is blocking here, the renamed dialect intends to contain ops related to X86 vectors. It does not yet, but this should not preclude us from stating the intent and proceeding. If somebody fills super-strongly about the name, I can waste my time to add a random SSE op once its landed...

Mon, Apr 12, 8:58 AM · Restricted Project, Restricted Project

Sat, Apr 10

ftynse added a comment to D100119: [mlir] Rename AVX512 dialect to X86Vector.

Is there a proposal for the first non AVX op to be added to this and which one it would be?

Sat, Apr 10, 12:02 PM · Restricted Project, Restricted Project

Fri, Apr 9

ftynse accepted D100119: [mlir] Rename AVX512 dialect to X86Vector.
Fri, Apr 9, 7:09 AM · Restricted Project, Restricted Project

Thu, Apr 8

ftynse accepted D100114: [MLIR] Support symbols in emptiness checks for FlatAffineConstraints.
Thu, Apr 8, 8:27 AM · Restricted Project

Wed, Apr 7

ftynse accepted D100040: [mlir] Export python-related .cmake files.
Wed, Apr 7, 8:24 AM · Restricted Project
ftynse added inline comments to D99939: [mlir] Support complex numbers in Linalg promotion.
Wed, Apr 7, 4:32 AM · Restricted Project
ftynse accepted D100001: [mlir] Add "mask" operand to vector.transfer_read/write..
Wed, Apr 7, 4:26 AM · Restricted Project
ftynse added inline comments to D99818: [mlir] X86Vector: Add AVX Rsqrt.
Wed, Apr 7, 12:13 AM · Restricted Project

Tue, Apr 6

ftynse added inline comments to D99948: [mlir] add support for index type in vectors..
Tue, Apr 6, 2:21 PM · Restricted Project
ftynse added inline comments to D99948: [mlir] add support for index type in vectors..
Tue, Apr 6, 2:21 PM · Restricted Project
ftynse added inline comments to D99925: [MLIR] Add a switch operation to the standard dialect.
Tue, Apr 6, 9:46 AM · Restricted Project
ftynse added a comment to D99925: [MLIR] Add a switch operation to the standard dialect.

Are these clang-tidy naming errors legit? I think the names match the ones used

Tue, Apr 6, 9:45 AM · Restricted Project
ftynse added inline comments to D99925: [MLIR] Add a switch operation to the standard dialect.
Tue, Apr 6, 9:35 AM · Restricted Project
ftynse committed rG7dc7790ec52e: [mlir] Fix support for lowering non-32-bit affine reductions. (authored by ftynse).
[mlir] Fix support for lowering non-32-bit affine reductions.
Tue, Apr 6, 5:00 AM
ftynse closed D99942: [mlir] Fix support for lowering non-32-bit affine reductions..
Tue, Apr 6, 5:00 AM · Restricted Project
ftynse requested review of D99942: [mlir] Fix support for lowering non-32-bit affine reductions..
Tue, Apr 6, 3:55 AM · Restricted Project
ftynse requested changes to D99643: [mlir] scf::ForOp: Propagate constants in loop body to trigger simplifications.

Would you mind providing a commit description in addition to the one-line summary? A good description explains _why_ this new functionality is useful, rather than what the change does.

Tue, Apr 6, 2:50 AM · Restricted Project
ftynse added inline comments to D99818: [mlir] X86Vector: Add AVX Rsqrt.
Tue, Apr 6, 2:31 AM · Restricted Project
ftynse added inline comments to D99925: [MLIR] Add a switch operation to the standard dialect.
Tue, Apr 6, 2:19 AM · Restricted Project

Fri, Apr 2

ftynse committed rG5d7c832e8c14: [mlir] add memref dialect as dependent of lower-affine pass (authored by ftynse).
[mlir] add memref dialect as dependent of lower-affine pass
Fri, Apr 2, 12:17 AM
ftynse closed D99720: [mlir] add memref dialect as dependent of lower-affine pass.
Fri, Apr 2, 12:17 AM · Restricted Project

Thu, Apr 1

ftynse requested review of D99720: [mlir] add memref dialect as dependent of lower-affine pass.
Thu, Apr 1, 5:21 AM · Restricted Project
ftynse accepted D99430: [mlir][Python][Linalg] Add missing attributes to linalg ops.
Thu, Apr 1, 1:13 AM · Restricted Project

Wed, Mar 31

ftynse added inline comments to D99430: [mlir][Python][Linalg] Add missing attributes to linalg ops.
Wed, Mar 31, 9:34 AM · Restricted Project
ftynse added inline comments to D99638: [mlir] Add C and python API for is_registered_operation..
Wed, Mar 31, 12:30 AM · Restricted Project
ftynse accepted D99578: [mlir][Linalg][Python] Create the body of builtin named Linalg ops.

Looks good. It would be nice to have DialectLinalg in a separate extension and generally start structuring the bindings more than the current flat representation, e.g. by adding lib/Bindings/Python/Dialect/Linalg. This could be a separate restructuring commit though.

Wed, Mar 31, 12:28 AM · Restricted Project

Sat, Mar 27

ftynse committed rGd68ba1fe5032: [mlir] Register Linalg passes in C API and Python Bindings (authored by ftynse).
[mlir] Register Linalg passes in C API and Python Bindings
Sat, Mar 27, 1:58 AM
ftynse closed D99431: [mlir] Register Linalg passes in C API and Python Bindings.
Sat, Mar 27, 1:58 AM · Restricted Project

Fri, Mar 26

ftynse added inline comments to D99442: Fix deletion of operations through the rewriter in a pattern matching a consumer operation.
Fri, Mar 26, 3:18 PM · Restricted Project
ftynse committed rGdb694c52b4aa: [mlir] fix -Wsign-compare in memref unit tests (authored by ftynse).
[mlir] fix -Wsign-compare in memref unit tests
Fri, Mar 26, 11:38 AM
ftynse requested review of D99431: [mlir] Register Linalg passes in C API and Python Bindings.
Fri, Mar 26, 11:06 AM · Restricted Project

Wed, Mar 24

ftynse committed rGb3386a734e43: [mlir] introduce data layout entry for index type (authored by ftynse).
[mlir] introduce data layout entry for index type
Wed, Mar 24, 7:14 AM
ftynse committed rG842d24350872: [mlir] forward data layout query to scoping op in absence of specification (authored by ftynse).
[mlir] forward data layout query to scoping op in absence of specification
Wed, Mar 24, 7:14 AM
ftynse committed rGf9cdc61d1131: [mlir] provide a version of data layout size hooks in bits (authored by ftynse).
[mlir] provide a version of data layout size hooks in bits
Wed, Mar 24, 7:14 AM
ftynse committed rG1916b0e098ad: [mlir] support data layout specs on ModuleOp (authored by ftynse).
[mlir] support data layout specs on ModuleOp
Wed, Mar 24, 7:14 AM
ftynse closed D98937: [mlir] introduce data layout entry for index type.
Wed, Mar 24, 7:14 AM · Restricted Project
ftynse closed D98525: [mlir] forward data layout query to scoping op in absence of specification.
Wed, Mar 24, 7:14 AM · Restricted Project
ftynse closed D98524: [mlir] provide a version of data layout size hooks in bits.
Wed, Mar 24, 7:14 AM · Restricted Project
ftynse closed D98500: [mlir] support data layout specs on ModuleOp.
Wed, Mar 24, 7:13 AM · Restricted Project
ftynse accepted D99166: [mlir] Support MemRefType with multiple AffineMaps in getStridesAndOffset.
Wed, Mar 24, 6:32 AM · Restricted Project
ftynse accepted D99246: [mlir] Translate global initializers after creating all LLVM IR globals.

Thanks!

Wed, Mar 24, 6:22 AM · Restricted Project

Tue, Mar 23

ftynse added a comment to D99059: [mlir] Add an option to still use bottom-up traversal.

With a test, I would have preferred to revert Chris' patch in this case.
Exposing the buggy behavior in linalg is cause to fix linalg, would we revert this patch immediately when fixing Linalg's bug?

Tue, Mar 23, 3:20 PM · Restricted Project
ftynse committed rG20c68d9441cd: [mlir] silence -Wunused-variable in release mode in Linalg transforms (authored by ftynse).
[mlir] silence -Wunused-variable in release mode in Linalg transforms
Tue, Mar 23, 11:00 AM
ftynse added a comment to D99059: [mlir] Add an option to still use bottom-up traversal.

Let me get a bit more practical here. Do you think this patch would have been more acceptable if it also included a test that exposed the buggy behavior in that Linalg pass?

Tue, Mar 23, 10:50 AM · Restricted Project
ftynse accepted D98965: [MLIR][Linalg] Hoist padding across multiple levels of tiling.
Tue, Mar 23, 10:36 AM · Restricted Project
ftynse committed rG5fac87d1bcc4: [mlir] verify that operand/result_segment_sizes attributes have i32 element (authored by ftynse).
[mlir] verify that operand/result_segment_sizes attributes have i32 element
Tue, Mar 23, 10:27 AM
ftynse closed D99183: [mlir] verify that operand/result_segment_sizes attributes have i32 element.
Tue, Mar 23, 10:26 AM · Restricted Project
ftynse requested review of D99183: [mlir] verify that operand/result_segment_sizes attributes have i32 element.
Tue, Mar 23, 6:05 AM · Restricted Project
ftynse added a comment to D99059: [mlir] Add an option to still use bottom-up traversal.

This is tested, although indirectly, by the linalg fusion-on-tensors pass that was changed to use the functionality. The buggy functionality is in upstream code, not exposing the bug upstream is justification enough for me. We can argue whether the linalg code was actually buggy, or was just relying on the behavior of the rewriter that was not specified as either part of the contract or not part of it (also, https://www.hyrumslaw.com/). I think minimizing the test that exposes the problem and adding it upstream would be beneficial for everyone, and is reasonable request, post-commit or otherwise. Suggestions on how to test the order-of-traversal directly are welcome. And I agree that we can do better on explaining our changes and our requests.

Tue, Mar 23, 5:48 AM · Restricted Project

Mon, Mar 22

ftynse added inline comments to D98965: [MLIR][Linalg] Hoist padding across multiple levels of tiling.
Mon, Mar 22, 8:51 AM · Restricted Project
ftynse accepted D98986: [mlir][Pattern] Add better support for using interfaces/traits to match root operations in rewrite patterns.

Please fix the linter messages and consider folding RootKind into some pointer.

Mon, Mar 22, 8:41 AM · Restricted Project
ftynse added inline comments to D98937: [mlir] introduce data layout entry for index type.
Mon, Mar 22, 6:58 AM · Restricted Project
ftynse updated the diff for D98937: [mlir] introduce data layout entry for index type.

Rebase

Mon, Mar 22, 6:58 AM · Restricted Project
ftynse added reviewers for D98500: [mlir] support data layout specs on ModuleOp: herhut, nicolasvasilache.
Mon, Mar 22, 6:58 AM · Restricted Project
ftynse added inline comments to D98500: [mlir] support data layout specs on ModuleOp.
Mon, Mar 22, 6:58 AM · Restricted Project
ftynse updated the diff for D98500: [mlir] support data layout specs on ModuleOp.

Address review.

Mon, Mar 22, 6:57 AM · Restricted Project
ftynse accepted D99070: [mlir][Linalg] Fix linalg on tensor fusion.
Mon, Mar 22, 6:01 AM · Restricted Project
ftynse added a comment to D99047: Fix toy language example.

Looks like this was already fixed, but thanks for the patch!

Mon, Mar 22, 2:19 AM · Restricted Project
ftynse accepted D99059: [mlir] Add an option to still use bottom-up traversal.
Mon, Mar 22, 1:55 AM · Restricted Project

Fri, Mar 19

ftynse updated the diff for D98937: [mlir] introduce data layout entry for index type.

cmake

Fri, Mar 19, 5:18 AM · Restricted Project
ftynse requested review of D98937: [mlir] introduce data layout entry for index type.
Fri, Mar 19, 3:26 AM · Restricted Project
ftynse updated the diff for D98525: [mlir] forward data layout query to scoping op in absence of specification.

rebase

Fri, Mar 19, 3:26 AM · Restricted Project
ftynse accepted D98930: [mlir] Rename gpu-to-llvm pass implementation file.
Fri, Mar 19, 2:17 AM · Restricted Project
ftynse accepted D98928: [mlir] Remove ConvertKernelFuncToBlob.
Fri, Mar 19, 1:29 AM · Restricted Project

Thu, Mar 18

ftynse added inline comments to D98041: [MLIR] Create memref dialect and move dialect-specific ops from std..
Thu, Mar 18, 1:04 AM · Restricted Project

Wed, Mar 17

ftynse accepted D98777: Move BaseOpWithOffsetSizesAndStrides to OpBase.td.

Thanks!

Wed, Mar 17, 5:48 AM · Restricted Project
ftynse accepted D98198: Add arm_neon.intr.sdot operation.
Wed, Mar 17, 5:47 AM · Restricted Project
ftynse updated the diff for D98524: [mlir] provide a version of data layout size hooks in bits.

rebase

Wed, Mar 17, 5:40 AM · Restricted Project
ftynse updated the diff for D98500: [mlir] support data layout specs on ModuleOp.

forgot to git-add a test

Wed, Mar 17, 5:40 AM · Restricted Project
ftynse added a comment to D98662: [mlir] Add lowering from math::Log1p to LLVM.

I wonder if this is something that should be instead implemented as an "expansion" pass on math dialect, converting it to std.constant, std.addf and math.log that are already handled by further lowerings.

Wed, Mar 17, 4:00 AM · Restricted Project
ftynse added a comment to D98764: [mlir] Fix Python bindings tests failure in Debug mode after D98474.

I don't understand this change. What are the other, non-float types that are passed here? Why shouldn't we just assert here (having a FloatAttr expect a FloatType sounds reasonable)?

Wed, Mar 17, 3:32 AM · Restricted Project
ftynse accepted D98742: [mlir][amx] regression test for tile-muli (all zero/sign-extension combinations).
Wed, Mar 17, 3:27 AM · Restricted Project
ftynse accepted D98727: [mlir][cpu-runner] register all llvm ir dialects.
Wed, Mar 17, 3:25 AM · Restricted Project
ftynse accepted D98725: [mlir][llvm] Pass struct results as parameter in c wrapper..
Wed, Mar 17, 3:25 AM · Restricted Project

Tue, Mar 16

ftynse accepted D98723: [mlir][amx] reformatted examples.
Tue, Mar 16, 9:49 AM · Restricted Project
ftynse added a comment to D98662: [mlir] Add lowering from math::Log1p to LLVM.

I wonder if this is something that should be instead implemented as an "expansion" pass on math dialect, converting it to std.constant, std.addf and math.log that are already handled by further lowerings.

Tue, Mar 16, 7:29 AM · Restricted Project
ftynse accepted D98680: [mlir][amx] blocked tilezero integration test.
Tue, Mar 16, 1:18 AM · Restricted Project

Mon, Mar 15

ftynse committed rGb868a3edad9d: [mlir] fix SPIR-V CPU and Vulkan runners after… (authored by ftynse).
[mlir] fix SPIR-V CPU and Vulkan runners after…
Mon, Mar 15, 10:37 AM
ftynse committed rG0aceb61665da: [mlir] make memref.cast implement ViewLikeOpInterface (authored by ftynse).
[mlir] make memref.cast implement ViewLikeOpInterface
Mon, Mar 15, 9:22 AM
ftynse committed rG7aa6f3aa0c86: [mlir] fix integration tests post e2310704d890ad252aeb1ca28b4b84d29514b1d1 (authored by ftynse).
[mlir] fix integration tests post e2310704d890ad252aeb1ca28b4b84d29514b1d1
Mon, Mar 15, 6:41 AM
ftynse committed rGe82a30bdce69: [mlir] enable Python bindings for the MemRef dialect (authored by ftynse).
[mlir] enable Python bindings for the MemRef dialect
Mon, Mar 15, 6:08 AM
ftynse committed rG0fb4a201c098: [mlir] fix shared-lib build fallout of e2310704d890ad252aeb1ca28b4b84d29514b1d1 (authored by ftynse).
[mlir] fix shared-lib build fallout of e2310704d890ad252aeb1ca28b4b84d29514b1d1
Mon, Mar 15, 5:42 AM
ftynse added a comment to D98624: [mlir] Add sparse linalg.dot to LLVMAVX512 translation test..

LLVMAVX512 no longer exists, please just use AVX512 in names

Mon, Mar 15, 3:24 AM · Restricted Project
ftynse committed rGa88371490dae: [mlir] better formatting in interface docs (authored by ftynse).
[mlir] better formatting in interface docs
Mon, Mar 15, 3:12 AM
ftynse committed rG03085156ec63: [mlir] fix cmake for generating data layout documentation (authored by ftynse).
[mlir] fix cmake for generating data layout documentation
Mon, Mar 15, 3:02 AM
ftynse added a comment to D98609: [Canonicalizer] Process regions top-down instead of bottom up & reuse existing constants..

Here's the list of broken tests

Mon, Mar 15, 2:34 AM · Restricted Project
ftynse added a comment to D98609: [Canonicalizer] Process regions top-down instead of bottom up & reuse existing constants..

This introduced a memory error and had to be rolled back. The error is visible under ASAN on several tests, here's mlir-opt -split-input-file -convert-linalg-to-spirv -canonicalize -verify-diagnostics mlir/test/Conversion/LinalgToSPIRV/linalg-to-spirv.mlir for example.

Mon, Mar 15, 2:30 AM · Restricted Project
ftynse added a reverting change for rGb5d9a3c92358: [Canonicalizer] Process regions top-down instead of bottom up & reuse existing…: rG40d8e4d3f992: Revert "[Canonicalizer] Process regions top-down instead of bottom up & reuse….
Mon, Mar 15, 2:28 AM
ftynse committed rG40d8e4d3f992: Revert "[Canonicalizer] Process regions top-down instead of bottom up & reuse… (authored by ftynse).
Revert "[Canonicalizer] Process regions top-down instead of bottom up & reuse…
Mon, Mar 15, 2:28 AM
ftynse added a reverting change for D98609: [Canonicalizer] Process regions top-down instead of bottom up & reuse existing constants.: rG40d8e4d3f992: Revert "[Canonicalizer] Process regions top-down instead of bottom up & reuse….
Mon, Mar 15, 2:28 AM · Restricted Project
ftynse accepted D92327: [MLIR][OpenMP] Pretty printer and parser for omp.wsloop.
Mon, Mar 15, 1:43 AM · Restricted Project

Mar 13 2021

ftynse added a comment to D98485: [mlir] fix a memory leak in NestedPattern.

Thanks!

Do we relies on the owning behavior of std::function for users of NestedPattern or could we switch it to function_ref?

Mar 13 2021, 2:27 AM · Restricted Project

Mar 12 2021

ftynse committed rG4affd0c40ecc: [mlir] fix a memory leak in NestedPattern (authored by ftynse).
[mlir] fix a memory leak in NestedPattern
Mar 12 2021, 9:52 AM
ftynse closed D98485: [mlir] fix a memory leak in NestedPattern.
Mar 12 2021, 9:52 AM · Restricted Project
ftynse requested review of D98525: [mlir] forward data layout query to scoping op in absence of specification.
Mar 12 2021, 9:37 AM · Restricted Project
ftynse requested review of D98524: [mlir] provide a version of data layout size hooks in bits.
Mar 12 2021, 9:36 AM · Restricted Project
ftynse updated the diff for D98500: [mlir] support data layout specs on ModuleOp.

rebase

Mar 12 2021, 9:36 AM · Restricted Project