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evgeny777 (Eugene Leviant)
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User Since
Sep 1 2015, 3:36 AM (268 w, 3 d)

Recent Activity

Today

evgeny777 added a comment to D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .

(paranoia level).
Are we sure that the lowering of MachineInstr to MCInst is preserving the operand sequence? Can it be that the immediate is at position 4 for the MCInst only?
I have no idea how an ldrbt looks like as a MachineInstr. The original check should have triggered an assertion too for MachineInstr then...

Fri, Oct 23, 9:52 AM · Restricted Project
evgeny777 added a comment to D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .

Should it always have been checking operand 4 then? I think that makes sense

Fri, Oct 23, 8:48 AM · Restricted Project
evgeny777 updated the diff for D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .

Uploaded diff with full context

Fri, Oct 23, 8:09 AM · Restricted Project
evgeny777 updated the diff for D90045: [ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate.

@andreadb Looks like I updated wrong diff last time, sorry. Addressed comments

Fri, Oct 23, 8:06 AM · Restricted Project
evgeny777 updated the diff for D90045: [ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate.

Rebased and added context

Fri, Oct 23, 7:23 AM · Restricted Project
evgeny777 requested review of D90045: [ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate.
Fri, Oct 23, 7:09 AM · Restricted Project
evgeny777 committed rGb651ecfb726f: [llvm-mca] Extend cortex-a57 memory instructions test (authored by evgeny777).
[llvm-mca] Extend cortex-a57 memory instructions test
Fri, Oct 23, 7:03 AM
evgeny777 updated the diff for D90029: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate.

Simplified

Fri, Oct 23, 6:32 AM · Restricted Project
evgeny777 added inline comments to D90029: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate.
Fri, Oct 23, 5:00 AM · Restricted Project
evgeny777 requested review of D90029: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate.
Fri, Oct 23, 4:59 AM · Restricted Project
evgeny777 committed rGcb86522c9450: [ARM][SchedModels] Convert IsR1P0AndLaterPred to MCSchedPredicate. NFC (authored by evgeny777).
[ARM][SchedModels] Convert IsR1P0AndLaterPred to MCSchedPredicate. NFC
Fri, Oct 23, 4:28 AM
evgeny777 closed D90017: [ARM][SchedModels] Convert IsR1P0AndLaterPred to MCSchedPredicate. NFC.
Fri, Oct 23, 4:28 AM · Restricted Project
evgeny777 requested review of D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .
Fri, Oct 23, 4:21 AM · Restricted Project
evgeny777 requested review of D90017: [ARM][SchedModels] Convert IsR1P0AndLaterPred to MCSchedPredicate. NFC.
Fri, Oct 23, 2:52 AM · Restricted Project
evgeny777 committed rGffc0f577dac7: [llvm-mca] Add test for cortex-a57 NEON instructions (authored by evgeny777).
[llvm-mca] Add test for cortex-a57 NEON instructions
Fri, Oct 23, 12:56 AM
evgeny777 committed rG7a78073be764: [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate (authored by evgeny777).
[ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate
Fri, Oct 23, 12:34 AM
evgeny777 closed D89957: [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate.
Fri, Oct 23, 12:34 AM · Restricted Project

Yesterday

evgeny777 updated the diff for D89957: [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate.

Fixed variable names

Thu, Oct 22, 9:52 AM · Restricted Project
evgeny777 updated the diff for D89957: [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate.

Fixed issue with update forms of ldm* instructions

Thu, Oct 22, 9:47 AM · Restricted Project
evgeny777 added inline comments to D89957: [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate.
Thu, Oct 22, 9:31 AM · Restricted Project
evgeny777 added inline comments to D89777: [TableGen][SchedModels] Fix read/write variant substitution.
Thu, Oct 22, 8:18 AM · Restricted Project
evgeny777 committed rGed6a91f4567e: [ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate (authored by evgeny777).
[ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate
Thu, Oct 22, 8:03 AM
evgeny777 closed D89939: [ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate.
Thu, Oct 22, 8:03 AM · Restricted Project
evgeny777 added inline comments to D89957: [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate.
Thu, Oct 22, 6:41 AM · Restricted Project
evgeny777 requested review of D89957: [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate.
Thu, Oct 22, 6:36 AM · Restricted Project
evgeny777 committed rG088f3c83cc8f: [llvm-mca] Add few ldm* instructions to cortex-a57 test case (authored by evgeny777).
[llvm-mca] Add few ldm* instructions to cortex-a57 test case
Thu, Oct 22, 6:22 AM
evgeny777 requested review of D89939: [ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate.
Thu, Oct 22, 2:15 AM · Restricted Project
evgeny777 committed rGefcb3952e0e9: [llvm-mca] Improve test case (authored by evgeny777).
[llvm-mca] Improve test case
Thu, Oct 22, 2:08 AM

Wed, Oct 21

evgeny777 committed rGbf9edcb6fda7: [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate (authored by evgeny777).
[ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate
Wed, Oct 21, 10:50 AM
evgeny777 closed D89876: [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate.
Wed, Oct 21, 10:50 AM · Restricted Project
evgeny777 updated the diff for D89876: [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate.

Addressed

Wed, Oct 21, 9:38 AM · Restricted Project
evgeny777 added inline comments to D89876: [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate.
Wed, Oct 21, 9:35 AM · Restricted Project
evgeny777 updated the diff for D89876: [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate.

@andreadb Makes sense. Let's try AArch64-like approach for this case. I've updated patch to handle just IsLdrAm3RegOffPred

Wed, Oct 21, 8:14 AM · Restricted Project
evgeny777 requested review of D89876: [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate.
Wed, Oct 21, 5:54 AM · Restricted Project
evgeny777 committed rG9f5ece63ce62: [llvm-mca] Add test for cortex-a57 memory instructions (authored by evgeny777).
[llvm-mca] Add test for cortex-a57 memory instructions
Wed, Oct 21, 5:10 AM

Tue, Oct 20

evgeny777 requested review of D89777: [TableGen][SchedModels] Fix read/write variant substitution.
Tue, Oct 20, 2:17 AM · Restricted Project
evgeny777 committed rG991e86156c88: [ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicate (authored by evgeny777).
[ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicate
Tue, Oct 20, 1:15 AM
evgeny777 closed D89460: [ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicate.
Tue, Oct 20, 1:15 AM · Restricted Project

Mon, Oct 19

evgeny777 updated the diff for D89460: [ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicate.

Addressed.
@dmgreen There is no predicate for basic (w/o shift) moves in A57 model, that's why mvneq is not touched.

Mon, Oct 19, 5:13 AM · Restricted Project
evgeny777 updated the diff for D89460: [ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicate.

Rebased

Mon, Oct 19, 2:02 AM · Restricted Project
evgeny777 abandoned D89458: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate.

D89553 was pushed instead

Mon, Oct 19, 2:00 AM · Restricted Project
evgeny777 committed rG8a7ca143f8bd: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate (authored by evgeny777).
[ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate
Mon, Oct 19, 1:39 AM
evgeny777 closed D89553: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate (alternative approach).
Mon, Oct 19, 1:39 AM · Restricted Project
evgeny777 abandoned D89575: Change target for sched-aliases.td test case.

@Paul-C-Anagnostopoulos I've removed the test completely. Closing this.

Mon, Oct 19, 1:05 AM · Restricted Project
evgeny777 committed rGf8b04e0653f1: [TableGen] Remove test case (authored by evgeny777).
[TableGen] Remove test case
Mon, Oct 19, 1:04 AM
evgeny777 closed D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant.
Mon, Oct 19, 1:04 AM · Restricted Project

Sat, Oct 17

evgeny777 added a comment to D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant.

If you are happy with the mca test showing the changes, the other test could be removed if it's causing more trouble than it's worth?

Sat, Oct 17, 12:30 AM · Restricted Project

Fri, Oct 16

evgeny777 requested review of D89575: Change target for sched-aliases.td test case.
Fri, Oct 16, 11:23 AM · Restricted Project
evgeny777 added a comment to D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant.

I do wish there was a faster way to test what you're testing.

Fri, Oct 16, 10:46 AM · Restricted Project
evgeny777 added a comment to D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant.

error: command failed with exit status: 2147483651

Fri, Oct 16, 8:54 AM · Restricted Project
evgeny777 added a comment to D89458: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate.

Thanks! I've created D89553 for this

Fri, Oct 16, 7:39 AM · Restricted Project
evgeny777 requested review of D89553: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate (alternative approach).
Fri, Oct 16, 7:39 AM · Restricted Project
evgeny777 added a comment to D89458: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate.

The main problem in your case was that CheckFunctionPredicate is not very good because it assumes a single operand in input to the function (i.e. a MachineInstr/MCInst operand).

Fri, Oct 16, 2:13 AM · Restricted Project
evgeny777 updated the diff for D89458: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate.

Removed commented line of code

Fri, Oct 16, 1:08 AM · Restricted Project
evgeny777 added inline comments to D89458: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate.
Fri, Oct 16, 12:11 AM · Restricted Project

Thu, Oct 15

evgeny777 requested review of D89460: [ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicate.
Thu, Oct 15, 6:27 AM · Restricted Project
evgeny777 updated the diff for D89458: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate.

Removed wrongly added file from diff

Thu, Oct 15, 5:49 AM · Restricted Project
evgeny777 requested review of D89458: [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate.
Thu, Oct 15, 5:21 AM · Restricted Project

Tue, Oct 13

evgeny777 committed rG2ad82b0ed1b4: [ARM.td] Make instruction definitions visible to sched models (authored by evgeny777).
[ARM.td] Make instruction definitions visible to sched models
Tue, Oct 13, 11:59 PM
evgeny777 closed D89308: [ARM.td] Make instruction definitions visible to sched models.
Tue, Oct 13, 11:59 PM · Restricted Project
evgeny777 committed rG836d0addee4a: Fix Windows/MSVC build after 6e56046f65 (authored by evgeny777).
Fix Windows/MSVC build after 6e56046f65
Tue, Oct 13, 5:25 AM
evgeny777 requested review of D89308: [ARM.td] Make instruction definitions visible to sched models.
Tue, Oct 13, 4:14 AM · Restricted Project
evgeny777 added inline comments to D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant.
Tue, Oct 13, 3:08 AM · Restricted Project
evgeny777 committed rG6e56046f65c0: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant (authored by evgeny777).
[TableGen][SchedModels] Fix aliasing of SchedWriteVariant
Tue, Oct 13, 3:05 AM
evgeny777 closed D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant.
Tue, Oct 13, 3:05 AM · Restricted Project

Mon, Oct 12

evgeny777 updated the diff for D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant.

Addressed comments

Mon, Oct 12, 3:14 AM · Restricted Project
evgeny777 added inline comments to D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant.
Mon, Oct 12, 3:14 AM · Restricted Project
evgeny777 added inline comments to D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant.
Mon, Oct 12, 3:12 AM · Restricted Project
evgeny777 committed rG7102793065f2: Add test for cortex-a57/ARM sched model. NFC (authored by evgeny777).
Add test for cortex-a57/ARM sched model. NFC
Mon, Oct 12, 2:50 AM
evgeny777 accepted D87970: [ThinLTO] Avoid temporaries when loading global decl attachment metadata.

LGTM

Mon, Oct 12, 1:27 AM · Restricted Project

Fri, Oct 9

evgeny777 updated the diff for D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant.

Reduced test case

Fri, Oct 9, 9:08 AM · Restricted Project
evgeny777 added a reviewer for D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant: SjoerdMeijer.
Fri, Oct 9, 7:49 AM · Restricted Project
evgeny777 updated the diff for D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant.

Patch also fixes Cortex-A57 model for sxth/uxth/sxtab/uxtab instruction family. Added test case.

Fri, Oct 9, 7:49 AM · Restricted Project
evgeny777 requested review of D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant.
Fri, Oct 9, 3:43 AM · Restricted Project

Sep 21 2020

evgeny777 added a comment to D46884: [AArch64] Cortex-A55 scheduler model.

@SjoerdMeijer

sounds like you've got your environment all setup. Would it be easy for you to quickly test the changes that you suggested earlier?

Sep 21 2020, 10:17 AM · Restricted Project
evgeny777 accepted D87970: [ThinLTO] Avoid temporaries when loading global decl attachment metadata.

LGTM with nits

Sep 21 2020, 8:36 AM · Restricted Project
evgeny777 added inline comments to D87970: [ThinLTO] Avoid temporaries when loading global decl attachment metadata.
Sep 21 2020, 4:01 AM · Restricted Project

Sep 20 2020

evgeny777 added a comment to D46884: [AArch64] Cortex-A55 scheduler model.

@flyingforyou There are numerous places where latencies are different from those in arm_cortex_a55_software_optimization_guide_v2.pdf. Values in the guide seems to be correct, at least they match my measurements on real piece of hardware.
Also there are some forwarding paths not listed by model

Sep 20 2020, 11:30 PM · Restricted Project

Sep 12 2020

evgeny777 committed rG2e61cd1295e0: [MachineScheduler] Fix operand scheduling for pre/post-increment loads (authored by evgeny777).
[MachineScheduler] Fix operand scheduling for pre/post-increment loads
Sep 12 2020, 6:53 AM
evgeny777 closed D87557: [AArch64][MachineScheduler] Fix operand scheduling for pre/post-increment loads.
Sep 12 2020, 6:53 AM · Restricted Project
evgeny777 added a reviewer for D87557: [AArch64][MachineScheduler] Fix operand scheduling for pre/post-increment loads: dmgreen.
Sep 12 2020, 6:01 AM · Restricted Project
evgeny777 updated the diff for D87557: [AArch64][MachineScheduler] Fix operand scheduling for pre/post-increment loads.

@dmgreen Thx, I've updated the diff.

Sep 12 2020, 6:01 AM · Restricted Project
evgeny777 requested review of D87557: [AArch64][MachineScheduler] Fix operand scheduling for pre/post-increment loads.
Sep 12 2020, 5:20 AM · Restricted Project

Sep 11 2020

evgeny777 abandoned D69331: [LegacyPM] Port CGProfile pass.
Sep 11 2020, 12:58 AM · Restricted Project

Sep 10 2020

evgeny777 added inline comments to D46884: [AArch64] Cortex-A55 scheduler model.
Sep 10 2020, 3:07 AM · Restricted Project

Sep 2 2020

evgeny777 added a comment to D86905: Flush bitcode incrementally for LTO output.

Our case is a bit different. Given a 512M incremental flush threshold, I tested an LTO built that outputs a 5G bitcode file. The BackpatchWord is called 16,613,927 times, among which only 12 needs disk seek. Plus, each access visits 4-8 bytes on a page, and all visited pages are far away from each other. It is likely that the pages are not cached, and need to load anyway, and after a load, our code does not access enough data on a page to 'cancel' the page fault cost. So its cost could be very similar to seek.

Sep 2 2020, 1:53 AM · Restricted Project

Sep 1 2020

evgeny777 added inline comments to D86905: Flush bitcode incrementally for LTO output.
Sep 1 2020, 5:19 AM · Restricted Project

Aug 20 2020

evgeny777 committed rGd5b701b9727d: [ThinLTO] Import globals recursively (authored by evgeny777).
[ThinLTO] Import globals recursively
Aug 20 2020, 2:14 AM
evgeny777 closed D73698: [ThinLTO] Import globals recursively.
Aug 20 2020, 2:14 AM · Restricted Project

Aug 1 2020

evgeny777 committed rGe73f5d86f179: [MachineVerifier] Refactor calcRegsPassed. NFC (authored by evgeny777).
[MachineVerifier] Refactor calcRegsPassed. NFC
Aug 1 2020, 2:59 AM
evgeny777 closed D84105: [MachineVerifier] Speed-up verification (up to 10x).
Aug 1 2020, 2:59 AM · Restricted Project

Jul 31 2020

evgeny777 accepted D84985: [ThinLTO] Compile time improvement to propagateAttributes.

The code in computeDeadSymbols will conservatively mark all copies live if any is. See not only the worklist iteration I modified here, but also the code in visit at lines 878-879, and the preserved GUID handling at lines 814-815. So if there is a collision, the colliding values may conservatively be marked live, so the loop in propagateAttributes will handle them. I.e they are either all dead or all live (especially after my fix here which will make the behavior more conservative in the chance case of any alias values that collide with a value marked live during module summary building). Other than the corner case I'm fixing here, this should be a no-op in behavior for that loop in propagateAttributes, which was already skipping all dead values, and which does check if it is a GlobalVarSummary already.

Jul 31 2020, 9:56 AM · Restricted Project
evgeny777 updated the diff for D73698: [ThinLTO] Import globals recursively.

Rebased/improved test case. @tejohnson Can you please look at this? I think that after D73851 compile time regressions are unlikely (at least I don't see them in LLVM test suite)

Jul 31 2020, 9:02 AM · Restricted Project
evgeny777 added a comment to D84985: [ThinLTO] Compile time improvement to propagateAttributes.

I made a smaller efficiency improvement (no measurable impact) to skip all summaries for a VI if the first copy is dead. I added an assert to ensure that all copies are dead if any is....

Jul 31 2020, 5:43 AM · Restricted Project
evgeny777 updated the diff for D84105: [MachineVerifier] Speed-up verification (up to 10x).

@arsenm

This LGTM, but why is the verifier figuring out how to do its own RPO?

Jul 31 2020, 4:08 AM · Restricted Project

Jul 24 2020

evgeny777 added a comment to D84105: [MachineVerifier] Speed-up verification (up to 10x).

Can anyone look at this, please? Thanks

Jul 24 2020, 10:23 AM · Restricted Project

Jul 23 2020

evgeny777 committed rGdc619f3d7a97: [CodeGen][TargetPassConfig] Add unreachable-mbb-elimination pass explicitly (authored by evgeny777).
[CodeGen][TargetPassConfig] Add unreachable-mbb-elimination pass explicitly
Jul 23 2020, 8:05 AM
evgeny777 closed D84228: [CodeGen][TargetPassConfig] Add unreachable-mbb-elimination pass explicitly.
Jul 23 2020, 8:05 AM · Restricted Project

Jul 22 2020

evgeny777 added a comment to D84228: [CodeGen][TargetPassConfig] Add unreachable-mbb-elimination pass explicitly.

Does this mean that we run UnreachableMachineBlockElimID twice?

Jul 22 2020, 1:58 AM · Restricted Project

Jul 21 2020

Herald added a project to D84228: [CodeGen][TargetPassConfig] Add unreachable-mbb-elimination pass explicitly: Restricted Project.
Jul 21 2020, 3:32 AM · Restricted Project