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aykevl (Ayke)
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User Since
Apr 25 2018, 9:12 AM (154 w, 3 d)

Recent Activity

Yesterday

aykevl added inline comments to D76526: Add an algorithm for performing "optimal" layout of a struct..
Sat, Apr 10, 3:24 PM · Restricted Project

Mar 9 2021

aykevl added a comment to D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

@andreisfr awesome! Thanks a lot!

Mar 9 2021, 2:28 PM · Restricted Project

Mar 4 2021

aykevl added a comment to D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

Also, there is an emulator here: https://github.com/espressif/qemu/wiki
I have successfully used it in the past. Noting it here as it can make backend review/development easier for those who don't have the hardware.

Mar 4 2021, 4:31 PM · Restricted Project
aykevl added a reviewer for D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description.: aykevl.
Mar 4 2021, 6:45 AM · Restricted Project
aykevl added a comment to D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

@andreisfr any update on this?

Mar 4 2021, 6:45 AM · Restricted Project
aykevl added a comment to D96394: [AVR] Improve inline assembly.

Yes, I was not aware of the special %A0/%B0 syntax, see my comment above.

Mar 4 2021, 5:16 AM · Restricted Project
aykevl added a comment to D97127: [AVR] Improve 8/16 bit atomic operations.

Do we need a test case to show the right AVR assembly ? Or at least shows that the points #1 and #2 in your comment are fixed.

I think that would imply using hardcoded registers in the test. Is that what you mean?

No. I meant, you have shown a case void atomicadd(_Atomic char *val) and corresponding assembly, and I would like to see the change of the generated assembly by your patch, and wonder if the change can be added as a test case.

Mar 4 2021, 5:13 AM · Restricted Project
aykevl committed rGa1155ae64dc7: [AVR] Fix lifeness issues in the AVR backend (authored by aykevl).
[AVR] Fix lifeness issues in the AVR backend
Mar 4 2021, 5:05 AM
aykevl closed D97172: [AVR] Fix lifeness issues in the AVR backend.
Mar 4 2021, 5:04 AM · Restricted Project
aykevl added a comment to D96394: [AVR] Improve inline assembly.

Oh, now I understand. Apparently there is a %A0/%B0 syntax that I've never seen before in any documentation with which you can select parts of a register.
Yes, this looks good to me, although perhaps @dylanmckay should also take a look?

Mar 4 2021, 4:29 AM · Restricted Project
aykevl added a comment to D96394: [AVR] Improve inline assembly.

Oh, I missed this comment.

Mar 4 2021, 3:39 AM · Restricted Project
aykevl added a comment to D96394: [AVR] Improve inline assembly.

I don't really understand what you're doing here. For example:

Mar 4 2021, 3:38 AM · Restricted Project

Mar 3 2021

aykevl updated the diff for D96677: [AVR] Expand large shifts early in IR.
  • fixes so that shl i32 undef, undef doesn't crash
Mar 3 2021, 2:51 PM · Restricted Project
aykevl added a reviewer for D96853: [clang][AVR] Support variable decorator '__flash': rjmccall.
Mar 3 2021, 7:02 AM · Restricted Project
aykevl updated the diff for D97172: [AVR] Fix lifeness issues in the AVR backend.

Re-upload (without changes) to try to get the buildbot working...

Mar 3 2021, 6:43 AM · Restricted Project
aykevl added a comment to D97131: [AVR] Fix expansion of NEGW.

Ok, committed.

Mar 3 2021, 6:38 AM · Restricted Project
aykevl committed rG15f495c0bcb2: [AVR] Fix def state of operands (authored by aykevl).
[AVR] Fix def state of operands
Mar 3 2021, 6:36 AM
aykevl committed rGbbfef8ac952b: [AVR] Fix expansion of NEGW (authored by aykevl).
[AVR] Fix expansion of NEGW
Mar 3 2021, 6:36 AM
aykevl committed rG4f6d7985d47a: [AVR] Add register aliases XL, YH, etc (authored by aykevl).
[AVR] Add register aliases XL, YH, etc
Mar 3 2021, 6:36 AM
aykevl closed D97159: [AVR] Fix def state of operands.
Mar 3 2021, 6:36 AM · Restricted Project
aykevl closed D97131: [AVR] Fix expansion of NEGW.
Mar 3 2021, 6:36 AM · Restricted Project
aykevl closed D96492: [AVR] Add register aliases XL, YH, etc.
Mar 3 2021, 6:36 AM · Restricted Project
aykevl added a comment to D97127: [AVR] Improve 8/16 bit atomic operations.

Do we need a test case to show the right AVR assembly ? Or at least shows that the points #1 and #2 in your comment are fixed.

Mar 3 2021, 6:27 AM · Restricted Project
aykevl updated the diff for D96969: [AVR] Only support sp, r0 and r1 in llvm.read_register.
  • fix lint warning
Mar 3 2021, 6:15 AM · Restricted Project
aykevl updated the diff for D96677: [AVR] Expand large shifts early in IR.
  • fix lint warnings
Mar 3 2021, 6:11 AM · Restricted Project
aykevl requested review of D97853: [AVR] Do not chain stores in call frame setup.
Mar 3 2021, 6:08 AM · Restricted Project
aykevl updated the summary of D97815: [AVR] Remove redundant dynalloca SP save/restore pass.
Mar 3 2021, 4:58 AM · Restricted Project

Mar 2 2021

aykevl requested review of D97745: [AVR] Set R31R30 as clobbered after ADJCALLSTACKUP.

Nevermind, that won't work. This looks like the right way forward.

Mar 2 2021, 4:09 PM · Restricted Project
aykevl retitled D97745: [AVR] Set R31R30 as clobbered after ADJCALLSTACKUP from [AVR] Set R31R30 as clobbered after ADJCALLSTACKDOWN to [AVR] Set R31R30 as clobbered after ADJCALLSTACKUP.
Mar 2 2021, 4:08 PM · Restricted Project
aykevl requested review of D97815: [AVR] Remove redundant dynalloca SP save/restore pass.
Mar 2 2021, 4:00 PM · Restricted Project
aykevl planned changes to D97745: [AVR] Set R31R30 as clobbered after ADJCALLSTACKUP.

I think there is a better way to do this: by always using a frame pointer when a function needs a call frame. That would simplify the code a lot.

Mar 2 2021, 6:19 AM · Restricted Project

Mar 1 2021

aykevl added a comment to D97131: [AVR] Fix expansion of NEGW.

Why not commit it? I think this bug fix should be fixed ASAP.

Mar 1 2021, 5:44 PM · Restricted Project
aykevl added a comment to D97669: [clang][AVR] Add avr-libc/include to clang system include paths.

Looks reasonable to me. But again, I would like this to be reviewed also by someone familiar with the internals of Clang (I'm not).

Mar 1 2021, 4:46 PM · Restricted Project
aykevl added a comment to D97172: [AVR] Fix lifeness issues in the AVR backend.

We need to fix the build failure before commit this patch.

Mar 1 2021, 4:33 PM · Restricted Project
aykevl requested review of D97745: [AVR] Set R31R30 as clobbered after ADJCALLSTACKUP.
Mar 1 2021, 4:30 PM · Restricted Project

Feb 28 2021

aykevl added a comment to D78581: [AVR] Remove faulty stack pushing behavior.

I have a fix ready and will post a patch soon.

Feb 28 2021, 3:56 PM · Restricted Project

Feb 27 2021

aykevl added a comment to D78581: [AVR] Remove faulty stack pushing behavior.

I have found that my fix isn't complete, it can result in broken code because the register allocator does not know that R31R30 is in use between ADJCALLSTACKDOWN and STDWSPQRr and might use it as the value operand for the STDWSPQRr instruction.

Feb 27 2021, 7:24 AM · Restricted Project

Feb 24 2021

aykevl added a comment to D96506: [AVR] Optimize 16-bit shifts.

I should have explained this a while ago, sorry for neglecting this.

Feb 24 2021, 9:11 AM · Restricted Project

Feb 22 2021

aykevl added a comment to D97159: [AVR] Fix def state of operands.

Thank you for the review!

Feb 22 2021, 4:55 PM · Restricted Project

Feb 21 2021

aykevl updated the diff for D97159: [AVR] Fix def state of operands.
Feb 21 2021, 5:03 PM · Restricted Project
aykevl abandoned D97171: [AVR] Fix operands for ASRW8Rd.

Let's merge this with D97159.

Feb 21 2021, 5:02 PM · Restricted Project
aykevl requested review of D97172: [AVR] Fix lifeness issues in the AVR backend.
Feb 21 2021, 4:56 PM · Restricted Project
aykevl requested review of D97171: [AVR] Fix operands for ASRW8Rd.
Feb 21 2021, 4:47 PM · Restricted Project
aykevl updated the summary of D97159: [AVR] Fix def state of operands.
Feb 21 2021, 11:29 AM · Restricted Project
aykevl requested review of D97159: [AVR] Fix def state of operands.
Feb 21 2021, 11:28 AM · Restricted Project
aykevl added a comment to D96677: [AVR] Expand large shifts early in IR.

I am not sure such a specific pass is needed. Why __ashlsi3 is not called in other backends? Is there a config flag/option to prevent calling __ashlsi3 ?

Feb 21 2021, 9:21 AM · Restricted Project
aykevl added a reviewer for D96969: [AVR] Only support sp, r0 and r1 in llvm.read_register: benshi001.
Feb 21 2021, 6:22 AM · Restricted Project
aykevl added inline comments to D97131: [AVR] Fix expansion of NEGW.
Feb 21 2021, 3:35 AM · Restricted Project

Feb 20 2021

aykevl added a comment to D96853: [clang][AVR] Support variable decorator '__flash'.

I am not very familiar with Clang so I can't say much about it. Although I wonder whether a macro is the right way to implement this? Is there something similar in other targets? (GPUs tend to have lots of address spaces, you could take a look there).

Feb 20 2021, 5:03 PM · Restricted Project
aykevl updated the summary of D97131: [AVR] Fix expansion of NEGW.
Feb 20 2021, 4:45 PM · Restricted Project
aykevl requested review of D97131: [AVR] Fix expansion of NEGW.
Feb 20 2021, 4:39 PM · Restricted Project
aykevl updated the diff for D96677: [AVR] Expand large shifts early in IR.
  • fix lint checks (hopefully)
  • simplify pass a bit, with suggestions from @benshi001
  • use update_test_checks.py for the test
Feb 20 2021, 4:08 PM · Restricted Project
aykevl added inline comments to D96677: [AVR] Expand large shifts early in IR.
Feb 20 2021, 4:07 PM · Restricted Project
aykevl updated the diff for D96969: [AVR] Only support sp, r0 and r1 in llvm.read_register.
  • fix lint warnings
Feb 20 2021, 3:12 PM · Restricted Project
aykevl updated the diff for D96957: [AVR] Fix rotate instructions.
  • remove misleading comment
  • adjust to fix lint warnings
Feb 20 2021, 3:08 PM · Restricted Project
aykevl added inline comments to D96957: [AVR] Fix rotate instructions.
Feb 20 2021, 3:07 PM · Restricted Project
aykevl added inline comments to D96492: [AVR] Add register aliases XL, YH, etc.
Feb 20 2021, 2:41 PM · Restricted Project
aykevl updated the summary of D97127: [AVR] Improve 8/16 bit atomic operations.
Feb 20 2021, 2:29 PM · Restricted Project
aykevl requested review of D97127: [AVR] Improve 8/16 bit atomic operations.
Feb 20 2021, 2:25 PM · Restricted Project

Feb 18 2021

aykevl updated the summary of D96969: [AVR] Only support sp, r0 and r1 in llvm.read_register.
Feb 18 2021, 9:18 AM · Restricted Project
aykevl requested review of D96969: [AVR] Only support sp, r0 and r1 in llvm.read_register.
Feb 18 2021, 9:17 AM · Restricted Project
aykevl updated the diff for D96957: [AVR] Fix rotate instructions.
  • match avr-gcc output (bst, ror, bld)
  • fix issue with the BLD instruction
Feb 18 2021, 8:01 AM · Restricted Project
aykevl planned changes to D96957: [AVR] Fix rotate instructions.

Oops this is not correct.

Feb 18 2021, 7:26 AM · Restricted Project
aykevl requested review of D96957: [AVR] Fix rotate instructions.
Feb 18 2021, 7:22 AM · Restricted Project

Feb 14 2021

aykevl updated the diff for D96677: [AVR] Expand large shifts early in IR.

Oops I uploaded the wrong patch.

Feb 14 2021, 4:12 PM · Restricted Project
aykevl updated the summary of D96677: [AVR] Expand large shifts early in IR.
Feb 14 2021, 4:11 PM · Restricted Project
aykevl requested review of D96677: [AVR] Expand large shifts early in IR.
Feb 14 2021, 4:10 PM · Restricted Project
aykevl added a comment to D96590: [AVR] Fix a bug in 16-bit shifts.

Thank you!
I have created a bug report to include this fix in the LLVM 12 release: https://bugs.llvm.org/show_bug.cgi?id=49176

Feb 14 2021, 6:17 AM · Restricted Project

Feb 13 2021

aykevl accepted D96590: [AVR] Fix a bug in 16-bit shifts.

@benshi001 can you commit it or should I do it for you?

Feb 13 2021, 9:53 AM · Restricted Project
aykevl added a comment to D96590: [AVR] Fix a bug in 16-bit shifts.

Thank you for the quick patch! I have verified locally that this does indeed fix the bug (my AVR tests pass again), so this looks good to me.

Feb 13 2021, 3:13 AM · Restricted Project

Feb 11 2021

aykevl added a comment to D86547: [compiler-rt][builtins] Use c[tl]zsi macro instead of __builtin_c[tl]z.

I checked this, and it seems good to me although I would like someone else to also take a look.

Feb 11 2021, 4:12 PM · Restricted Project
aykevl added a comment to D86546: [compiler-rt][builtins] Use explicitly-sized integer types for LibCalls.

This looks good to me, although I would like someone else to take a look as well. I can confirm that these changes fix an issue on AVR: this patch (together with D86547) make __floatsisf correct on AVR while it would previously do something incorrect.

Feb 11 2021, 3:57 PM · Restricted Project
aykevl added a comment to D90092: [AVR] Optimize 16-bit int shift.

I found at least one code sample that is miscompiled.

Feb 11 2021, 11:55 AM · Restricted Project
aykevl added a comment to D90092: [AVR] Optimize 16-bit int shift.

I've been testing the llvm main branch and I found that this change introduces a miscompilation. I have not yet investigated what exactly is going wrong.

Feb 11 2021, 11:24 AM · Restricted Project
aykevl requested review of D96492: [AVR] Add register aliases XL, YH, etc.
Feb 11 2021, 5:11 AM · Restricted Project

Feb 4 2021

aykevl added a comment to D95891: [ARM] Do not emit ldrexd/strexd on Cortex-M chips.

@SjoerdMeijer thank you for the quick review!

Feb 4 2021, 12:56 PM · Restricted Project
aykevl committed rGaecdf15cc7f8: [ARM] Do not emit ldrexd/strexd on Cortex-M chips (authored by aykevl).
[ARM] Do not emit ldrexd/strexd on Cortex-M chips
Feb 4 2021, 12:56 PM
aykevl closed D95891: [ARM] Do not emit ldrexd/strexd on Cortex-M chips.
Feb 4 2021, 12:56 PM · Restricted Project

Feb 3 2021

aykevl added a comment to D95891: [ARM] Do not emit ldrexd/strexd on Cortex-M chips.

Thanks for the review! I've updated the patch accordingly.

Feb 3 2021, 10:34 AM · Restricted Project
aykevl updated the diff for D95891: [ARM] Do not emit ldrexd/strexd on Cortex-M chips.
  • added comment to shouldExpandAtomicCmpXchgInIR explaining Cortex-M exception
  • added checks for armv8m architecture (which are the same as armv7m)
Feb 3 2021, 10:30 AM · Restricted Project

Feb 2 2021

aykevl updated the summary of D95891: [ARM] Do not emit ldrexd/strexd on Cortex-M chips.
Feb 2 2021, 12:24 PM · Restricted Project
aykevl added a reviewer for D95891: [ARM] Do not emit ldrexd/strexd on Cortex-M chips: dmgreen.
Feb 2 2021, 12:24 PM · Restricted Project
aykevl updated the summary of D95891: [ARM] Do not emit ldrexd/strexd on Cortex-M chips.
Feb 2 2021, 12:17 PM · Restricted Project
aykevl requested review of D95891: [ARM] Do not emit ldrexd/strexd on Cortex-M chips.
Feb 2 2021, 12:14 PM · Restricted Project

Jan 23 2021

aykevl added a comment to D63852: [Clang] Move assembler into a separate file.

Yeah I was wondering the same thing when I saw the failure. Unfortunately such design is a bit outside of my LLVM knowledge. I would just like to use cc1as_main.cpp functionality outside of LLVM without needing to update my copy of cc1as with every LLVM update.

Jan 23 2021, 6:35 AM · Restricted Project
aykevl added a comment to D63852: [Clang] Move assembler into a separate file.

@echristo do you have an idea what's going on or how to fix this? I suspect I'm not including a required dependency or maybe I've put AssemblerInvocation in the wrong directory/library.
I'm not very familiar with CMake or C++ so I'm not sure how to best fix this.

Jan 23 2021, 6:09 AM · Restricted Project
aykevl added a reverting change for rG2325157c0568: [Clang] Move assembler into a separate file: rG0057cc5a215e: Revert "[Clang] Move assembler into a separate file".
Jan 23 2021, 6:07 AM
aykevl committed rG0057cc5a215e: Revert "[Clang] Move assembler into a separate file" (authored by aykevl).
Revert "[Clang] Move assembler into a separate file"
Jan 23 2021, 6:07 AM
aykevl added a reverting change for D63852: [Clang] Move assembler into a separate file: rG0057cc5a215e: Revert "[Clang] Move assembler into a separate file".
Jan 23 2021, 6:07 AM · Restricted Project
aykevl added a comment to D63852: [Clang] Move assembler into a separate file.

Well that didn't quite work. I get errors like this:

Jan 23 2021, 6:07 AM · Restricted Project
aykevl added a comment to D63852: [Clang] Move assembler into a separate file.

Thanks! I have updated this patch to match LLVM main and committed it.

Jan 23 2021, 5:39 AM · Restricted Project
aykevl committed rG2325157c0568: [Clang] Move assembler into a separate file (authored by aykevl).
[Clang] Move assembler into a separate file
Jan 23 2021, 5:38 AM
aykevl closed D63852: [Clang] Move assembler into a separate file.
Jan 23 2021, 5:38 AM · Restricted Project

Nov 3 2020

aykevl added inline comments to D88658: [AVR] Optimize the 16-bit NEGW pseudo instruction.
Nov 3 2020, 5:55 PM · Restricted Project

Oct 31 2020

aykevl added a comment to D86418: [AVR] Improve inline rotate/shift expansions.

Great patch

I made this patch to get more familiar with these inline expansions, in the hope that I can also do the other expansions inline (such as 32-bit shifts).

That would be nice!

Oct 31 2020, 4:05 PM · Restricted Project
aykevl committed rGe03ba2198dbb: [AVR] Improve inline rotate/shift expansions (authored by aykevl).
[AVR] Improve inline rotate/shift expansions
Oct 31 2020, 3:16 PM
aykevl closed D86418: [AVR] Improve inline rotate/shift expansions.
Oct 31 2020, 3:16 PM · Restricted Project
aykevl added a comment to D88410: [clang][AVR] Improve avr-ld command line options.

I haven't verified this all but this looks reasonable to me, at least until a better way is figured out to store MCU specific information in the compiler.

Oct 31 2020, 2:26 PM · Restricted Project
aykevl added a comment to D90092: [AVR] Optimize 16-bit int shift.

See my comment D89047#2366709.
I think this optimization would be implemented better in SelectionDAG instead of using pseudo-instructions. That would also make it possible to optimize things like (short)x << 12.

Oct 31 2020, 2:17 PM · Restricted Project
aykevl added a comment to D89047: [AVR] Optimize 8-bit logic left/right shifts.

The original AVR backend TD is also wrong, that it maps the bswap IR to AVR's swap instruction.

Since the IR bswap is byte level operation, which requires the minimal data type to be at least 16-bit.

But AVR's swap performs on half-byte level.

Oct 31 2020, 2:13 PM · Restricted Project