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avieira (Andre Vieira)
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User Since
Jan 19 2017, 12:49 AM (214 w, 4 d)

Recent Activity

Thu, Feb 4

avieira added a comment to D92235: [ARM] Turn pred_cast(xor(x, -1)) into xor(pred_cast(x), -1).

Accidentally linked my commit of https://reviews.llvm.org/D92236 to this revision. Apologies.

Thu, Feb 4, 4:18 AM · Restricted Project
avieira closed D92236: [LIBC] Add optimized memcpy routine for AArch64.

I've committed the patch in https://reviews.llvm.org/rG369f7de3135a517a69c45084d4b175f7b0d5e6f5 but it seems when copying the revision link I may have hit ctrl + x in vim and linked it to D92235 :(

Thu, Feb 4, 4:17 AM · Restricted Project

Wed, Feb 3

avieira committed rG369f7de3135a: [LIBC] Add optimized memcpy routine for AArch64 (authored by avieira).
[LIBC] Add optimized memcpy routine for AArch64
Wed, Feb 3, 1:32 AM

Jan 24 2021

avieira committed rG8fbc1437c605: [AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L (authored by avieira).
[AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L
Jan 24 2021, 11:59 PM
avieira closed D95218: [AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L.
Jan 24 2021, 11:58 PM · Restricted Project

Jan 22 2021

avieira added a comment to D95218: [AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L.

Thanks. I'll wait till Monday to commit. To avoid Friday hit-and-run's ;)

Jan 22 2021, 9:02 AM · Restricted Project
avieira added inline comments to D95218: [AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L.
Jan 22 2021, 8:27 AM · Restricted Project
avieira updated the diff for D95218: [AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L.

Updated the testcase. Ok to commit?

Jan 22 2021, 8:27 AM · Restricted Project
avieira requested review of D95218: [AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L.
Jan 22 2021, 2:16 AM · Restricted Project

Jan 20 2021

avieira updated the diff for D92236: [LIBC] Add optimized memcpy routine for AArch64.

So here is an updated version for an optimized memcpy routine for AArch64. This one basically uses the same as the default memcpy, but picks a different block size and alignment for copies > 128.
I also disable tail merging as I found it was leading to worse code. This new memcpy seems to show improvements accross the board for both sweep and distribution benchmarks.

Jan 20 2021, 2:14 AM · Restricted Project

Jan 15 2021

avieira accepted D94770: [libc] CopyAlignedBlocks can now specify alignment on top of block size.

Eh you beat me to it. Had a similar patch I've been measuring and testing. Your's is more complete though :)

Jan 15 2021, 6:43 AM · Restricted Project

Jan 6 2021

avieira added a comment to D93457: [libc] Align src buffer instead of dst buffer.

Sure, LGTM. What is the usual convention for Libc reviewing? Should I 'accept revision' if I agree with it even though I'm not a maintainer?

Jan 6 2021, 2:17 AM · Restricted Project
avieira added a comment to D93457: [libc] Align src buffer instead of dst buffer.

Hi Guillaume,

Jan 6 2021, 2:01 AM · Restricted Project

Dec 17 2020

avieira added inline comments to D92236: [LIBC] Add optimized memcpy routine for AArch64.
Dec 17 2020, 7:29 AM · Restricted Project

Dec 3 2020

avieira added a comment to D92236: [LIBC] Add optimized memcpy routine for AArch64.

Hi Guillaume,

Dec 3 2020, 10:09 AM · Restricted Project

Nov 27 2020

avieira committed rGa4b80efea98f: [AArch64] Define __ARM_FEATURE_{CRC32,ATOMICS} (authored by avieira).
[AArch64] Define __ARM_FEATURE_{CRC32,ATOMICS}
Nov 27 2020, 9:43 AM
avieira closed D91438: [AArch64] Define __ARM_FEATURE_{CRC32,ATOMICS}.
Nov 27 2020, 9:43 AM · Restricted Project
avieira added reviewers for D92236: [LIBC] Add optimized memcpy routine for AArch64: sivachandra, dxf.
Nov 27 2020, 9:31 AM · Restricted Project
avieira requested review of D92236: [LIBC] Add optimized memcpy routine for AArch64.
Nov 27 2020, 9:12 AM · Restricted Project

Nov 16 2020

avieira updated the diff for D91438: [AArch64] Define __ARM_FEATURE_{CRC32,ATOMICS}.

Rebased on top of trunk.

Nov 16 2020, 7:18 AM · Restricted Project

Nov 13 2020

avieira added a reviewer for D91438: [AArch64] Define __ARM_FEATURE_{CRC32,ATOMICS}: t.p.northover.
Nov 13 2020, 9:16 AM · Restricted Project
avieira requested review of D91438: [AArch64] Define __ARM_FEATURE_{CRC32,ATOMICS}.
Nov 13 2020, 9:06 AM · Restricted Project

Jul 13 2020

avieira committed rGc051312eb24d: [libc][benchmark] Add display option to render.py3 (authored by avieira).
[libc][benchmark] Add display option to render.py3
Jul 13 2020, 4:09 AM
avieira closed D83380: [libc][benchmark] Add display option to render.py3.
Jul 13 2020, 4:09 AM · Restricted Project

Jul 9 2020

avieira updated the diff for D83380: [libc][benchmark] Add display option to render.py3.

Hoisted frequency out of invariant loops.

Jul 9 2020, 3:40 AM · Restricted Project

Jul 8 2020

Herald added a project to D83380: [libc][benchmark] Add display option to render.py3: Restricted Project.
Jul 8 2020, 3:54 AM · Restricted Project

Feb 13 2018

avieira committed rL325000: [ARM] Don't print "Requires NEON" error message for M-profile.
[ARM] Don't print "Requires NEON" error message for M-profile
Feb 13 2018, 3:48 AM
avieira closed D43125: [ARM] Don't print "Requires NEON" error message for M-profile.
Feb 13 2018, 3:48 AM

Feb 9 2018

avieira created D43125: [ARM] Don't print "Requires NEON" error message for M-profile.
Feb 9 2018, 6:34 AM

Jan 12 2018

avieira committed rL322361: [ARM] Add codegen for SMMULR, SMMLAR and SMMLSR.
[ARM] Add codegen for SMMULR, SMMLAR and SMMLSR
Jan 12 2018, 1:26 AM
avieira closed D41775: [ARM] Add codegen for SMMULR, SMMLAR and SMMLSR.
Jan 12 2018, 1:26 AM
avieira added inline comments to D41775: [ARM] Add codegen for SMMULR, SMMLAR and SMMLSR.
Jan 12 2018, 1:25 AM
avieira committed rL322360: [ARM] Fix erroneous availability of SMMLS for Armv7-M.
[ARM] Fix erroneous availability of SMMLS for Armv7-M
Jan 12 2018, 1:22 AM
avieira closed D41855: [ARM] Fix erroneous availability of SMMLS for Armv7-M.
Jan 12 2018, 1:22 AM

Jan 9 2018

avieira added inline comments to D41855: [ARM] Fix erroneous availability of SMMLS for Armv7-M.
Jan 9 2018, 7:30 AM
avieira updated the diff for D41855: [ARM] Fix erroneous availability of SMMLS for Armv7-M.
Jan 9 2018, 7:30 AM
avieira added inline comments to D41855: [ARM] Fix erroneous availability of SMMLS for Armv7-M.
Jan 9 2018, 3:40 AM
avieira updated the diff for D41775: [ARM] Add codegen for SMMULR, SMMLAR and SMMLSR.

Split the patch, see fix in: https://reviews.llvm.org/D41855
Also applied other suggested changes.

Jan 9 2018, 2:28 AM
avieira created D41855: [ARM] Fix erroneous availability of SMMLS for Armv7-M.
Jan 9 2018, 2:27 AM

Jan 8 2018

avieira added a comment to D41775: [ARM] Add codegen for SMMULR, SMMLAR and SMMLSR.

Thanks for the comments. The split is definitely a good idea, also I have some questions/feedback on the comments. Ill post a new patch here for the code generation and a separate one for the fix.

Jan 8 2018, 10:32 AM

Jan 5 2018

avieira created D41775: [ARM] Add codegen for SMMULR, SMMLAR and SMMLSR.
Jan 5 2018, 9:39 AM

Nov 13 2017

avieira added a comment to D38175: [ARM] Make sure assembler rejects PC as an operand for VMOV.F16.

Just a nit, why did you call it rGPR2? If this is a noPC/noSP class, than a longer but more meaningful name like rGPRnopcsp would be preferable.

Nov 13 2017, 10:05 AM

Nov 8 2017

avieira added a comment to D38175: [ARM] Make sure assembler rejects PC as an operand for VMOV.F16.

I started working on the first set of changes for this, taking the vmov instructions only. I added a new register class rGPR2 which behaves the way we want for these instructions. However, I ran into a failure in the CodeGen/ARM/fast-isel-align.ll test when it tried to generate the following:
%vreg6<def> = VMOVRS %vreg10, pred:14, pred:%noreg; GPR:%vreg6 SPR:%vreg10

Nov 8 2017, 2:46 AM

Oct 18 2017

avieira committed rL316085: [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode.
[ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode
Oct 18 2017, 7:48 AM
avieira closed D38347: [PATCH][ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode by committing rL316085: [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode.
Oct 18 2017, 7:47 AM

Sep 28 2017

avieira created D38347: [PATCH][ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode.
Sep 28 2017, 2:20 AM

Sep 25 2017

avieira added a comment to D38175: [ARM] Make sure assembler rejects PC as an operand for VMOV.F16.

I took the opportunity to also look at the SP operand. Currently it is not rejected either, and it should for non Armv8-A architectures running in Thumb mode.

Sep 25 2017, 5:03 AM

Sep 22 2017

avieira added a comment to D38175: [ARM] Make sure assembler rejects PC as an operand for VMOV.F16.

All similar VMOVs seem to have the same restriction, maybe we should update the whole lot at the same time?

Sep 22 2017, 8:42 AM
avieira created D38175: [ARM] Make sure assembler rejects PC as an operand for VMOV.F16.
Sep 22 2017, 5:47 AM
avieira committed rL313979: [ARM] Fix assembly and disassembly for VMRS/VMSR.
[ARM] Fix assembly and disassembly for VMRS/VMSR
Sep 22 2017, 5:19 AM
avieira closed D36306: [ARM] Fix assembly and disassembly for VMRS/VMSR by committing rL313979: [ARM] Fix assembly and disassembly for VMRS/VMSR.
Sep 22 2017, 5:19 AM

Sep 21 2017

avieira requested review of D36306: [ARM] Fix assembly and disassembly for VMRS/VMSR.

The new version of the patch hasnt been reviewed.

Sep 21 2017, 8:27 AM

Sep 11 2017

avieira committed rL312908: [ARM] Enable the use of SVC anywhere in an IT block.
[ARM] Enable the use of SVC anywhere in an IT block
Sep 11 2017, 4:12 AM
avieira closed D37374: [PATCH][ARM] Enable the use of SVC anywhere in an IT block by committing rL312908: [ARM] Enable the use of SVC anywhere in an IT block.
Sep 11 2017, 4:12 AM

Sep 1 2017

avieira added a comment to D37374: [PATCH][ARM] Enable the use of SVC anywhere in an IT block.

OK, I will wait a few days to see if there are any objections.

Sep 1 2017, 5:56 AM
avieira updated the diff for D37374: [PATCH][ARM] Enable the use of SVC anywhere in an IT block.

I moved the check into the existing isCall check and updated the comments.

Sep 1 2017, 3:48 AM
avieira updated the diff for D37374: [PATCH][ARM] Enable the use of SVC anywhere in an IT block.

Added bigger diff.

Sep 1 2017, 3:26 AM
avieira created D37374: [PATCH][ARM] Enable the use of SVC anywhere in an IT block.
Sep 1 2017, 2:28 AM

Aug 21 2017

avieira updated the diff for D36306: [ARM] Fix assembly and disassembly for VMRS/VMSR.

Now only access to MVFR2 requires Armv8, both A and M profiles, all other instructions are available for any Arm architecture.

Aug 21 2017, 4:03 AM
avieira reopened D36306: [ARM] Fix assembly and disassembly for VMRS/VMSR.

Reopening as this was reverted earlier, submitting new version.

Aug 21 2017, 4:01 AM

Aug 7 2017

avieira committed rL310243: [ARM] Fix assembly and disassembly for VMRS/VMSR.
[ARM] Fix assembly and disassembly for VMRS/VMSR
Aug 7 2017, 1:42 AM
avieira closed D36306: [ARM] Fix assembly and disassembly for VMRS/VMSR by committing rL310243: [ARM] Fix assembly and disassembly for VMRS/VMSR.
Aug 7 2017, 1:42 AM
avieira updated subscribers of D36306: [ARM] Fix assembly and disassembly for VMRS/VMSR.
Aug 7 2017, 1:04 AM

Aug 4 2017

avieira created D36306: [ARM] Fix assembly and disassembly for VMRS/VMSR.
Aug 4 2017, 4:57 AM

Jun 6 2017

avieira accepted D33931: [ARM] Add curly braces around switch case [NFC].

LGTM, thanks for the patch!

Jun 6 2017, 3:13 AM

Mar 17 2017

avieira committed rL298056: [ARM] Fix triple format in test branch disassemble test.
[ARM] Fix triple format in test branch disassemble test
Mar 17 2017, 2:49 AM
avieira committed rL298055: [ARM] Change tests after fixing branch label for Thumb targets.
[ARM] Change tests after fixing branch label for Thumb targets
Mar 17 2017, 2:49 AM
avieira closed D30987: [ARM] Fix triple format in test branch disassemble test by committing rL298056: [ARM] Fix triple format in test branch disassemble test.
Mar 17 2017, 2:49 AM
avieira closed D30986: [ARM] Change tests after fixing branch label for Thumb targets by committing rL298055: [ARM] Change tests after fixing branch label for Thumb targets.
Mar 17 2017, 2:49 AM

Mar 15 2017

avieira updated subscribers of D30986: [ARM] Change tests after fixing branch label for Thumb targets.
Mar 15 2017, 9:45 AM
avieira created D30987: [ARM] Fix triple format in test branch disassemble test.
Mar 15 2017, 9:45 AM
avieira created D30986: [ARM] Change tests after fixing branch label for Thumb targets.
Mar 15 2017, 9:43 AM

Mar 14 2017

avieira created D30943: [ARM] Fix for branch label dissassembly for Thumb targets.
Mar 14 2017, 8:07 AM
avieira abandoned D29012: [PATCH] Avoid the use of signed to unsigned integer conversion implementation-defined behavior.

OK, I just thought having it rely on implementation defined behavior wasn't very nice. Though I do agree it is not a big deal in this case...

Mar 14 2017, 7:48 AM

Feb 1 2017

avieira added a reviewer for D29012: [PATCH] Avoid the use of signed to unsigned integer conversion implementation-defined behavior: rengolin.
Feb 1 2017, 2:06 AM

Jan 30 2017

avieira added a comment to D29012: [PATCH] Avoid the use of signed to unsigned integer conversion implementation-defined behavior.

Euhm, what sort of test would you propose?

Jan 30 2017, 3:54 AM

Jan 23 2017

avieira created D29012: [PATCH] Avoid the use of signed to unsigned integer conversion implementation-defined behavior.
Jan 23 2017, 3:50 AM