- User Since
- Jan 19 2017, 12:49 AM (214 w, 4 d)
Thu, Feb 4
Accidentally linked my commit of https://reviews.llvm.org/D92236 to this revision. Apologies.
I've committed the patch in https://reviews.llvm.org/rG369f7de3135a517a69c45084d4b175f7b0d5e6f5 but it seems when copying the revision link I may have hit ctrl + x in vim and linked it to D92235 :(
Wed, Feb 3
Jan 24 2021
Jan 22 2021
Thanks. I'll wait till Monday to commit. To avoid Friday hit-and-run's ;)
Updated the testcase. Ok to commit?
Jan 20 2021
So here is an updated version for an optimized memcpy routine for AArch64. This one basically uses the same as the default memcpy, but picks a different block size and alignment for copies > 128.
I also disable tail merging as I found it was leading to worse code. This new memcpy seems to show improvements accross the board for both sweep and distribution benchmarks.
Jan 15 2021
Eh you beat me to it. Had a similar patch I've been measuring and testing. Your's is more complete though :)
Jan 6 2021
Sure, LGTM. What is the usual convention for Libc reviewing? Should I 'accept revision' if I agree with it even though I'm not a maintainer?
Dec 17 2020
Dec 3 2020
Nov 27 2020
Nov 16 2020
Rebased on top of trunk.
Nov 13 2020
Jul 13 2020
Jul 9 2020
Hoisted frequency out of invariant loops.
Jul 8 2020
Feb 13 2018
Feb 9 2018
Jan 12 2018
Jan 9 2018
Split the patch, see fix in: https://reviews.llvm.org/D41855
Also applied other suggested changes.
Jan 8 2018
Thanks for the comments. The split is definitely a good idea, also I have some questions/feedback on the comments. Ill post a new patch here for the code generation and a separate one for the fix.
Jan 5 2018
Nov 13 2017
Nov 8 2017
I started working on the first set of changes for this, taking the vmov instructions only. I added a new register class rGPR2 which behaves the way we want for these instructions. However, I ran into a failure in the CodeGen/ARM/fast-isel-align.ll test when it tried to generate the following:
%vreg6<def> = VMOVRS %vreg10, pred:14, pred:%noreg; GPR:%vreg6 SPR:%vreg10
Oct 18 2017
Sep 28 2017
Sep 25 2017
I took the opportunity to also look at the SP operand. Currently it is not rejected either, and it should for non Armv8-A architectures running in Thumb mode.
Sep 22 2017
Sep 21 2017
The new version of the patch hasnt been reviewed.
Sep 11 2017
Sep 1 2017
OK, I will wait a few days to see if there are any objections.
I moved the check into the existing isCall check and updated the comments.
Added bigger diff.
Aug 21 2017
Now only access to MVFR2 requires Armv8, both A and M profiles, all other instructions are available for any Arm architecture.
Reopening as this was reverted earlier, submitting new version.
Aug 7 2017
Aug 4 2017
Jun 6 2017
LGTM, thanks for the patch!
Mar 17 2017
Mar 15 2017
Mar 14 2017
OK, I just thought having it rely on implementation defined behavior wasn't very nice. Though I do agree it is not a big deal in this case...
Feb 1 2017
Jan 30 2017
Euhm, what sort of test would you propose?