Page MenuHomePhabricator

asavonic (Andrew Savonichev)
User

Projects

User does not belong to any projects.

User Details

User Since
Jun 2 2016, 11:01 PM (253 w, 2 d)

Recent Activity

Fri, Apr 9

asavonic added inline comments to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
Fri, Apr 9, 2:26 PM · Restricted Project
asavonic updated the diff for D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.

Added test cases for fp16 to the MIR test.

Fri, Apr 9, 2:17 PM · Restricted Project
asavonic requested review of D100227: [AArch64] Teach InstCombine to optimize coercion through an undef vector.
Fri, Apr 9, 1:16 PM · Restricted Project
asavonic requested review of D100225: [Clang][AArch64] Coerce integer return values through an undef vector.
Fri, Apr 9, 12:59 PM · Restricted Project
asavonic added inline comments to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
Fri, Apr 9, 7:26 AM · Restricted Project
asavonic updated the diff for D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
  • Removed extra assert
  • Removed arguments that can be queried from Root
  • Removed assignments to RC and Opc
  • Changed tests to ensure that basic blocks are not merged
  • Added fp16 cases to arm64-fma-combines.ll
Fri, Apr 9, 7:21 AM · Restricted Project

Thu, Apr 8

asavonic committed rGf08a2fc09e75: [MCA] Add tests for IPC on Cortex-A55 (authored by asavonic).
[MCA] Add tests for IPC on Cortex-A55
Thu, Apr 8, 9:40 AM
asavonic closed D98174: [MCA] Add tests for IPC on Cortex-A55.
Thu, Apr 8, 9:40 AM · Restricted Project

Wed, Apr 7

asavonic added a comment to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.

But the other thing I was just wondering, not that I mind these patterns here, but are we not expecting that the VDUP is sunk to its user? I think that's probably what I would expect, but don't know if that is a fair expectation.

Wed, Apr 7, 1:46 PM · Restricted Project
asavonic updated the diff for D98174: [MCA] Add tests for IPC on Cortex-A55.

Enabled auto-generated checks for all tests except the XFAIL'ed ones.

Wed, Apr 7, 11:11 AM · Restricted Project
asavonic added a comment to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.

I've uploaded a separate patch for the FIXME issue: https://reviews.llvm.org/D100047
Let me know if anything should be fixed or improved for this one.

Wed, Apr 7, 9:58 AM · Restricted Project
asavonic requested review of D100047: [AArch64] Handle processLogicalImmediate error in Machine InstCombine.
Wed, Apr 7, 9:49 AM · Restricted Project

Wed, Mar 31

asavonic added inline comments to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
Wed, Mar 31, 1:22 PM · Restricted Project
asavonic added inline comments to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
Wed, Mar 31, 11:38 AM · Restricted Project
asavonic updated the diff for D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.

Added test/CodeGen/AArch64/machine-combiner-fmul-dup.mir

Wed, Mar 31, 11:34 AM · Restricted Project
asavonic requested review of D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
Wed, Mar 31, 7:35 AM · Restricted Project

Fri, Mar 26

asavonic updated the diff for D98174: [MCA] Add tests for IPC on Cortex-A55.
  • Adjusted SDIV operands to match the average latency specified in the model.
  • Added FP tests.
  • Added a test for instructions with OOO write and retire.
Fri, Mar 26, 8:08 AM · Restricted Project

Thu, Mar 25

asavonic committed rGbba25a9cd827: [MCA] Support carry-over instructions for in-order processors (authored by asavonic).
[MCA] Support carry-over instructions for in-order processors
Thu, Mar 25, 2:18 PM
asavonic closed D99339: [MCA] Support carry-over instructions for in-order processors.
Thu, Mar 25, 2:17 PM · Restricted Project
asavonic added a comment to D99339: [MCA] Support carry-over instructions for in-order processors.

Thanks for the review Andrea!

Thu, Mar 25, 12:55 PM · Restricted Project
asavonic updated the diff for D99339: [MCA] Support carry-over instructions for in-order processors.
  • Refactored code, added updateCarriedOver function
  • Used a different prefix for non-event debugging messages
Thu, Mar 25, 12:52 PM · Restricted Project
asavonic requested review of D99339: [MCA] Support carry-over instructions for in-order processors.
Thu, Mar 25, 7:19 AM · Restricted Project

Wed, Mar 24

asavonic committed rG292da93d59a3: [MCA] Disable RCU for InOrderIssueStage (authored by asavonic).
[MCA] Disable RCU for InOrderIssueStage
Wed, Mar 24, 3:56 AM
asavonic closed D98628: [MCA] Disable RCU for InOrderIssueStage.
Wed, Mar 24, 3:56 AM · Restricted Project

Tue, Mar 23

asavonic updated the diff for D98628: [MCA] Disable RCU for InOrderIssueStage.
  • Enabled negative readadvance tracking.
  • Reverted unnecessary changes in RetireStage.
Tue, Mar 23, 12:43 PM · Restricted Project

Mon, Mar 22

asavonic added inline comments to D98628: [MCA] Disable RCU for InOrderIssueStage.
Mon, Mar 22, 8:50 AM · Restricted Project

Fri, Mar 19

asavonic updated the diff for D98628: [MCA] Disable RCU for InOrderIssueStage.

Removed RetireStage from the in-order pipeline.
Retire and execute events are emitted in the same cycle.

Fri, Mar 19, 11:08 AM · Restricted Project

Thu, Mar 18

asavonic added a comment to D98895: [X86][Draft] Disable long double type for -mno-x87 option.

I'm not sure that this is the right approach, but I wanted to get feedback on
how the issue should be fixed. Currently, the compiler crashes on almost any
code with long double (excluding cases where CG does not properly disable x87):

Thu, Mar 18, 2:01 PM · Restricted Project
asavonic requested review of D98895: [X86][Draft] Disable long double type for -mno-x87 option.
Thu, Mar 18, 1:45 PM · Restricted Project
asavonic updated the diff for D98628: [MCA] Disable RCU for InOrderIssueStage.

RCU is now optional for RetireStage
RCU statistic is disabled for in-order processors.

Thu, Mar 18, 12:19 PM · Restricted Project
asavonic added a comment to D98628: [MCA] Disable RCU for InOrderIssueStage.

There is nothing wrong with using a dummy RCU for the InOrderIssue stage.

The RCUtokenID is always stored in the instruction at dispatch time. You don't need any changes to pre-existing dispatch stage APIs (and listeners).

Thu, Mar 18, 12:15 PM · Restricted Project
asavonic committed rGe6ce0db37847: [MCA] Ensure that writes occur in-order (authored by asavonic).
[MCA] Ensure that writes occur in-order
Thu, Mar 18, 7:12 AM
asavonic closed D98604: [MCA] Ensure that writes occur in-order.
Thu, Mar 18, 7:11 AM · Restricted Project

Tue, Mar 16

asavonic updated the diff for D98604: [MCA] Ensure that writes occur in-order.

Store LastWriteBackCycle instead of recomputing it.

Tue, Mar 16, 1:26 PM · Restricted Project
asavonic added a comment to D98604: [MCA] Ensure that writes occur in-order.

Is there a reason why you don't allow the bypassing of the write-back hazard check for all RetiresOOO instructions?

NOTE: normally this may not be a problem in practice, since RetiresOOO instructions (for what I have read) tend to have a high write latency. Still, it sounds a bit odd to me that we lift the check in one case, but not the other.
Tue, Mar 16, 12:58 PM · Restricted Project

Mon, Mar 15

asavonic added inline comments to D98604: [MCA] Ensure that writes occur in-order.
Mon, Mar 15, 11:15 AM · Restricted Project
asavonic updated the diff for D98604: [MCA] Ensure that writes occur in-order.

Disable RCU in a separate patch: D98628 [MCA] Disable RCU for InOrderIssueStage

Mon, Mar 15, 4:54 AM · Restricted Project
asavonic requested review of D98628: [MCA] Disable RCU for InOrderIssueStage.
Mon, Mar 15, 4:52 AM · Restricted Project

Sun, Mar 14

asavonic requested review of D98604: [MCA] Ensure that writes occur in-order.
Sun, Mar 14, 10:15 AM · Restricted Project

Mar 9 2021

asavonic added a comment to D98174: [MCA] Add tests for IPC on Cortex-A55.

One last question.
What is the plan with the SDIV test cases? I don't think that there is anything that we can do to improve that simulation, since it would require knowledge that isn't available at simulation time. The risk is to end up with a test which isn't very useful in practice (it will always be marked as XFAIL). In which case, I suggest to remove those DIV tests entirely.

Mar 9 2021, 7:00 AM · Restricted Project
asavonic updated the summary of D98031: [ARM] Add an optimization to avoid S-register forwarding hazards.
Mar 9 2021, 4:25 AM · Restricted Project
asavonic added a comment to D98174: [MCA] Add tests for IPC on Cortex-A55.

Any chance we can use more descriptive testcases names? :-)

Mar 9 2021, 4:02 AM · Restricted Project
asavonic updated the diff for D98174: [MCA] Add tests for IPC on Cortex-A55.

Renamed test files
Replaced "--dispatch-stats" with " --all-views=false --summary-view"

Mar 9 2021, 3:53 AM · Restricted Project

Mar 8 2021

asavonic requested review of D98174: [MCA] Add tests for IPC on Cortex-A55.
Mar 8 2021, 5:48 AM · Restricted Project

Mar 5 2021

asavonic requested review of D98031: [ARM] Add an optimization to avoid S-register forwarding hazards.
Mar 5 2021, 3:30 AM · Restricted Project

Mar 4 2021

asavonic committed rGd791695cb517: [MCA] Add support for in-order CPUs (authored by asavonic).
[MCA] Add support for in-order CPUs
Mar 4 2021, 3:12 AM
asavonic closed D94928: [llvm-mca] Add support for in-order CPUs.
Mar 4 2021, 3:12 AM · Restricted Project

Mar 2 2021

asavonic added inline comments to D94928: [llvm-mca] Add support for in-order CPUs.
Mar 2 2021, 9:19 AM · Restricted Project
asavonic updated the diff for D94928: [llvm-mca] Add support for in-order CPUs.

Update StallCycles and continue instead of return,

Mar 2 2021, 6:46 AM · Restricted Project
asavonic added inline comments to D94928: [llvm-mca] Add support for in-order CPUs.
Mar 2 2021, 6:04 AM · Restricted Project
asavonic added a comment to D94928: [llvm-mca] Add support for in-order CPUs.

Now that https://reviews.llvm.org/D95954 has been fixed, there are only a few things left to do:

  1. Disable the bottleneck analysis for in-order processors.
  2. Add a couple of lines to the release notes describing this new feature.
  3. Update the llvm-mca docs.
Mar 2 2021, 4:47 AM · Restricted Project
asavonic updated the diff for D94928: [llvm-mca] Add support for in-order CPUs.

Supported UNKNOWN_CYCLES left and negative ReadAdvance.
Disabled bottleneck analysis for in-order CPUs.
Updated documentation.

Mar 2 2021, 4:37 AM · Restricted Project

Feb 17 2021

asavonic committed rG4bee0dc918d2: [NFC] Use the same type for bit fields in MCSchedClassDesc (authored by asavonic).
[NFC] Use the same type for bit fields in MCSchedClassDesc
Feb 17 2021, 5:00 AM
asavonic closed D95954: [NFC] Use the same type for bit fields in MCSchedClassDesc.
Feb 17 2021, 4:59 AM · Restricted Project

Feb 3 2021

asavonic added inline comments to D94928: [llvm-mca] Add support for in-order CPUs.
Feb 3 2021, 7:26 AM · Restricted Project
asavonic requested review of D95954: [NFC] Use the same type for bit fields in MCSchedClassDesc.
Feb 3 2021, 7:24 AM · Restricted Project
asavonic updated the diff for D94928: [llvm-mca] Add support for in-order CPUs.

Updated the comment for RetireOOO.

Feb 3 2021, 6:42 AM · Restricted Project

Jan 25 2021

asavonic updated the diff for D94928: [llvm-mca] Add support for in-order CPUs.

Fixed LIT InvalidMCSchedClassDesc.td.

Jan 25 2021, 3:44 AM · Restricted Project

Jan 24 2021

asavonic added inline comments to D94928: [llvm-mca] Add support for in-order CPUs.
Jan 24 2021, 1:10 PM · Restricted Project
asavonic updated the diff for D94928: [llvm-mca] Add support for in-order CPUs.
  • Added RCU support for the in-order pipeline. Some instructions should retire out-of-order, so a new flag was added to SchedClass.
Jan 24 2021, 12:40 PM · Restricted Project

Jan 20 2021

asavonic added inline comments to D94928: [llvm-mca] Add support for in-order CPUs.
Jan 20 2021, 11:22 AM · Restricted Project
asavonic added a comment to D94928: [llvm-mca] Add support for in-order CPUs.

Thanks for the review Andrea!

Jan 20 2021, 9:38 AM · Restricted Project

Jan 18 2021

asavonic requested review of D94928: [llvm-mca] Add support for in-order CPUs.
Jan 18 2021, 12:06 PM · Restricted Project
asavonic updated asavonic.
Jan 18 2021, 12:00 PM

Nov 13 2020

asavonic added inline comments to D89909: [SYCL] Implement SYCL address space attributes handling.
Nov 13 2020, 7:20 AM · Restricted Project, Restricted Project
asavonic added inline comments to D89909: [SYCL] Implement SYCL address space attributes handling.
Nov 13 2020, 1:41 AM · Restricted Project, Restricted Project

Dec 13 2019

asavonic added a comment to D71460: [OpenCL] Fix support for cl_khr_mipmap_image_writes.

What about get_image_num_mip_levels functions defined in the extension specification?

Dec 13 2019, 4:54 AM · Restricted Project

Oct 1 2019

asavonic committed rL373307: Request commit access for asavonic.
Request commit access for asavonic
Oct 1 2019, 12:45 AM

Jun 18 2019

asavonic accepted D63256: [OpenCL] Split type and macro definitions into opencl-c-base.h.

Thanks. LGTM.

Jun 18 2019, 3:22 AM · Restricted Project, Restricted Project

Jun 14 2019

asavonic added a comment to D63256: [OpenCL] Split type and macro definitions into opencl-c-base.h.

LGTM, except for the IncludeDefaultHeader and DeclareOpenCLBuiltins logic.

Jun 14 2019, 8:48 AM · Restricted Project, Restricted Project

Jun 3 2019

asavonic committed rG9ed325e463d5: [OpenCL] Undefine cl_intel_planar_yuv extension (authored by asavonic).
[OpenCL] Undefine cl_intel_planar_yuv extension
Jun 3 2019, 6:01 AM
asavonic committed rL362398: [OpenCL] Undefine cl_intel_planar_yuv extension.
[OpenCL] Undefine cl_intel_planar_yuv extension
Jun 3 2019, 6:01 AM
asavonic closed D58666: [OpenCL] Undefine cl_intel_planar_yuv extension.
Jun 3 2019, 6:01 AM · Restricted Project, Restricted Project
asavonic committed rGfa8cd7691ac2: [OpenCL] Use long instead of long long in x86 builtins (authored by asavonic).
[OpenCL] Use long instead of long long in x86 builtins
Jun 3 2019, 5:35 AM
asavonic committed rL362391: [OpenCL] Use long instead of long long in x86 builtins.
[OpenCL] Use long instead of long long in x86 builtins
Jun 3 2019, 5:34 AM
asavonic closed D62580: [OpenCL] Use long instead of long long in x86 builtins.
Jun 3 2019, 5:34 AM · Restricted Project, Restricted Project

May 30 2019

vladimirlaz <vladimir.lazarev@intel.com> committed rGced972ae1619: [SYCL] Fix ASFixer build with cmake -DBUILD_SHARED_LIBS=ON (authored by asavonic).
[SYCL] Fix ASFixer build with cmake -DBUILD_SHARED_LIBS=ON
May 30 2019, 8:07 AM

Mar 20 2019

asavonic committed rG76b178d9496e: [OpenCL] Generate 'unroll.enable' metadata for __attribute__… (authored by asavonic).
[OpenCL] Generate 'unroll.enable' metadata for __attribute__…
Mar 20 2019, 9:43 AM
asavonic committed rL356571: [OpenCL] Generate 'unroll.enable' metadata for __attribute__….
[OpenCL] Generate 'unroll.enable' metadata for __attribute__…
Mar 20 2019, 9:43 AM
asavonic committed rC356571: [OpenCL] Generate 'unroll.enable' metadata for __attribute__….
[OpenCL] Generate 'unroll.enable' metadata for __attribute__…
Mar 20 2019, 9:43 AM
asavonic closed D59493: [OpenCL] Generate 'unroll.enable' metadata for __attribute__((opencl_unroll_hint)).
Mar 20 2019, 9:43 AM · Restricted Project

Feb 21 2019

asavonic committed rG43fceb27271f: [OpenCL] Simplify LLVM IR generated for OpenCL blocks (authored by asavonic).
[OpenCL] Simplify LLVM IR generated for OpenCL blocks
Feb 21 2019, 3:04 AM
asavonic committed rL354568: [OpenCL] Simplify LLVM IR generated for OpenCL blocks.
[OpenCL] Simplify LLVM IR generated for OpenCL blocks
Feb 21 2019, 3:04 AM
asavonic committed rC354568: [OpenCL] Simplify LLVM IR generated for OpenCL blocks.
[OpenCL] Simplify LLVM IR generated for OpenCL blocks
Feb 21 2019, 3:04 AM
asavonic closed D58388: [OpenCL] Simplify LLVM IR generated for OpenCL blocks.
Feb 21 2019, 3:04 AM · Restricted Project

Dec 12 2018

asavonic committed rL348919: [OpenCL] Fix for TBAA information of pointer after addresspacecast.
[OpenCL] Fix for TBAA information of pointer after addresspacecast
Dec 12 2018, 1:54 AM
asavonic committed rC348919: [OpenCL] Fix for TBAA information of pointer after addresspacecast.
[OpenCL] Fix for TBAA information of pointer after addresspacecast
Dec 12 2018, 1:54 AM
asavonic closed D55262: [OpenCL] Fix for TBAA information of pointer after addresspacecast.
Dec 12 2018, 1:54 AM

Dec 10 2018

asavonic committed rL348752: [OpenCL][CodeGen] Fix replacing memcpy with addrspacecast.
[OpenCL][CodeGen] Fix replacing memcpy with addrspacecast
Dec 10 2018, 4:06 AM
asavonic committed rC348752: [OpenCL][CodeGen] Fix replacing memcpy with addrspacecast.
[OpenCL][CodeGen] Fix replacing memcpy with addrspacecast
Dec 10 2018, 4:06 AM
asavonic closed D54947: [OpenCL][CodeGen] Fix replacing memcpy with addrspacecast.
Dec 10 2018, 4:06 AM

Nov 26 2018

asavonic added a comment to D54253: [OpenCL] Launch opencl-types.cl test only on x86.

FWIW, I'd vote for the first revision of this patch. From my
understanding, the test verifies that libclang is able to parse OpenCL
code correctly. It doesn't do anything specific to x86: target for x86 just
happens to support a set of OpenCL extensions.

I am trying to understand what exactly does it bring into testing if the code doesn't have anything target specific in there?

Nov 26 2018, 3:10 AM

Nov 22 2018

asavonic added a comment to D54253: [OpenCL] Launch opencl-types.cl test only on x86.

FWIW, I'd vote for the first revision of this patch. From my
understanding, the test verifies that libclang is able to parse OpenCL
code correctly. It doesn't do anything specific to x86: target for x86 just
happens to support a set of OpenCL extensions.

Nov 22 2018, 1:46 AM

Nov 8 2018

asavonic added a comment to D51484: [OpenCL] Add support of cl_intel_device_side_avc_motion_estimation extension.

Committed in r346392.

Nov 8 2018, 3:34 AM
asavonic committed rL346392: [OpenCL] Add support of cl_intel_device_side_avc_motion_estimation extension.
[OpenCL] Add support of cl_intel_device_side_avc_motion_estimation extension
Nov 8 2018, 3:28 AM
asavonic committed rC346392: [OpenCL] Add support of cl_intel_device_side_avc_motion_estimation extension.
[OpenCL] Add support of cl_intel_device_side_avc_motion_estimation extension
Nov 8 2018, 3:28 AM
asavonic added a comment to D54253: [OpenCL] Launch opencl-types.cl test only on x86.

LGTM.

Nov 8 2018, 3:01 AM

Nov 7 2018

asavonic added a comment to D51484: [OpenCL] Add support of cl_intel_device_side_avc_motion_estimation extension.

I reverted this change in r346338, as it breaks Index/opencl-types.cl LIT test. See http://lab.llvm.org:8011/builders/clang-ppc64le-linux/builds/21503/steps/ninja%20check%201/logs/FAIL%3A%20Clang%3A%3Aopencl-types.cl

Nov 7 2018, 10:40 AM
asavonic committed rC346338: Revert r346326 [OpenCL] Add support of….
Revert r346326 [OpenCL] Add support of…
Nov 7 2018, 10:37 AM
asavonic committed rL346338: Revert r346326 [OpenCL] Add support of….
Revert r346326 [OpenCL] Add support of…
Nov 7 2018, 10:37 AM