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LiuChen3 (LiuChen)
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User Since
Sep 9 2019, 7:00 PM (64 w, 3 d)

Recent Activity

Fri, Nov 20

LiuChen3 committed rG776f92e06759: [X86] Add support for vex, vex2, vex3, and evex for MASM (authored by LiuChen3).
[X86] Add support for vex, vex2, vex3, and evex for MASM
Fri, Nov 20, 12:22 AM
LiuChen3 closed D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Fri, Nov 20, 12:22 AM · Restricted Project, Restricted Project

Tue, Nov 17

LiuChen3 added a comment to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.

It allows more than two, right? like {vex}{vex2}{vex3} instruction. I think it should be a bug for att.

Tue, Nov 17, 9:35 PM · Restricted Project, Restricted Project
LiuChen3 added a comment to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
  1. Delete IsPrefix parameter, and delete 'break'
Tue, Nov 17, 9:03 PM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
  1. Check prefix, ignoring case
  2. Delete IsPrefix parameter, and delete 'break', so that we won't check prefix again. I am not sure if this is right. Att format can allow two prefix and using the last one as the finally encoding prefix. I think this may not be the original intention of the design.
  3. Change the test: checking the IR istead of checking the assembly.
  4. Made some format adjustments.
Tue, Nov 17, 7:55 PM · Restricted Project, Restricted Project
LiuChen3 added inline comments to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Tue, Nov 17, 5:20 PM · Restricted Project, Restricted Project
LiuChen3 added a comment to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.

Ping?

Tue, Nov 17, 12:24 AM · Restricted Project, Restricted Project

Wed, Nov 11

LiuChen3 added inline comments to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Wed, Nov 11, 11:53 PM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.

Rebase.
Adding the '{}' to prefix when generate IR.

Wed, Nov 11, 11:49 PM · Restricted Project, Restricted Project

Wed, Nov 4

LiuChen3 added inline comments to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Wed, Nov 4, 5:15 PM · Restricted Project, Restricted Project

Nov 4 2020

LiuChen3 added inline comments to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Nov 4 2020, 1:18 AM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
  1. Address comments;
  2. Only support parsing vex/vex2/vex3/evex prefix for MASM
Nov 4 2020, 12:56 AM · Restricted Project, Restricted Project

Nov 2 2020

LiuChen3 added inline comments to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Nov 2 2020, 4:44 PM · Restricted Project, Restricted Project

Oct 30 2020

LiuChen3 added a comment to D89105: [X86] Support Intel avxvnni.

Thanks for all of your review!

Oct 30 2020, 10:20 PM · Restricted Project, Restricted Project
LiuChen3 committed rG756f59784108: [X86] Support Intel avxvnni (authored by LiuChen3).
[X86] Support Intel avxvnni
Oct 30 2020, 10:18 PM
LiuChen3 closed D89105: [X86] Support Intel avxvnni.
Oct 30 2020, 10:18 PM · Restricted Project, Restricted Project
LiuChen3 added a comment to D89105: [X86] Support Intel avxvnni.

LGTM. Thanks. Better to wait one day or two to see if others object.

Oct 30 2020, 12:51 AM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D89105: [X86] Support Intel avxvnni.
  1. Move the testcase from avx-vnni/ to test/CodeGen/X86/.
  2. Refine the Run line in avx_vnni-intrinsics.ll
Oct 30 2020, 12:39 AM · Restricted Project, Restricted Project

Oct 29 2020

LiuChen3 updated the diff for D89105: [X86] Support Intel avxvnni.

Address comments

Oct 29 2020, 10:50 PM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D89105: [X86] Support Intel avxvnni.
Oct 29 2020, 10:02 PM · Restricted Project, Restricted Project
LiuChen3 added reviewers for D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM: craig.topper, pengfei, LuoYuanke, RKSimon.
Oct 29 2020, 8:41 PM · Restricted Project, Restricted Project
LiuChen3 requested review of D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Oct 29 2020, 8:28 PM · Restricted Project, Restricted Project
LiuChen3 committed rG00090a2b826a: Support complex target features combinations (authored by LiuChen3).
Support complex target features combinations
Oct 29 2020, 7:36 PM
LiuChen3 closed D89184: Support complex target features combinations.
Oct 29 2020, 7:36 PM · Restricted Project
LiuChen3 added a comment to D89184: Support complex target features combinations.

Let's go ahead and unblock you, but getting a lot of this refactored would be great if you can. I think it's hitting the limits of the original design. :)

Oct 29 2020, 7:03 PM · Restricted Project

Oct 28 2020

LiuChen3 added a comment to D89184: Support complex target features combinations.

I'll take a look tomorrow, sorry for the delay.

Oct 28 2020, 5:50 PM · Restricted Project
LiuChen3 added a comment to D89184: Support complex target features combinations.

Ping?

Oct 28 2020, 5:39 PM · Restricted Project

Oct 26 2020

LiuChen3 added a comment to D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly..

I have added a fix to run the test only when the X86 target is available. Please feel free to change if it is not the correct fix.
https://github.com/llvm/llvm-project/commit/c551ba0e90bd2b49ef501d591f8362ba44e5484d

Oct 26 2020, 5:39 PM · Restricted Project, Restricted Project

Oct 25 2020

LiuChen3 updated the diff for D89105: [X86] Support Intel avxvnni.

Address comments.

Oct 25 2020, 8:24 PM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D89105: [X86] Support Intel avxvnni.

Adding avxvnni to Alder Lake.

Oct 25 2020, 7:58 PM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D89105: [X86] Support Intel avxvnni.
  1. move the commonvnniintrin.h to the avx512vlvnniintrin.h.
  2. move the testcase avxvnni-builtins.c to X86 subdirectory.
Oct 25 2020, 6:36 PM · Restricted Project, Restricted Project
LiuChen3 committed rG180548c5c784: [X86] VEX/EVEX prefix doesn't work for inline assembly. (authored by LiuChen3).
[X86] VEX/EVEX prefix doesn't work for inline assembly.
Oct 25 2020, 6:09 PM
LiuChen3 closed D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly..
Oct 25 2020, 6:09 PM · Restricted Project, Restricted Project
LiuChen3 added a comment to D89184: Support complex target features combinations.

Hi, @echristo. What's your opinion here?

Oct 25 2020, 5:26 PM · Restricted Project

Oct 23 2020

LiuChen3 added inline comments to D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly..
Oct 23 2020, 1:13 AM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly..

Address comments

Oct 23 2020, 1:12 AM · Restricted Project, Restricted Project

Oct 22 2020

LiuChen3 added inline comments to D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly..
Oct 22 2020, 11:21 PM · Restricted Project, Restricted Project
LiuChen3 added inline comments to D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly..
Oct 22 2020, 11:12 PM · Restricted Project, Restricted Project
LiuChen3 added inline comments to D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly..
Oct 22 2020, 10:35 PM · Restricted Project, Restricted Project
LiuChen3 added reviewers for D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly.: LuoYuanke, pengfei, craig.topper, RKSimon, xiangzhangllvm.
Oct 22 2020, 9:59 PM · Restricted Project, Restricted Project
LiuChen3 requested review of D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly..
Oct 22 2020, 9:54 PM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D89184: Support complex target features combinations.

Address comments

Oct 22 2020, 2:33 AM · Restricted Project

Oct 21 2020

LiuChen3 added a comment to D89184: Support complex target features combinations.

LGTM. But I suggest you waiting for 1 or 2 days to see if other reviewers object.

Oct 21 2020, 11:43 PM · Restricted Project

Oct 19 2020

LiuChen3 added a comment to D89747: Add option to use older clang ABI behavior when passing certain union types as function arguments.

Adding an option compatible with old abi is good method. Looks good for me.

Oct 19 2020, 6:23 PM · Restricted Project

Oct 18 2020

LiuChen3 updated the diff for D89105: [X86] Support Intel avxvnni.

Rebase.

Oct 18 2020, 8:05 PM · Restricted Project, Restricted Project
LiuChen3 added a comment to D89184: Support complex target features combinations.

ping?

Oct 18 2020, 6:31 PM · Restricted Project

Oct 14 2020

LiuChen3 updated the diff for D89184: Support complex target features combinations.

Add a line of comment on unit test.

Oct 14 2020, 5:50 PM · Restricted Project
LiuChen3 updated the diff for D89184: Support complex target features combinations.

Address comments.

Oct 14 2020, 12:29 AM · Restricted Project

Oct 13 2020

LiuChen3 added inline comments to D89184: Support complex target features combinations.
Oct 13 2020, 10:18 PM · Restricted Project
LiuChen3 added a comment to D89361: [X86][NFC] Fix RUN line bug in the testcase.

Thanks for all of your help!

Oct 13 2020, 9:42 PM · Restricted Project
LiuChen3 committed rGbd05afcb3f40: [X86][NFC] Fix RUN line bug in the testcase (authored by LiuChen3).
[X86][NFC] Fix RUN line bug in the testcase
Oct 13 2020, 9:41 PM
LiuChen3 closed D89361: [X86][NFC] Fix RUN line bug in the testcase.
Oct 13 2020, 9:41 PM · Restricted Project
LiuChen3 requested review of D89361: [X86][NFC] Fix RUN line bug in the testcase.
Oct 13 2020, 7:27 PM · Restricted Project
LiuChen3 added a comment to D89184: Support complex target features combinations.

D89105 appears to use only "avx512vl , avx512vnni | avxvnni".
Does it mean (avx512vl , avx512vnni) | avxvnni or avx512vl , (avx512vnni | avxvnni) ?

Oct 13 2020, 7:07 PM · Restricted Project
LiuChen3 added a comment to D78699: [X86] Passing union type through register..

Hi, the test you added seems to pass both before and after your change, is this intended?

Oct 13 2020, 6:41 PM · Restricted Project
LiuChen3 added a comment to D89184: Support complex target features combinations.

LGTM with nit. I'd like to see if others have objection.

Oct 13 2020, 12:11 AM · Restricted Project
LiuChen3 updated the diff for D89184: Support complex target features combinations.

Address comments

Oct 13 2020, 12:11 AM · Restricted Project

Oct 12 2020

LiuChen3 added inline comments to D89184: Support complex target features combinations.
Oct 12 2020, 11:17 PM · Restricted Project
LiuChen3 updated the diff for D89184: Support complex target features combinations.

Address comments.

Oct 12 2020, 11:09 PM · Restricted Project
LiuChen3 added a comment to D89184: Support complex target features combinations.
In D89184#2325597, @tra wrote:

Would it make sense to add a negation, too?

Oct 12 2020, 7:57 PM · Restricted Project
LiuChen3 added a comment to D89105: [X86] Support Intel avxvnni.
Oct 12 2020, 1:37 AM · Restricted Project, Restricted Project

Oct 10 2020

LiuChen3 requested review of D89184: Support complex target features combinations.
Oct 10 2020, 3:47 AM · Restricted Project
LiuChen3 added a comment to D89105: [X86] Support Intel avxvnni.
Oct 10 2020, 1:17 AM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D89105: [X86] Support Intel avxvnni.

Address comments.

Oct 10 2020, 12:56 AM · Restricted Project, Restricted Project

Oct 9 2020

LiuChen3 requested review of D89105: [X86] Support Intel avxvnni.
Oct 9 2020, 2:04 AM · Restricted Project, Restricted Project

Oct 8 2020

LiuChen3 added a comment to D78699: [X86] Passing union type through register..

LGTM

Oct 8 2020, 8:27 PM · Restricted Project
LiuChen3 committed rG26cfb6e562f1: [X86] Passing union type through register (authored by LiuChen3).
[X86] Passing union type through register
Oct 8 2020, 8:26 PM
LiuChen3 closed D78699: [X86] Passing union type through register..
Oct 8 2020, 8:25 PM · Restricted Project
LiuChen3 abandoned D60748: Adds an option "malign-pass-aggregate" to make the alignment of the struct and union parameters compatible with the default gcc.

@wxiao3 @LiuChen3 Are you still looking at this or should it be abandoned?

Oct 8 2020, 7:48 PM · Restricted Project

Sep 27 2020

LiuChen3 updated the diff for D78699: [X86] Passing union type through register..

Address comments.

Sep 27 2020, 11:09 PM · Restricted Project

Sep 22 2020

LiuChen3 updated the diff for D78699: [X86] Passing union type through register..

Include the context.

Sep 22 2020, 8:03 PM · Restricted Project
LiuChen3 added a comment to D78699: [X86] Passing union type through register..

It has been a long time to remember details, but I share @rjmccall concerns.

Sep 22 2020, 7:59 PM · Restricted Project
LiuChen3 updated the diff for D78699: [X86] Passing union type through register..

Address comments

Sep 22 2020, 7:51 PM · Restricted Project

Sep 14 2020

LiuChen3 added a comment to D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

Ping?

Sep 14 2020, 8:07 PM
LiuChen3 added a comment to D78699: [X86] Passing union type through register..

Hi, @majnemer, @bruno. I saw that both of you have modified this logic. What's your opinion here?

Sep 14 2020, 8:06 PM · Restricted Project
LiuChen3 added a reviewer for D78699: [X86] Passing union type through register.: majnemer.
Sep 14 2020, 8:03 PM · Restricted Project

Sep 7 2020

LiuChen3 added a comment to D78699: [X86] Passing union type through register..

Ping?

Sep 7 2020, 6:16 PM · Restricted Project

Sep 6 2020

LiuChen3 updated the diff for D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

Address comments: Replacing the bool argument with an enum argument

Sep 6 2020, 8:37 PM

Sep 1 2020

LiuChen3 added inline comments to D78699: [X86] Passing union type through register..
Sep 1 2020, 2:02 AM · Restricted Project
LiuChen3 added a reviewer for D78699: [X86] Passing union type through register.: bruno.
Sep 1 2020, 1:53 AM · Restricted Project

Jul 7 2020

LiuChen3 committed rGea85ff82c826: [X86] Fix a bug that when lowering byval argument (authored by LiuChen3).
[X86] Fix a bug that when lowering byval argument
Jul 7 2020, 6:50 AM
LiuChen3 closed D83175: [X86] Fix a bug that when lowering byval argument.
Jul 7 2020, 6:50 AM · Restricted Project

Jul 6 2020

LiuChen3 updated the diff for D83175: [X86] Fix a bug that when lowering byval argument.

Address the comments

Jul 6 2020, 10:19 PM · Restricted Project
LiuChen3 updated the diff for D83175: [X86] Fix a bug that when lowering byval argument.

Remove redundant variables

Jul 6 2020, 2:36 AM · Restricted Project

Jul 5 2020

LiuChen3 added inline comments to D83175: [X86] Fix a bug that when lowering byval argument.
Jul 5 2020, 6:07 PM · Restricted Project
LiuChen3 created D83175: [X86] Fix a bug that when lowering byval argument.
Jul 5 2020, 6:23 AM · Restricted Project

Jun 23 2020

LiuChen3 added inline comments to D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..
Jun 23 2020, 9:35 PM
LiuChen3 updated the diff for D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

Remove default arguments.

Jun 23 2020, 7:59 PM
LiuChen3 added inline comments to D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..
Jun 23 2020, 7:26 PM
LiuChen3 added a comment to D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

I used gcc and clang cross-compilation for testing, and currently found no problems.
main.c:

Jun 23 2020, 3:40 AM
LiuChen3 updated the diff for D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

Restricting this change to varargs function calls and address comments.

Jun 23 2020, 3:08 AM

Jun 18 2020

LiuChen3 added a comment to D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

Can you provide a few C testcases comparing gcc and clang, where clang currently misaligns an argument? I briefly tried a few testcases with __m256i vectors, and clang seemed to do the right thing.

Jun 18 2020, 8:11 PM

Jun 17 2020

LiuChen3 added a comment to D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

ping?

Jun 17 2020, 11:11 PM
LiuChen3 added inline comments to D78699: [X86] Passing union type through register..
Jun 17 2020, 11:11 PM · Restricted Project

Apr 27 2020

LiuChen3 added inline comments to D78699: [X86] Passing union type through register..
Apr 27 2020, 2:05 AM · Restricted Project

Apr 23 2020

LiuChen3 added inline comments to D78699: [X86] Passing union type through register..
Apr 23 2020, 7:02 PM · Restricted Project
LiuChen3 updated the diff for D78699: [X86] Passing union type through register..

Address the comment.

Apr 23 2020, 7:01 PM · Restricted Project
LiuChen3 created D78699: [X86] Passing union type through register..
Apr 23 2020, 4:17 AM · Restricted Project

Apr 22 2020

LiuChen3 updated the diff for D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

Determine whether the type is m128/m256/__m512 by type alignment rather than type size.
Since I am not familiar with front-end, adding diagnostics will take some effort. I think it would be better to foucus on this calling-convention for now.

Apr 22 2020, 1:35 AM

Apr 21 2020

LiuChen3 added reviewers for D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi.: efriedma, echristo.
Apr 21 2020, 8:01 PM