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LiuChen3 (LiuChen)
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Sep 9 2019, 7:00 PM (93 w, 1 d)

Recent Activity

Apr 22 2021

LiuChen3 added a comment to D100091: [X86] Fix wrong handle with "-mno-x87".

What is the usage model you’re trying to enable? This has been broken for a long time. Why is it important now?

Apr 22 2021, 12:43 AM · Restricted Project
LiuChen3 added a comment to D100091: [X86] Fix wrong handle with "-mno-x87".

Does adding HasX87 predicates to the instructions cause the conversions in my example to fail?

Apr 22 2021, 12:37 AM · Restricted Project

Apr 21 2021

LiuChen3 added a comment to D100091: [X86] Fix wrong handle with "-mno-x87".

What about cases that use x87 to do float/double conversions? I think it’s i64 conversions in 32-bit mode. But maybe other cases. Does gcc disable those with -mno-80387?

You are right! GCC can do the conversions: https://godbolt.org/z/87ez838oc .
With this patch, llvm will fail in ISEL. I want to make another patch to do this.

I'm more concerned about these cases that don't use long double and aren't missed constant folding. https://godbolt.org/z/qGv54ef34

Apr 21 2021, 11:40 PM · Restricted Project

Apr 20 2021

LiuChen3 committed rG72e4bf12eec4: [X86] Support some missing intrinsics (authored by LiuChen3).
[X86] Support some missing intrinsics
Apr 20 2021, 7:52 PM
LiuChen3 closed D100368: [X86] Support some missing intrinsics.
Apr 20 2021, 7:51 PM · Restricted Project

Apr 19 2021

LiuChen3 added inline comments to D100368: [X86] Support some missing intrinsics.
Apr 19 2021, 1:37 AM · Restricted Project
LiuChen3 updated the diff for D100368: [X86] Support some missing intrinsics.

Fix format issue.

Apr 19 2021, 1:34 AM · Restricted Project
LiuChen3 updated the diff for D100368: [X86] Support some missing intrinsics.
  1. Rebase.
  2. Adding _mm512_i32loscatter_epi64 and _mm512_mask_i32loscatter_epi64.
Apr 19 2021, 1:24 AM · Restricted Project

Apr 14 2021

LiuChen3 added a comment to D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

Thanks for your review. Hope this patch won't cause too many ABI issues in the future.

Apr 14 2021, 1:51 AM · Restricted Project
LiuChen3 committed rG1c4108ab661d: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386… (authored by LiuChen3).
[i386] Modify the alignment of __m128/__m256/__m512 vector type according i386…
Apr 14 2021, 1:48 AM
LiuChen3 closed D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..
Apr 14 2021, 1:47 AM · Restricted Project

Apr 13 2021

LiuChen3 updated the summary of D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled..
Apr 13 2021, 10:13 PM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled..

Address Craig's comments

Apr 13 2021, 10:11 PM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D100368: [X86] Support some missing intrinsics.

Address Simon's comments

Apr 13 2021, 6:13 PM · Restricted Project
LiuChen3 added a comment to D100368: [X86] Support some missing intrinsics.

Add _mm512_i32loscatter_epi64 and _mm512_mask_i32loscatter_epi64 for completeness?

Apr 13 2021, 6:07 AM · Restricted Project
LiuChen3 added reviewers for D100368: [X86] Support some missing intrinsics: craig.topper, pengfei, LuoYuanke, FreddyYe, RKSimon.
Apr 13 2021, 1:44 AM · Restricted Project
LiuChen3 requested review of D100368: [X86] Support some missing intrinsics.
Apr 13 2021, 1:38 AM · Restricted Project
LiuChen3 updated the diff for D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled..

Address Craig's comments

Apr 13 2021, 1:36 AM · Restricted Project, Restricted Project
LiuChen3 added a comment to D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled..

I think I wouldn't mind if we just didn't emit aligned loads/store instructions for AVX/AVX512 from isel and other places in the compiler in the first place. As noted, if the load gets folded the alignment check doesn't happen. That would reduce the size of the isel tables and remove branches, reducing complexity of the compiler. Adding a new step and a command line to undo the earlier decision increases complexity.

The counter argument to that is that the alignment check has found bugs in the vectorizer on more than one occasion that I know of.

Apr 13 2021, 12:58 AM · Restricted Project, Restricted Project
LiuChen3 added a comment to D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled..

I'm still uncomfortable with changing current status quo, even though i obviously don't get to cast the final vote here.

One should not use aligned loads in hope that they will cause an exception to detect address misalignment.
That's UBSan's job. -fsanitize=undefined/-fsanitize=aligment *should* catch it.
If it does not do so in your particular case, please file a bug, i would like to take a look.

Likewise, i don't think one should do overaligned loads and hope that they will just work.
UB is UB. The code will still be miscompiled, but you've just hidden your warning.

Likewise, even if unaligned loads can be always used, i would personally find it pretty surprising
to suddenly see unaliged loads instead of aligned ones.
Also, isn't that only possible/so when AVX is available?
Also, doesn't that cause compiler lock-in?
What happens without AVX? Do so anyways at the perfomance's cost?
Or back to exceptions?

Should this process in any form other than the UBSan changes,
i would like to first see a RFC on llvm-dev.
Sorry about being uneasy about this. :S

Apr 13 2021, 12:51 AM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled..
  1. Rebase;
  2. Emit unaligned move in ISEL;
  3. Only do the conversion on AVX machine.
Apr 13 2021, 12:46 AM · Restricted Project, Restricted Project

Apr 12 2021

LiuChen3 added a comment to D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled..

I think I wouldn't mind if we just didn't emit aligned loads/store instructions for AVX/AVX512 from isel and other places in the compiler in the first place. As noted, if the load gets folded the alignment check doesn't happen. That would reduce the size of the isel tables and remove branches, reducing complexity of the compiler. Adding a new step and a command line to undo the earlier decision increases complexity.

The counter argument to that is that the alignment check has found bugs in the vectorizer on more than one occasion that I know of.

Apr 12 2021, 1:46 AM · Restricted Project, Restricted Project
LiuChen3 added a comment to D100091: [X86] Fix wrong handle with "-mno-x87".

I'm more concerned about these cases that don't use long double and aren't missed constant folding. https://godbolt.org/z/qGv54ef34

Apr 12 2021, 1:36 AM · Restricted Project

Apr 8 2021

LiuChen3 added a comment to D100091: [X86] Fix wrong handle with "-mno-x87".

What about cases that use x87 to do float/double conversions? I think it’s i64 conversions in 32-bit mode. But maybe other cases. Does gcc disable those with -mno-80387?

Apr 8 2021, 12:23 AM · Restricted Project

Apr 7 2021

LiuChen3 retitled D100091: [X86] Fix wrong handle with "-mno-x87" from [X86] Fix wrong handle wih "-mno-x87" to [X86] Fix wrong handle with "-mno-x87".
Apr 7 2021, 11:32 PM · Restricted Project
LiuChen3 added reviewers for D100091: [X86] Fix wrong handle with "-mno-x87": LuoYuanke, pengfei, craig.topper, andrew.w.kaylor.
Apr 7 2021, 11:31 PM · Restricted Project
LiuChen3 requested review of D100091: [X86] Fix wrong handle with "-mno-x87".
Apr 7 2021, 11:28 PM · Restricted Project

Apr 5 2021

LiuChen3 updated the diff for D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

Address Pengfei's comments

Apr 5 2021, 7:38 PM · Restricted Project

Apr 1 2021

LiuChen3 added a comment to D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

Ping?

Apr 1 2021, 5:52 PM · Restricted Project
LiuChen3 updated the diff for D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

Rebase and avoid using 'byval' parameter.

Apr 1 2021, 5:51 PM · Restricted Project

Mar 30 2021

LiuChen3 added inline comments to D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled..
Mar 30 2021, 1:34 AM · Restricted Project, Restricted Project

Mar 29 2021

LiuChen3 added reviewers for D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled.: pengfei, LuoYuanke, craig.topper, kbsmith1.
Mar 29 2021, 11:55 PM · Restricted Project, Restricted Project
LiuChen3 requested review of D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled..
Mar 29 2021, 11:52 PM · Restricted Project, Restricted Project

Mar 9 2021

LiuChen3 committed rGb70e02a7e73c: [X86][NFC] Move instruction selection of the x86_tdpb[s,u]d_internal and… (authored by LiuChen3).
[X86][NFC] Move instruction selection of the x86_tdpb[s,u]d_internal and…
Mar 9 2021, 5:29 AM
LiuChen3 closed D97997: [X86][NFC] Move instruction selection of the x86_tdpb[s,u]d_internal and x86_tilezero_internal to X86InstrAMX.td.
Mar 9 2021, 5:28 AM · Restricted Project
LiuChen3 added inline comments to D97997: [X86][NFC] Move instruction selection of the x86_tdpb[s,u]d_internal and x86_tilezero_internal to X86InstrAMX.td.
Mar 9 2021, 4:03 AM · Restricted Project
LiuChen3 committed rG3618b212987c: [X86][NFC] Adding one flag to imply whether the instruction should check the… (authored by LiuChen3).
[X86][NFC] Adding one flag to imply whether the instruction should check the…
Mar 9 2021, 3:59 AM
LiuChen3 closed D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..
Mar 9 2021, 3:58 AM · Restricted Project

Mar 8 2021

LiuChen3 updated the summary of D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..
Mar 8 2021, 5:11 PM · Restricted Project
LiuChen3 updated the diff for D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..

Address pengfei's comments

Mar 8 2021, 5:08 PM · Restricted Project
LiuChen3 added a comment to D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..

Tests, and some words in description/patch, are missing.

Thanks for your review, @lebedev.ri. This is actually one NFC patch. I think we don't need add new tests.

How is it NFC?

I think @LiuChen3 's NFC firstly means to LLVM. I.e. Moving the manually added check to .inc that generated by tablegen. It's hard to say NFC for the tablegen code. But with a coarse search, I didn't find we have a test for this EVEX2VEX backend. So I assumed it is covered by LLVM tests. By this mean, I think we can call it a NFC :)

That should be explained in patch's description :)

Agreed. Thanks.

Mar 8 2021, 4:43 PM · Restricted Project
LiuChen3 updated the diff for D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..

Address comments

Mar 8 2021, 3:46 AM · Restricted Project
LiuChen3 added inline comments to D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..
Mar 8 2021, 12:10 AM · Restricted Project

Mar 7 2021

LiuChen3 updated the diff for D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..

Address pengfei's comment.

Mar 7 2021, 7:40 PM · Restricted Project
LiuChen3 added inline comments to D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..
Mar 7 2021, 7:35 PM · Restricted Project
LiuChen3 retitled D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding. from [X86] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding. to [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..
Mar 7 2021, 7:33 PM · Restricted Project
LiuChen3 updated the diff for D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..

Rebase and address Pengfei and Craig's comments.

Mar 7 2021, 7:28 PM · Restricted Project
LiuChen3 added a comment to D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..

Tests, and some words in description/patch, are missing.

Mar 7 2021, 6:02 PM · Restricted Project
LiuChen3 added inline comments to D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..
Mar 7 2021, 5:42 PM · Restricted Project
LiuChen3 added inline comments to D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..
Mar 7 2021, 5:25 PM · Restricted Project

Mar 5 2021

LiuChen3 added reviewers for D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding.: LuoYuanke, pengfei, craig.topper.
Mar 5 2021, 12:00 AM · Restricted Project

Mar 4 2021

LiuChen3 requested review of D98011: [X86][NFC] Adding one flag to imply whether the instruction should check the predicate when compress EVEX instructions to VEX encoding..
Mar 4 2021, 11:59 PM · Restricted Project
LiuChen3 added reviewers for D97997: [X86][NFC] Move instruction selection of the x86_tdpb[s,u]d_internal and x86_tilezero_internal to X86InstrAMX.td: pengfei, craig.topper, LuoYuanke.
Mar 4 2021, 6:03 PM · Restricted Project
LiuChen3 requested review of D97997: [X86][NFC] Move instruction selection of the x86_tdpb[s,u]d_internal and x86_tilezero_internal to X86InstrAMX.td.
Mar 4 2021, 6:00 PM · Restricted Project

Feb 24 2021

LiuChen3 committed rG4bc7c8631ad6: [X86] Support amx-bf16 intrinsic. (authored by LiuChen3).
[X86] Support amx-bf16 intrinsic.
Feb 24 2021, 5:07 PM
LiuChen3 closed D97358: [X86] Support amx-bf16 intrinsic..
Feb 24 2021, 5:07 PM · Restricted Project, Restricted Project
LiuChen3 added a comment to D97358: [X86] Support amx-bf16 intrinsic..

I don't know why pre-merge-checks failed. I can check-all successfully locally in redhat8. I don't have debian mainchine to reproduce this problem.

Feb 24 2021, 3:39 AM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D97358: [X86] Support amx-bf16 intrinsic..

Address Pengfei and Yuanke's comments. We don't need more tile type.

Feb 24 2021, 12:23 AM · Restricted Project, Restricted Project

Feb 23 2021

LiuChen3 added inline comments to D97358: [X86] Support amx-bf16 intrinsic..
Feb 23 2021, 11:36 PM · Restricted Project, Restricted Project
LiuChen3 added reviewers for D97358: [X86] Support amx-bf16 intrinsic.: pengfei, LuoYuanke, craig.topper, xiangzhangllvm.
Feb 23 2021, 10:27 PM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D97358: [X86] Support amx-bf16 intrinsic..

Adding back 'avx512f' to amx-tile-basic.ll

Feb 23 2021, 10:26 PM · Restricted Project, Restricted Project
LiuChen3 requested review of D97358: [X86] Support amx-bf16 intrinsic..
Feb 23 2021, 10:20 PM · Restricted Project, Restricted Project
LiuChen3 committed rGf8b9035aae44: [X86] Support amx-int8 intrinsic. (authored by LiuChen3).
[X86] Support amx-int8 intrinsic.
Feb 23 2021, 1:09 AM
LiuChen3 closed D97259: [X86] Support amx-int8 intrinsic..
Feb 23 2021, 1:09 AM · Restricted Project, Restricted Project
LiuChen3 added inline comments to D97259: [X86] Support amx-int8 intrinsic..
Feb 23 2021, 12:53 AM · Restricted Project, Restricted Project

Feb 22 2021

LiuChen3 added inline comments to D97259: [X86] Support amx-int8 intrinsic..
Feb 22 2021, 11:03 PM · Restricted Project, Restricted Project
LiuChen3 added reviewers for D97259: [X86] Support amx-int8 intrinsic.: pengfei, LuoYuanke, xiangzhangllvm, craig.topper.
Feb 22 2021, 11:01 PM · Restricted Project, Restricted Project
LiuChen3 requested review of D97259: [X86] Support amx-int8 intrinsic..
Feb 22 2021, 10:59 PM · Restricted Project, Restricted Project

Dec 28 2020

LiuChen3 added a comment to D86864: [MachineSinking] sink more profitable loads.

The above threshold is for number of MIs. BB->size() is to get instruction number of BB. I committed 31c2b93d83f63ce7f9bb4977f58de2e00bf18e0f to further reduce compiling time. You can have a try

Dec 28 2020, 12:17 AM · Restricted Project

Dec 27 2020

LiuChen3 added a comment to D86864: [MachineSinking] sink more profitable loads.

I can surely do that. But I think the most reasonable solution would be fix the compiling time issue. Since compiling time tests I did before does not expose any regression, your test case must be a little special. Could you find out the special point, for example the function has too many blocks or some/many blocks in the function has too many instructions? Thanks.

I think the increase in compile time is because the function has too many instructions and blocks. The function has Thousands of lines of instructions. Can you add limitation for the number of instructions or the number of blocks so the check for 'store' can end early?

Could you please help to check if the following change can solve your issue?

C
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 0abdf89..8ca3520 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -79,6 +79,12 @@ static cl::opt<unsigned> SplitEdgeProbabilityThreshold(
         "splitted critical edge"),
     cl::init(40), cl::Hidden);
 
+static cl::opt<unsigned> SinkLoadInstsPerBlockThreshold(
+    "machine-sink-load-instrs-threshold",
+    cl::desc("Do not try to find alias store for a load if there is a in-path "
+             "block whose instruction number is higher than this threshold."),
+    cl::init(2000), cl::Hidden);
+
 STATISTIC(NumSunk,      "Number of machine instructions sunk");
 STATISTIC(NumSplit,     "Number of critical edges split");
 STATISTIC(NumCoalesces, "Number of copies coalesced");
@@ -1036,6 +1042,12 @@ bool MachineSinking::hasStoreBetween(MachineBasicBlock *From,
     HandledBlocks.insert(BB);
     // To post dominates BB, it must be a path from block From.
     if (PDT->dominates(To, BB)) {
+      // If this BB is too big, stop searching to save compiling time.
+      if (BB->size() > SinkLoadInstsPerBlockThreshold) {
+        HasStoreCache[BlockPair] = true;
+        return true;
+      }
+
       for (MachineInstr &I : *BB) {
         // Treat as alias conservatively for a call or an ordered memory
         // operation.
Dec 27 2020, 6:22 PM · Restricted Project
LiuChen3 added a comment to D86864: [MachineSinking] sink more profitable loads.

I can surely do that. But I think the most reasonable solution would be fix the compiling time issue. Since compiling time tests I did before does not expose any regression, your test case must be a little special. Could you find out the special point, for example the function has too many blocks or some/many blocks in the function has too many instructions? Thanks.

Dec 27 2020, 4:39 PM · Restricted Project

Dec 22 2020

LiuChen3 added a comment to D86864: [MachineSinking] sink more profitable loads.

Yes, we have been aware that this patch may introduce compiling time degradations. And as you can see in previous comments, I already tested the compiling time on X86 arch. Sadly, the tested benchmarks don't expose any regressions.

Could you please help to send me your regression function/IR? So I can have a look about how to fix it? Thanks.

Dec 22 2020, 11:52 PM · Restricted Project
LiuChen3 added a comment to D86864: [MachineSinking] sink more profitable loads.

Hi, @shchenz. Our several opecncl benchmarks have appeared great compile time regression.
For only one function, the time consume on Machine code sinking pass increased form 6.0711s to 366.5713.
According to your algorithm, this patch will obviously increase the compile time for some cases.

Dec 22 2020, 6:22 PM · Restricted Project

Dec 16 2020

LiuChen3 added a comment to D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..

No. I think this patch can only fix part of the issue.

Can you fix the go issue?

Dec 16 2020, 10:50 PM · Restricted Project
LiuChen3 added a reviewer for D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi.: pengfei.
Dec 16 2020, 10:41 PM · Restricted Project
LiuChen3 added a comment to D78564: [i386] Modify the alignment of __m128/__m256/__m512 vector type according i386 abi..
Dec 16 2020, 9:47 PM · Restricted Project

Nov 20 2020

LiuChen3 committed rG776f92e06759: [X86] Add support for vex, vex2, vex3, and evex for MASM (authored by LiuChen3).
[X86] Add support for vex, vex2, vex3, and evex for MASM
Nov 20 2020, 12:22 AM
LiuChen3 closed D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Nov 20 2020, 12:22 AM · Restricted Project, Restricted Project

Nov 17 2020

LiuChen3 added a comment to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.

It allows more than two, right? like {vex}{vex2}{vex3} instruction. I think it should be a bug for att.

Nov 17 2020, 9:35 PM · Restricted Project, Restricted Project
LiuChen3 added a comment to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
  1. Delete IsPrefix parameter, and delete 'break'
Nov 17 2020, 9:03 PM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
  1. Check prefix, ignoring case
  2. Delete IsPrefix parameter, and delete 'break', so that we won't check prefix again. I am not sure if this is right. Att format can allow two prefix and using the last one as the finally encoding prefix. I think this may not be the original intention of the design.
  3. Change the test: checking the IR istead of checking the assembly.
  4. Made some format adjustments.
Nov 17 2020, 7:55 PM · Restricted Project, Restricted Project
LiuChen3 added inline comments to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Nov 17 2020, 5:20 PM · Restricted Project, Restricted Project
LiuChen3 added a comment to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.

Ping?

Nov 17 2020, 12:24 AM · Restricted Project, Restricted Project

Nov 11 2020

LiuChen3 added inline comments to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Nov 11 2020, 11:53 PM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.

Rebase.
Adding the '{}' to prefix when generate IR.

Nov 11 2020, 11:49 PM · Restricted Project, Restricted Project

Nov 4 2020

LiuChen3 added inline comments to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Nov 4 2020, 5:15 PM · Restricted Project, Restricted Project
LiuChen3 added inline comments to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Nov 4 2020, 1:18 AM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
  1. Address comments;
  2. Only support parsing vex/vex2/vex3/evex prefix for MASM
Nov 4 2020, 12:56 AM · Restricted Project, Restricted Project

Nov 2 2020

LiuChen3 added inline comments to D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Nov 2 2020, 4:44 PM · Restricted Project, Restricted Project

Oct 30 2020

LiuChen3 added a comment to D89105: [X86] Support Intel avxvnni.

Thanks for all of your review!

Oct 30 2020, 10:20 PM · Restricted Project, Restricted Project
LiuChen3 committed rG756f59784108: [X86] Support Intel avxvnni (authored by LiuChen3).
[X86] Support Intel avxvnni
Oct 30 2020, 10:18 PM
LiuChen3 closed D89105: [X86] Support Intel avxvnni.
Oct 30 2020, 10:18 PM · Restricted Project, Restricted Project
LiuChen3 added a comment to D89105: [X86] Support Intel avxvnni.

LGTM. Thanks. Better to wait one day or two to see if others object.

Oct 30 2020, 12:51 AM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D89105: [X86] Support Intel avxvnni.
  1. Move the testcase from avx-vnni/ to test/CodeGen/X86/.
  2. Refine the Run line in avx_vnni-intrinsics.ll
Oct 30 2020, 12:39 AM · Restricted Project, Restricted Project

Oct 29 2020

LiuChen3 updated the diff for D89105: [X86] Support Intel avxvnni.

Address comments

Oct 29 2020, 10:50 PM · Restricted Project, Restricted Project
LiuChen3 updated the diff for D89105: [X86] Support Intel avxvnni.
Oct 29 2020, 10:02 PM · Restricted Project, Restricted Project
LiuChen3 added reviewers for D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM: craig.topper, pengfei, LuoYuanke, RKSimon.
Oct 29 2020, 8:41 PM · Restricted Project, Restricted Project
LiuChen3 requested review of D90441: [X86] Add support for vex, vex2, vex3, and evex for MASM.
Oct 29 2020, 8:28 PM · Restricted Project, Restricted Project
LiuChen3 committed rG00090a2b826a: Support complex target features combinations (authored by LiuChen3).
Support complex target features combinations
Oct 29 2020, 7:36 PM
LiuChen3 closed D89184: Support complex target features combinations.
Oct 29 2020, 7:36 PM · Restricted Project