Page MenuHomePhabricator
Feed Advanced Search

Today

bondhugula added inline comments to D85769: [mlir] [VectorOps] Canonicalization of 1-D memory operations.
Tue, Aug 11, 1:27 PM · Restricted Project
bondhugula added a comment to D85226: [MLIR] Support for ReturnOps in memref map layout normalization.

I tried the patch and this simple code appears to disable memref normalization

#map0 = affine_map<(d0, d1) -> (d1, d0)>
module {
  func @test_simplification(%arg : memref<5x10xf32>) {
    %a = alloc() : memref<10x5xf32, #map0>
    %c1 = constant 1 :index
    %d = dim %arg, %c1 : memref<5x10xf32>
    dealloc %a : memref<10x5xf32, #map0>
    return 
  }
}

The dim is used on a memref that does not have a map, the presence of the dim for arg variable (no maps) seems to disable the normalization of the a variable (with map)

Tue, Aug 11, 1:21 PM · Restricted Project
bondhugula requested changes to D85769: [mlir] [VectorOps] Canonicalization of 1-D memory operations.

Documentation and comments are missing throughout.

Tue, Aug 11, 1:15 PM · Restricted Project
bondhugula requested changes to D85167: [mlir][DialectConversion] Update the documentation for dialect conversion.
Tue, Aug 11, 3:18 AM · Restricted Project

Yesterday

bondhugula added a comment to D85226: [MLIR] Support for ReturnOps in memref map layout normalization.

Looks great. Some initial comments.

Mon, Aug 10, 9:08 AM · Restricted Project
bondhugula added a comment to D85226: [MLIR] Support for ReturnOps in memref map layout normalization.

The code looks good, and I like the addition of skipping the analysis for "extern" functions. Because dialect ops can in some ways also represent "future" external functions, a natural way of handling "not yet expanded" external functions would to add an interface query that ask if a given op is "external" also. Default would be false, and dialects that needs dome/all of their ops to be external would be able to refine the interface to provide the necessary functionality.

Second, the presence of "dim" currently prevent normalization when the dim act on a memref wit maps. It is my firm belief that "dim" should return the logical iterations, not the mapped ones. Would it be possible that when looking at a dim as below:

Mon, Aug 10, 9:02 AM · Restricted Project

Sat, Aug 8

bondhugula committed rG231c554abc8a: [MLIR][NFC] Fix misleading diagnostic error + clang-tidy fix (authored by bondhugula).
[MLIR][NFC] Fix misleading diagnostic error + clang-tidy fix
Sat, Aug 8, 11:06 PM
bondhugula closed D85587: [MLIR][NFC] Fix misleading diagnostic error + clang-tidy fix.
Sat, Aug 8, 11:06 PM · Restricted Project
bondhugula added inline comments to D85260: [mlir][docs] Update/Add documentation for MLIRs Pattern Rewrite infrastructure.
Sat, Aug 8, 3:31 PM · Restricted Project
bondhugula added inline comments to D85260: [mlir][docs] Update/Add documentation for MLIRs Pattern Rewrite infrastructure.
Sat, Aug 8, 3:27 PM · Restricted Project
bondhugula added a comment to D85587: [MLIR][NFC] Fix misleading diagnostic error + clang-tidy fix.

Do we not have a test for this?

Sat, Aug 8, 3:21 PM · Restricted Project
bondhugula requested review of D85587: [MLIR][NFC] Fix misleading diagnostic error + clang-tidy fix.
Sat, Aug 8, 2:51 PM · Restricted Project
bondhugula committed rG654e8aadfdda: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in… (authored by kumasento).
[MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in…
Sat, Aug 8, 2:46 PM
bondhugula closed D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.
Sat, Aug 8, 2:46 PM · Restricted Project
bondhugula accepted D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.
Sat, Aug 8, 2:40 PM · Restricted Project
bondhugula accepted D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.

Some minor fixes.

Sat, Aug 8, 9:44 AM · Restricted Project

Fri, Aug 7

bondhugula added inline comments to D85133: [mlir] Extend BufferAssignmentTypeConverter with result conversion callbacks.
Fri, Aug 7, 10:55 PM · Restricted Project
bondhugula requested changes to D85133: [mlir] Extend BufferAssignmentTypeConverter with result conversion callbacks.
Fri, Aug 7, 10:34 PM · Restricted Project
bondhugula added a comment to D85133: [mlir] Extend BufferAssignmentTypeConverter with result conversion callbacks.

The functionality added looks great! Thanks. I'll shortly submit a review.

Fri, Aug 7, 10:32 PM · Restricted Project
bondhugula accepted D85167: [mlir][DialectConversion] Update the documentation for dialect conversion.
Fri, Aug 7, 9:22 PM · Restricted Project
bondhugula accepted D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.
Fri, Aug 7, 9:12 PM · Restricted Project
bondhugula requested changes to D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.
Fri, Aug 7, 9:07 PM · Restricted Project
bondhugula accepted D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.
Fri, Aug 7, 9:06 PM · Restricted Project
bondhugula committed rG754e09f9cef1: [MLIR] Add tiling validity check to loop tiling pass (authored by kumasento).
[MLIR] Add tiling validity check to loop tiling pass
Fri, Aug 7, 9:04 PM
bondhugula closed D84882: [MLIR] Add tiling validity check to loop tiling pass.
Fri, Aug 7, 9:04 PM · Restricted Project
bondhugula accepted D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.

Looks good, thanks.

Fri, Aug 7, 3:14 AM · Restricted Project

Thu, Aug 6

bondhugula added inline comments to D84998: [MLIR] Add affine.parallel canonicalizations and folding.
Thu, Aug 6, 1:22 PM · Restricted Project
bondhugula added inline comments to D84998: [MLIR] Add affine.parallel canonicalizations and folding.
Thu, Aug 6, 1:19 PM · Restricted Project
bondhugula requested changes to D84998: [MLIR] Add affine.parallel canonicalizations and folding.
Thu, Aug 6, 1:15 PM · Restricted Project
bondhugula added a comment to D85226: [MLIR] Support for ReturnOps in memref map layout normalization.

@AlexEichenberger Would you be able to review this - esp. for the part that's connected to what you wanted?

Thu, Aug 6, 7:50 AM · Restricted Project
bondhugula added a comment to D84882: [MLIR] Add tiling validity check to loop tiling pass.

Looks great - let me know if you'd like me to commit.

Thu, Aug 6, 7:19 AM · Restricted Project
bondhugula accepted D84882: [MLIR] Add tiling validity check to loop tiling pass.
Thu, Aug 6, 7:19 AM · Restricted Project
bondhugula requested changes to D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.
Thu, Aug 6, 7:18 AM · Restricted Project
bondhugula added a comment to D84935: [MLIR] Redundancy detection for FlatAffineConstraints using Simplex.

Please add an [MLIR] tag to the commit title.

Thu, Aug 6, 5:40 AM · Restricted Project
bondhugula accepted D84935: [MLIR] Redundancy detection for FlatAffineConstraints using Simplex.
Thu, Aug 6, 5:40 AM · Restricted Project
bondhugula added a comment to D84935: [MLIR] Redundancy detection for FlatAffineConstraints using Simplex.

Looks great overall - ideally, I'd like to some more test case patterns - the additional tests can be small. Consider this one:

Thu, Aug 6, 5:39 AM · Restricted Project
bondhugula added inline comments to D84935: [MLIR] Redundancy detection for FlatAffineConstraints using Simplex.
Thu, Aug 6, 5:33 AM · Restricted Project
bondhugula added inline comments to D84935: [MLIR] Redundancy detection for FlatAffineConstraints using Simplex.
Thu, Aug 6, 12:07 AM · Restricted Project

Wed, Aug 5

bondhugula added inline comments to D85370: [mlir][Attribute] Remove usages of Attribute::getKind.
Wed, Aug 5, 11:56 PM · Restricted Project
bondhugula added inline comments to D85167: [mlir][DialectConversion] Update the documentation for dialect conversion.
Wed, Aug 5, 10:17 AM · Restricted Project
bondhugula committed rG1d75f004ab06: [MLIR][NFC] Fix clang-tidy warnings in std to llvm conversion (authored by bondhugula).
[MLIR][NFC] Fix clang-tidy warnings in std to llvm conversion
Wed, Aug 5, 9:46 AM
bondhugula added a comment to D85260: [mlir][docs] Update/Add documentation for MLIRs Pattern Rewrite infrastructure.

Thanks very much for this finally - this was long overdue. I skimmed through it - I think it's documenting most of the things. But I think it's also important to have a few lines where appropriate on what one can't do inside a pattern rewrite: in fact, this is typically what new users get wrong and source of many questions.

Wed, Aug 5, 3:49 AM · Restricted Project

Tue, Aug 4

bondhugula requested changes to D85226: [MLIR] Support for ReturnOps in memref map layout normalization.
Tue, Aug 4, 12:43 PM · Restricted Project
bondhugula added a reviewer for D85226: [MLIR] Support for ReturnOps in memref map layout normalization: AlexEichenberger.
Tue, Aug 4, 11:50 AM · Restricted Project
bondhugula accepted D85177: [MLIR][Affine] Fix createPrivateMemRef in affine fusion.
Tue, Aug 4, 9:48 AM · Restricted Project
bondhugula committed rG56593fa37012: [MLIR] Simplify semi-affine expressions (authored by yash).
[MLIR] Simplify semi-affine expressions
Tue, Aug 4, 9:42 AM
bondhugula closed D84920: [MLIR] Simplify semi-affine expressions.
Tue, Aug 4, 9:41 AM · Restricted Project
bondhugula updated the summary of D84920: [MLIR] Simplify semi-affine expressions.
Tue, Aug 4, 7:51 AM · Restricted Project
bondhugula accepted D84920: [MLIR] Simplify semi-affine expressions.
Tue, Aug 4, 7:51 AM · Restricted Project
bondhugula accepted D85048: [mlir] Conversion of ViewOp with memory space to LLVM..
Tue, Aug 4, 2:02 AM · Restricted Project
bondhugula added a comment to D85167: [mlir][DialectConversion] Update the documentation for dialect conversion.

This is quite useful - thanks. Some minor comments on the first half.

Tue, Aug 4, 1:19 AM · Restricted Project
bondhugula requested changes to D85177: [MLIR][Affine] Fix createPrivateMemRef in affine fusion.

Thanks for spotting this @dcaballe. That was clearly an incorrect assumption in the simplification being done for the all zero offset case which was thought to not require a remapping at all.

Tue, Aug 4, 12:52 AM · Restricted Project

Sat, Aug 1

bondhugula added inline comments to D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.
Sat, Aug 1, 8:50 AM · Restricted Project
bondhugula requested changes to D84882: [MLIR] Add tiling validity check to loop tiling pass.
Sat, Aug 1, 8:48 AM · Restricted Project
bondhugula accepted D84882: [MLIR] Add tiling validity check to loop tiling pass.
Sat, Aug 1, 8:47 AM · Restricted Project
bondhugula added inline comments to D84882: [MLIR] Add tiling validity check to loop tiling pass.
Sat, Aug 1, 7:36 AM · Restricted Project
bondhugula requested changes to D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.
Sat, Aug 1, 7:30 AM · Restricted Project
bondhugula requested changes to D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.
Sat, Aug 1, 3:50 AM · Restricted Project
bondhugula added a comment to D84882: [MLIR] Add tiling validity check to loop tiling pass.

Consider changing title to something like '[MLIR] Added tiling validity check to loop tiling pass'. You'll have to hit "Edit revision" manually here as arc doesn't automatically update it.

Sat, Aug 1, 12:32 AM · Restricted Project
bondhugula added a comment to D84882: [MLIR] Add tiling validity check to loop tiling pass.

I think the commit summary is more detailed / has additional info that could be in the doc / implementation comment of checkTilingValidity. You could move a few things from the former to the latter.

Sat, Aug 1, 12:30 AM · Restricted Project
bondhugula accepted D84882: [MLIR] Add tiling validity check to loop tiling pass.

Thanks for revising this - looks good. Some minor comments and this one below.

Sat, Aug 1, 12:29 AM · Restricted Project
bondhugula requested changes to D85048: [mlir] Conversion of ViewOp with memory space to LLVM..
Sat, Aug 1, 12:14 AM · Restricted Project
bondhugula edited reviewers for D84998: [MLIR] Add affine.parallel canonicalizations and folding, added: andydavis1; removed: bondhugula.
Sat, Aug 1, 12:09 AM · Restricted Project
bondhugula added a comment to D84998: [MLIR] Add affine.parallel canonicalizations and folding.

@dcaballe or @ftynse - could one of you review this please? I'm quite tied up the next week.

Sat, Aug 1, 12:09 AM · Restricted Project
bondhugula accepted D84920: [MLIR] Simplify semi-affine expressions.

Thanks for revising. Looks good to me - minor comments.

Sat, Aug 1, 12:05 AM · Restricted Project

Fri, Jul 31

bondhugula requested changes to D84998: [MLIR] Add affine.parallel canonicalizations and folding.

I notice auto being used pervasively and it's impacting readability at most places. Please spell the type out.

Fri, Jul 31, 2:15 AM · Restricted Project
bondhugula added inline comments to D84920: [MLIR] Simplify semi-affine expressions.
Fri, Jul 31, 2:07 AM · Restricted Project
bondhugula added a comment to D84920: [MLIR] Simplify semi-affine expressions.

Added test case for division of constant 0 by symbol.

Fri, Jul 31, 2:04 AM · Restricted Project

Thu, Jul 30

bondhugula added a comment to D84882: [MLIR] Add tiling validity check to loop tiling pass.

Please expand the commit summary a little. The h in h^T . R here are always the canonical directions with the current tiling pass. You really don't need to do anything with FlatAffineConstraints. Instead, the conditions of Irigoin and Triolet would just simplify here to checking whether all dependence components are non-negative along the dimensions you want to tile. And checking this by simply looking at the dependence information is sufficient. You may want to expand on the motivation if you intended something else.

Thank you for your detailed comments @bondhugula !

Can I ask a quick question about the quoted suggestion: I reckon your point is that, since the loop tiles are always hyperrect in the current implementation in affine, the conditions of Irigoin and Triolet can just be simplified to checking non-negative dependence components?

Thu, Jul 30, 2:08 PM · Restricted Project
bondhugula added a comment to D84920: [MLIR] Simplify semi-affine expressions.

But no property for the expressions with different operations ((expr1 ceildiv expr2) floordiv expr3)

Thu, Jul 30, 7:18 AM · Restricted Project
bondhugula requested changes to D84920: [MLIR] Simplify semi-affine expressions.
Thu, Jul 30, 7:16 AM · Restricted Project
bondhugula added inline comments to D84935: [MLIR] Redundancy detection for FlatAffineConstraints using Simplex.
Thu, Jul 30, 7:11 AM · Restricted Project
bondhugula added inline comments to D84935: [MLIR] Redundancy detection for FlatAffineConstraints using Simplex.
Thu, Jul 30, 7:09 AM · Restricted Project
bondhugula requested changes to D84935: [MLIR] Redundancy detection for FlatAffineConstraints using Simplex.

Thanks for implementing this functionality. Some superfluous comments on documentation to start with.

Thu, Jul 30, 7:05 AM · Restricted Project
bondhugula added inline comments to D84882: [MLIR] Add tiling validity check to loop tiling pass.
Thu, Jul 30, 5:59 AM · Restricted Project
bondhugula requested changes to D84882: [MLIR] Add tiling validity check to loop tiling pass.

Please expand the commit summary a little. The h in h^T . R here are always the canonical directions with the current tiling pass. You really don't need to do anything with FlatAffineConstraints. Instead, the conditions of Iriogoin and Triolet would just simplify here to checking whether all dependence components are non-negative along the dimensions you want to tile. And checking this by simply looking at the dependence information is sufficient. You may want to expand on the motivation if you intended something else.

Thu, Jul 30, 5:57 AM · Restricted Project
bondhugula added a comment to D84882: [MLIR] Add tiling validity check to loop tiling pass.

Can you please rephrase the commit title to avoid the name and instead just have it in natural language?

Thu, Jul 30, 5:50 AM · Restricted Project
bondhugula committed rG76d07503f0c6: [MLIR] Introduce inter-procedural memref layout normalization (authored by avarmapml).
[MLIR] Introduce inter-procedural memref layout normalization
Thu, Jul 30, 5:45 AM
bondhugula closed D84490: [MLIR] Introduce inter-procedural memref layout normalization.
Thu, Jul 30, 5:44 AM · Restricted Project
bondhugula added inline comments to D84920: [MLIR] Simplify semi-affine expressions.
Thu, Jul 30, 3:20 AM · Restricted Project
bondhugula added inline comments to D84920: [MLIR] Simplify semi-affine expressions.
Thu, Jul 30, 2:20 AM · Restricted Project
bondhugula added inline comments to D84920: [MLIR] Simplify semi-affine expressions.
Thu, Jul 30, 2:13 AM · Restricted Project
bondhugula requested changes to D84920: [MLIR] Simplify semi-affine expressions.
Thu, Jul 30, 2:10 AM · Restricted Project

Wed, Jul 29

bondhugula requested changes to D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.

Looks great so far - thanks. Some more comments.

Wed, Jul 29, 10:13 PM · Restricted Project
bondhugula added a comment to D84490: [MLIR] Introduce inter-procedural memref layout normalization.

Can you please rebase and fix merge conflicts?

Wed, Jul 29, 8:21 PM · Restricted Project
bondhugula accepted D84490: [MLIR] Introduce inter-procedural memref layout normalization.

Just a few minor comments.

Wed, Jul 29, 7:37 AM · Restricted Project

Tue, Jul 28

bondhugula added a comment to D84698: [MLIR] Consider AffineIfOp when getting the index set of an Op wrapped in nested loops.

Thanks very much for completing these! I'll be able to review this tomorrow. You could consider adding a few test cases to exercise these. These changes could be tested by adding test cases with affine.if's for say memref dep analysis or memref-bound-checking or affine data copy generation - whichever appears easier.

Tue, Jul 28, 3:43 PM · Restricted Project
bondhugula added inline comments to D84769: [mlir][Vector] Add linalg.copy-based pattern for splitting vector.transfer_read into full and partial copies..
Tue, Jul 28, 10:55 AM · Restricted Project
bondhugula accepted D84490: [MLIR] Introduce inter-procedural memref layout normalization.
Tue, Jul 28, 10:48 AM · Restricted Project
bondhugula added inline comments to D84490: [MLIR] Introduce inter-procedural memref layout normalization.
Tue, Jul 28, 5:35 AM · Restricted Project
bondhugula requested changes to D84490: [MLIR] Introduce inter-procedural memref layout normalization.
Tue, Jul 28, 5:32 AM · Restricted Project
bondhugula added inline comments to D84490: [MLIR] Introduce inter-procedural memref layout normalization.
Tue, Jul 28, 5:32 AM · Restricted Project
bondhugula added a comment to D84490: [MLIR] Introduce inter-procedural memref layout normalization.

Could you update the commit summary on this revision page to update the return op handing part? (It doesn't pick it up from arc - you'll have to manually hit "Edit Revision" to edit it.

Tue, Jul 28, 5:20 AM · Restricted Project

Mon, Jul 27

bondhugula added a comment to D84490: [MLIR] Introduce inter-procedural memref layout normalization.

It would be best to handle return ops (where they return memref values with non-identity layouts to be normalized) separately in the next revision - since they add significant complexity.

Mon, Jul 27, 7:22 AM · Restricted Project
bondhugula accepted D84590: [mlir][AffineToStandard] Make LowerAffine pass Op-agnostic..
Mon, Jul 27, 7:18 AM · Restricted Project
bondhugula added inline comments to D84633: [MLIR][SPIRVToLLVM] Conversion for inverse sqrt and tanh.
Mon, Jul 27, 7:17 AM · Restricted Project

Sun, Jul 26

bondhugula accepted D84590: [mlir][AffineToStandard] Make LowerAffine pass Op-agnostic..
Sun, Jul 26, 8:32 PM · Restricted Project
bondhugula committed rGd135744c34dc: [MLIR][Affine] Add test for non-hyperrectangular loop tiling (authored by kumasento).
[MLIR][Affine] Add test for non-hyperrectangular loop tiling
Sun, Jul 26, 7:48 AM
bondhugula closed D84531: [MLIR][Affine] Add test for non-hyperrectangular loop tiling.
Sun, Jul 26, 7:48 AM · Restricted Project
bondhugula added inline comments to D84531: [MLIR][Affine] Add test for non-hyperrectangular loop tiling.
Sun, Jul 26, 7:45 AM · Restricted Project