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foad added a comment to rG6f6d389da5c3: [SplitKit] Only copy live lanes.

I have tried several variations on this:

# RUN: llc -march=amdgcn -run-pass=greedy,virtregrewriter -verify-regalloc < %s | FileCheck %s
Thu, Sep 24, 4:28 AM
foad added a comment to D88020: [SplitKit] In addDeadDef tolerate parent range that defines more lanes.

I don't think it's safe to add dead defs to the extra lanes. You could split the superset into the matching part and the remaining part, then only operate on the matching one.

Thu, Sep 24, 1:48 AM · Restricted Project

Tue, Sep 22

foad added inline comments to D88081: [AMDGPU] Move WQM Pass after MI Scheduler.
Tue, Sep 22, 3:41 AM · Restricted Project
foad committed rG892ef2e3c0b6: [AMDGPU] More codegen patterns for v2i16/v2f16 build_vector (authored by foad).
[AMDGPU] More codegen patterns for v2i16/v2f16 build_vector
Tue, Sep 22, 2:42 AM
foad closed D88028: [AMDGPU] More codegen patterns for v2i16/v2f16 build_vector.
Tue, Sep 22, 2:42 AM · Restricted Project
foad added inline comments to rG6f6d389da5c3: [SplitKit] Only copy live lanes.
Tue, Sep 22, 1:07 AM

Mon, Sep 21

foad added a comment to D88028: [AMDGPU] More codegen patterns for v2i16/v2f16 build_vector.

Can this appear later in the codegen?

Mon, Sep 21, 12:22 PM · Restricted Project
foad updated the diff for D88028: [AMDGPU] More codegen patterns for v2i16/v2f16 build_vector.

Add a move to materialize the constant.

Mon, Sep 21, 8:56 AM · Restricted Project
foad added a comment to D88028: [AMDGPU] More codegen patterns for v2i16/v2f16 build_vector.

The only codegen diffs I saw across several thousand graphics shaders were three instances of:

-	s_pack_ll_b32_b16 s3, s2, 0
+	s_and_b32 s3, 0xffff, s2
Mon, Sep 21, 8:46 AM · Restricted Project
foad requested review of D88028: [AMDGPU] More codegen patterns for v2i16/v2f16 build_vector.
Mon, Sep 21, 8:44 AM · Restricted Project
foad added a comment to D88020: [SplitKit] In addDeadDef tolerate parent range that defines more lanes.

In the test case, RAGreedy::tryLocalSplit splits %72 at 7376r. First we have this:

%72 [1072r,7376r:0)[7376r,7440r:1)  0@1072r 1@7376r L000000000000000C [1072r,1072d:0)[7376r,7440r:1)  0@1072r 1@7376r L00000000000000F3 [1072r,7440r:0)  0@1072r weight:5.969267e-04
...
1072B	  %72:sgpr_128 = COPY %71:sgpr_128
...
7376B	  %72.sub1:sgpr_128 = COPY %912:sreg_32_xm0_xexec
7440B	  %558:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %72:sgpr_128, 0, 0, 0 :: (dereferenceable invariant load 4)

Then SplitEditor::enterIntvBefore creates %914 and inserts the bundled copies (annoying the SlotIndexes get renumbered at this point):

%72 [1072r,7388r:0)[7388r,7452r:1)  0@1072r 1@7388r L000000000000000C [1072r,1072d:0)[7388r,7452r:1)  0@1072r 1@7388r L00000000000000F3 [1072r,7452r:0)  0@1072r weight:5.969267e-04
%914 EMPTY  0@7380r L00000000000000F0 [7380r,7380d:0)  0@7380r L0000000000000003 [7380r,7380d:0)  0@7380r L000000000000000C EMPTY weight:0.000000e+00
...
1072B	  %72:sgpr_128 = COPY %71:sgpr_128
...
7380B	  undef %914.sub2_sub3:sgpr_128 = COPY %72.sub2_sub3:sgpr_128 {
	    internal %914.sub0:sgpr_128 = COPY %72.sub0:sgpr_128
7388B	  }
  %72.sub1:sgpr_128 = COPY %912:sreg_32_xm0_xexec
7452B	  %558:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %72:sgpr_128, 0, 0, 0 :: (dereferenceable invariant load 4)

Then SplitEditor::finish tries to add dead defs for %914 L00000000000000F0 and L0000000000000003 but fails to find matching lane masks in the original live ranges for %72 -- which just had a single lane mask L00000000000000F3.

Mon, Sep 21, 5:28 AM · Restricted Project
foad added reviewers for D88020: [SplitKit] In addDeadDef tolerate parent range that defines more lanes: kparzysz, qcolombet, MatzeB.
Mon, Sep 21, 5:16 AM · Restricted Project
foad requested review of D88020: [SplitKit] In addDeadDef tolerate parent range that defines more lanes.
Mon, Sep 21, 5:14 AM · Restricted Project

Fri, Sep 18

foad added inline comments to D87912: [X86] Use shuffle to widen truncate of 128-bit and smaller vectors.
Fri, Sep 18, 9:17 AM · Restricted Project
foad added inline comments to D87502: [DAGCombiner] Use known bits to fold extract_vector_elt with const index.
Fri, Sep 18, 9:05 AM · Restricted Project
foad requested review of D87912: [X86] Use shuffle to widen truncate of 128-bit and smaller vectors.
Fri, Sep 18, 9:04 AM · Restricted Project

Thu, Sep 17

foad updated subscribers of D87502: [DAGCombiner] Use known bits to fold extract_vector_elt with const index.

This isn't ready to commit yet:

  1. there are a few code quality regressions in the test cases
  2. it provokes a crash on test/CodeGen/AMDGPU/global-extload-i16.ll which I haven't been able to fix yet
Thu, Sep 17, 2:22 AM · Restricted Project
foad updated the diff for D87502: [DAGCombiner] Use known bits to fold extract_vector_elt with const index.

Rebase.

Thu, Sep 17, 2:11 AM · Restricted Project
foad committed rG6f6d389da5c3: [SplitKit] Only copy live lanes (authored by foad).
[SplitKit] Only copy live lanes
Thu, Sep 17, 1:27 AM
foad committed rGd49707cf4b28: [AMDGPU] Generate test checks for splitkit-copy-bundle.mir (authored by foad).
[AMDGPU] Generate test checks for splitkit-copy-bundle.mir
Thu, Sep 17, 1:26 AM
foad closed D87757: [SplitKit] Only copy live lanes.
Thu, Sep 17, 1:26 AM · Restricted Project

Wed, Sep 16

foad added a comment to D87757: [SplitKit] Only copy live lanes.

@rampitec this patch causes CodeGen/AMDGPU/splitkit-copy-bundle.mir to fail because it no longer generates any bundles. Could you help find a way to update the test case? I have pushed this patch to github in case you want to pull from there: https://github.com/jayfoad/llvm-project/tree/only-copy-live-lanes

There is very high chance this test in unfixable with your changes as these prevent the very situation where the KIILs were formed. I'd say you may just generate checks there. At the end this code snippet did not compile and asserted, so we need to make sure it compiles. Bundles themselves are just an implementation detail.

Wed, Sep 16, 12:32 PM · Restricted Project
foad updated the diff for D87757: [SplitKit] Only copy live lanes.

Generate test checks for splitkit-copy-bundle.mir.

Wed, Sep 16, 12:31 PM · Restricted Project
foad committed rGcb64455faa36: [AMDGPU] Remove obsolete comment (authored by foad).
[AMDGPU] Remove obsolete comment
Wed, Sep 16, 9:04 AM
foad committed rG90777e2924ec: [AMDGPU] Enable scheduling around FP MODE-setting instructions (authored by foad).
[AMDGPU] Enable scheduling around FP MODE-setting instructions
Wed, Sep 16, 8:12 AM
foad committed rG54bb9e864980: [AMDGPU] Add -show-mc-encoding to setreg tests (authored by foad).
[AMDGPU] Add -show-mc-encoding to setreg tests
Wed, Sep 16, 8:12 AM
foad closed D87446: [AMDGPU] Enable scheduling around FP MODE-setting instructions.
Wed, Sep 16, 8:12 AM · Restricted Project
foad updated the diff for D87446: [AMDGPU] Enable scheduling around FP MODE-setting instructions.

Factor instruction definitions into a class.

Wed, Sep 16, 7:54 AM · Restricted Project
foad added inline comments to D87621: [AMDGPU] Add XDL resource to scheduling model.
Wed, Sep 16, 7:13 AM · Restricted Project
foad updated the diff for D87757: [SplitKit] Only copy live lanes.

Generate test checks.

Wed, Sep 16, 6:48 AM · Restricted Project
foad added a comment to D87757: [SplitKit] Only copy live lanes.

I'm assuming this doesn't fix the problem of spilling unnecessary lanes?

Wed, Sep 16, 6:24 AM · Restricted Project
foad added reviewers for D87757: [SplitKit] Only copy live lanes: qcolombet, arsenm, rampitec, kparzysz, MatzeB, tpr.
Wed, Sep 16, 5:11 AM · Restricted Project
foad updated subscribers of D87757: [SplitKit] Only copy live lanes.

@rampitec this patch causes CodeGen/AMDGPU/splitkit-copy-bundle.mir to fail because it no longer generates any bundles. Could you help find a way to update the test case? I have pushed this patch to github in case you want to pull from there: https://github.com/jayfoad/llvm-project/tree/only-copy-live-lanes

Wed, Sep 16, 5:10 AM · Restricted Project
foad requested review of D87757: [SplitKit] Only copy live lanes.
Wed, Sep 16, 5:07 AM · Restricted Project
foad added a comment to D87585: [AMDGPU] Dynamically clear renamable to avoid constant bus errors.

Are there any other significant changes? I'm thinking of things like this that would help with dependency stalls on gfx10:

v_mov v0, 0
v_mov v1, v0

->

v_mov v0, 0
v_mov v1, 0
Wed, Sep 16, 1:52 AM · Restricted Project
foad added a comment to D87585: [AMDGPU] Dynamically clear renamable to avoid constant bus errors.

The numbers for this change are not vastly compelling.
I looked at 11598 game shaders and compiled these for GFX7, GFX9 and GFX10.
On GFX7, 1 shader lost 1 instruction.
On GFX9, 1 shader lost 1 instruction, but 64 shaders gained 1 instruction.
On GFX10, 1 shader lost 1 instruction, but 2 shaders gained 1 instruction.

Wed, Sep 16, 1:31 AM · Restricted Project

Tue, Sep 15

foad added a comment to D87446: [AMDGPU] Enable scheduling around FP MODE-setting instructions.

The encoding seems OK. I can pre-commit the -show-mc-encoding change to make that clearer if you want.

Tue, Sep 15, 4:21 AM · Restricted Project
foad updated the diff for D87446: [AMDGPU] Enable scheduling around FP MODE-setting instructions.

Add -show-mc-encoding.

Tue, Sep 15, 4:20 AM · Restricted Project
foad added a comment to D52010: RegAllocFast: Rewrite and improve.

With this patch applied I'm getting:

$ ~/llvm-debug/bin/llc -march=amdgcn -o /dev/null -regalloc=fast x.ll
llc: /home/jayfoad2/git/llvm-project/llvm/lib/CodeGen/RegAllocFast.cpp:876: void (anonymous namespace)::RegAllocFast::useVirtReg(llvm::MachineInstr &, unsigned int, llvm::Register): Assertion `!MO.isTied() && "tied op should be allocated"' failed.

Tue, Sep 15, 2:19 AM · Restricted Project

Mon, Sep 14

foad added inline comments to D87446: [AMDGPU] Enable scheduling around FP MODE-setting instructions.
Mon, Sep 14, 8:45 AM · Restricted Project
foad added a comment to D87585: [AMDGPU] Dynamically clear renamable to avoid constant bus errors.

Where/why is renameable set in the first place? Can we just avoid setting it to begin with?

Mon, Sep 14, 7:41 AM · Restricted Project
foad added inline comments to D87464: [TargetLowering] Improve SimplifyDemandedBits for AND and OR.
Mon, Sep 14, 7:38 AM · Restricted Project
foad added inline comments to D87464: [TargetLowering] Improve SimplifyDemandedBits for AND and OR.
Mon, Sep 14, 7:07 AM · Restricted Project
foad committed rGc799f873cb9f: [AMDGPU] Don't cluster stores (authored by foad).
[AMDGPU] Don't cluster stores
Mon, Sep 14, 5:40 AM
foad closed D85530: [AMDGPU] Don't cluster stores.
Mon, Sep 14, 5:40 AM · Restricted Project
foad added a comment to D87585: [AMDGPU] Dynamically clear renamable to avoid constant bus errors.

Do you have any stats on how many more copies get propagated, and how many instructions that actually saves in the final ISA? I have a feeling that SIFoldOperands currently catches a lot of the cases that MachineCopyProp misses.

Mon, Sep 14, 1:16 AM · Restricted Project
foad committed rG9a4476072e15: [UnifyLoopExits] Fix non-deterministic iteration order (authored by foad).
[UnifyLoopExits] Fix non-deterministic iteration order
Mon, Sep 14, 1:10 AM
foad closed D87548: [UnifyLoopExits] Fix non-deterministic iteration order.
Mon, Sep 14, 1:10 AM · Restricted Project

Fri, Sep 11

foad requested review of D87548: [UnifyLoopExits] Fix non-deterministic iteration order.
Fri, Sep 11, 2:04 PM · Restricted Project
foad added inline comments to D87464: [TargetLowering] Improve SimplifyDemandedBits for AND and OR.
Fri, Sep 11, 7:46 AM · Restricted Project
foad added a comment to D87456: AMDGPU/GlobalISel Check for NoNaNsFPMath in isKnownNeverSNaN.

This will be fixed by in D87511.

Fri, Sep 11, 6:50 AM · Restricted Project
foad added reviewers for D87511: GlobalISel/IRTranslator resetTargetOptions based on function attributes: aemerson, qcolombet.
Fri, Sep 11, 6:43 AM · Restricted Project
foad added a comment to D87502: [DAGCombiner] Use known bits to fold extract_vector_elt with const index.
  1. it provokes a crash on test/CodeGen/AMDGPU/global-extload-i16.ll which I haven't been able to fix yet
Fri, Sep 11, 6:03 AM · Restricted Project
foad added a comment to D87502: [DAGCombiner] Use known bits to fold extract_vector_elt with const index.

This isn't ready to commit yet:

  1. there are a few code quality regressions in the test cases
  2. it provokes a crash on test/CodeGen/AMDGPU/global-extload-i16.ll which I haven't been able to fix yet
Fri, Sep 11, 2:48 AM · Restricted Project
foad requested review of D87502: [DAGCombiner] Use known bits to fold extract_vector_elt with const index.
Fri, Sep 11, 2:44 AM · Restricted Project
foad committed rG06e356c81e0f: [AMDGPU] Make movreld-bug test case more robust (authored by foad).
[AMDGPU] Make movreld-bug test case more robust
Fri, Sep 11, 2:25 AM
foad added a comment to D87464: [TargetLowering] Improve SimplifyDemandedBits for AND and OR.

@nikic this could perhaps increase compile time. Could you test it please?

Not seeing any impact from this change (https://llvm-compile-time-tracker.com/compare.php?from=a5168bdb4a25485ac62e18bdc538b4842bc9fbd9&to=c23aa3c1c163fc5343b1df5254b8c0782d4324cb&stat=instructions).

Fri, Sep 11, 1:39 AM · Restricted Project

Thu, Sep 10

foad updated the diff for D87446: [AMDGPU] Enable scheduling around FP MODE-setting instructions.

Rename the pseudo-instructions.

Thu, Sep 10, 9:31 AM · Restricted Project
foad added inline comments to D87145: [SelectionDAG] Remove an early-out from computeKnownBits for smin/smax.
Thu, Sep 10, 9:25 AM · Restricted Project
foad requested review of D87465: [TargetLowering] Change SimplifyDemandedBits for XOR.
Thu, Sep 10, 9:21 AM · Restricted Project
foad updated subscribers of D87464: [TargetLowering] Improve SimplifyDemandedBits for AND and OR.

@nikic this could perhaps increase compile time. Could you test it please?

Thu, Sep 10, 9:04 AM · Restricted Project
foad requested review of D87464: [TargetLowering] Improve SimplifyDemandedBits for AND and OR.
Thu, Sep 10, 9:03 AM · Restricted Project
foad committed rG517202c720ea: [TargetLowering] Fix comments describing XOR -> OR/AND transformations (authored by foad).
[TargetLowering] Fix comments describing XOR -> OR/AND transformations
Thu, Sep 10, 5:57 AM
foad added inline comments to D87145: [SelectionDAG] Remove an early-out from computeKnownBits for smin/smax.
Thu, Sep 10, 5:45 AM · Restricted Project
foad requested review of D87446: [AMDGPU] Enable scheduling around FP MODE-setting instructions.
Thu, Sep 10, 3:42 AM · Restricted Project

Wed, Sep 9

foad committed rG649bde488ce9: [AMDGPU] Simplify S_SETREG_B32 case in EmitInstrWithCustomInserter (authored by foad).
[AMDGPU] Simplify S_SETREG_B32 case in EmitInstrWithCustomInserter
Wed, Sep 9, 7:19 AM
foad added a comment to D86294: AMDGPU/GlobalISel: Add tablegen operator that looks through copies.

I think copies that can be ignored should be taken care of by a combiner pass, and the selector should not have to do this

Wed, Sep 9, 2:01 AM · Restricted Project
foad added a comment to D87351: AMDGPU/GlobalISel/Emitter Recognize additional 'same operand checks'.

How does the new test case relate to the tablegen change? Perhaps you could pre-commit it so we can see the test case diffs?

Wed, Sep 9, 1:56 AM · Restricted Project

Tue, Sep 8

foad added inline comments to D87285: AMDGPU/GlobalISelemitter Support for predicate code that uses operands.
Tue, Sep 8, 8:55 AM · Restricted Project
foad accepted D87093: [AMDGPU] Workaround for LDS Misalignment bug on GFX10.

Looks good to me if Matt has no further comments. I'm not sure whether gfx10.1.1 has the bug but it's certainly safe to assume it does, unless/until we know otherwise.

Tue, Sep 8, 3:52 AM · Restricted Project
foad added inline comments to D87145: [SelectionDAG] Remove an early-out from computeKnownBits for smin/smax.
Tue, Sep 8, 2:48 AM · Restricted Project
foad added a comment to D87034: [KnownBits] Implement accurate unsigned and signed max and min.

Contrary to my expectations, this change had a small but measurable compile-time impact: https://llvm-compile-time-tracker.com/compare.php?from=04ea680a8ccc4f9a4d7333cd712333960348c35b&to=5350e1b5096aa4707aa525baf7398d93b4a4f1a5&stat=instructions

Unfortunately, I have no idea why. I looked at callgrind profiles and the extra instructions (consistently) end up inside a DenseMap method (without changes to number of calls). Can't explain why that would happen, and the diff is not large enough to bother looking further.

I did end up applying this small cleanup while looking over the code again: https://github.com/llvm/llvm-project/commit/ddab4cd83ea31141aaada424dccf94278482ee88

Tue, Sep 8, 2:39 AM · Restricted Project

Mon, Sep 7

foad committed rG713c2ad60c13: [GlobalISel] Extend not_cmp_fold to work on conditional expressions (authored by foad).
[GlobalISel] Extend not_cmp_fold to work on conditional expressions
Mon, Sep 7, 1:31 AM
foad closed D86709: [GlobalISel] Extend not_cmp_fold to work on conditional expressions.
Mon, Sep 7, 1:31 AM · Restricted Project
foad committed rG5350e1b5096a: [KnownBits] Implement accurate unsigned and signed max and min (authored by foad).
[KnownBits] Implement accurate unsigned and signed max and min
Mon, Sep 7, 1:10 AM
foad closed D87034: [KnownBits] Implement accurate unsigned and signed max and min.
Mon, Sep 7, 1:10 AM · Restricted Project

Sat, Sep 5

foad added a comment to D87174: [GlobalISel] Add `X,Y<dead> = G_UNMERGE Z` -> X = G_TRUNC Z.

Typo in summary "except".

Sat, Sep 5, 2:50 AM · Restricted Project

Fri, Sep 4

foad added a comment to D87145: [SelectionDAG] Remove an early-out from computeKnownBits for smin/smax.

N.B without D87034, this change wouldn't affect any codegen tests. So this is one case where the improved known bits analysis actually makes a difference.

Fri, Sep 4, 8:26 AM · Restricted Project
foad requested review of D87145: [SelectionDAG] Remove an early-out from computeKnownBits for smin/smax.
Fri, Sep 4, 8:24 AM · Restricted Project
foad updated the diff for D87034: [KnownBits] Implement accurate unsigned and signed max and min.

Simplify makeGE.

Fri, Sep 4, 7:20 AM · Restricted Project
foad added inline comments to D87140: [GlobalISel] Avoid making G_PTR_ADD with nullptr.
Fri, Sep 4, 7:12 AM · Restricted Project

Thu, Sep 3

foad added inline comments to D87034: [KnownBits] Implement accurate unsigned and signed max and min.
Thu, Sep 3, 2:07 PM · Restricted Project
foad added inline comments to D86750: GlobalISel: Port smarter known bits for umin/umax from DAG.
Thu, Sep 3, 11:25 AM · Restricted Project
foad updated the diff for D87034: [KnownBits] Implement accurate unsigned and signed max and min.

Use it in SelectionDAG, GlobalISel and ValueTracking.

Thu, Sep 3, 11:21 AM · Restricted Project
foad added inline comments to D86750: GlobalISel: Port smarter known bits for umin/umax from DAG.
Thu, Sep 3, 11:14 AM · Restricted Project
foad added a comment to D87034: [KnownBits] Implement accurate unsigned and signed max and min.

Can you replace the implementations in SelectionDAG::computeKnownBits with these?

Yes, that's the idea, and the same in GlobalISel and in ValueTracking.

Sorry, what I meant was are there any codegen test diffs if you replace SelectionDAG::computeKnownBits with this implementation?

No, using it in SelectionDAG doesn't affect any existing tests.

I think the question is, is this implementation expected to be identical to those, or better?
Regardless, i believe all those implementations should be replaced to use this in *this* patch,
to give better testing coverage.

Thu, Sep 3, 10:12 AM · Restricted Project
foad updated the diff for D87034: [KnownBits] Implement accurate unsigned and signed max and min.

Use const APInt &.

Thu, Sep 3, 10:01 AM · Restricted Project
foad added a comment to D87034: [KnownBits] Implement accurate unsigned and signed max and min.

Can you replace the implementations in SelectionDAG::computeKnownBits with these?

Yes, that's the idea, and the same in GlobalISel and in ValueTracking.

Sorry, what I meant was are there any codegen test diffs if you replace SelectionDAG::computeKnownBits with this implementation?

Thu, Sep 3, 9:52 AM · Restricted Project
foad added a comment to D84403: [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag.

This breaks LDS. LLVMSetAlignment(inst, 4) on loads and stores has no effect. The IR says "align 4", yet the backend still selects b128.

On what subtargets? GFX9 and 10 should select b128 for align 4. That is the purpose of the patch. Are you saying it selects it for SI, CI or VI?

On GFX10. Apparently b128 with align 4 doesn't work there.

I've checked a couple Vulkan CTS tests that now produce b128 instructions for SDag and they work fine. I also did not find any regressions on others. Can you give us any more details? Or a test to reproduce the issue?

More information:

  • (gfx9 hasn't been tested)
  • gfx10.1 has the corruption in WGP mode only (CU mode works)
  • gfx10.3 works

It looks like it's a gfx10.1 hw bug in WGP mode, so a fix or workaround is needed. The driver always uses WGP mode.

Thu, Sep 3, 12:31 AM · Restricted Project

Wed, Sep 2

foad committed rG099c089d4b41: [APInt] New member function setBitVal (authored by foad).
[APInt] New member function setBitVal
Wed, Sep 2, 1:57 PM
foad closed D87033: [APInt] New member function setBitVal.
Wed, Sep 2, 1:57 PM · Restricted Project
foad updated subscribers of D87034: [KnownBits] Implement accurate unsigned and signed max and min.
Wed, Sep 2, 1:42 PM · Restricted Project
foad added inline comments to D87034: [KnownBits] Implement accurate unsigned and signed max and min.
Wed, Sep 2, 12:16 PM · Restricted Project
foad updated the diff for D87034: [KnownBits] Implement accurate unsigned and signed max and min.

Simplify the implementation of KnownBits::umax.

Wed, Sep 2, 12:15 PM · Restricted Project
foad added inline comments to D87034: [KnownBits] Implement accurate unsigned and signed max and min.
Wed, Sep 2, 12:07 PM · Restricted Project
foad retitled D87033: [APInt] New member function setBitVal from [APInt] New member function setBitTo to [APInt] New member function setBitVal.
Wed, Sep 2, 12:05 PM · Restricted Project
foad added a comment to D87034: [KnownBits] Implement accurate unsigned and signed max and min.

Can you replace the implementations in SelectionDAG::computeKnownBits with these?

Wed, Sep 2, 12:04 PM · Restricted Project
foad updated the diff for D87034: [KnownBits] Implement accurate unsigned and signed max and min.

Rebase.

Wed, Sep 2, 12:03 PM · Restricted Project
foad updated the diff for D87033: [APInt] New member function setBitVal.

Rename to setBitVal and change implementation.

Wed, Sep 2, 12:03 PM · Restricted Project
foad added inline comments to D87034: [KnownBits] Implement accurate unsigned and signed max and min.
Wed, Sep 2, 11:31 AM · Restricted Project