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sepavloff added a comment to D99083: [RISCV] Introduce floating point control and state registers.

Does this patch require other changes?

Mon, Apr 19, 2:20 AM · Restricted Project

Wed, Apr 14

sepavloff added a comment to D74730: [FPEnv][X86] Implement lowering of llvm.set.rounding.

Is there anything I can do to facilitate the review process?

Wed, Apr 14, 7:43 PM · Restricted Project

Mon, Apr 12

sepavloff added a comment to D82525: [FPEnv] Intrinsics for access to FP control modes.

Any feedback?

Mon, Apr 12, 8:39 AM · Restricted Project

Thu, Apr 8

sepavloff added a comment to D74730: [FPEnv][X86] Implement lowering of llvm.set.rounding.

Ping.

Thu, Apr 8, 4:06 AM · Restricted Project

Wed, Apr 7

sepavloff updated the diff for D99083: [RISCV] Introduce floating point control and state registers.

Use zero for encoding of FFLAGS, FRM and FCSR. Rebased.

Wed, Apr 7, 11:18 PM · Restricted Project
sepavloff added inline comments to D99083: [RISCV] Introduce floating point control and state registers.
Wed, Apr 7, 8:48 PM · Restricted Project
sepavloff added inline comments to D99083: [RISCV] Introduce floating point control and state registers.
Wed, Apr 7, 8:47 PM · Restricted Project
sepavloff committed rG65b1103798df: [RISCV] DAG nodes and pseudo instructions for CSR access (authored by sepavloff).
[RISCV] DAG nodes and pseudo instructions for CSR access
Wed, Apr 7, 8:37 PM
sepavloff closed D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.
Wed, Apr 7, 8:37 PM · Restricted Project
sepavloff added inline comments to D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.
Wed, Apr 7, 1:35 AM · Restricted Project
sepavloff updated the diff for D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

Addressed reviewer's notes and rebased

Wed, Apr 7, 1:33 AM · Restricted Project

Mon, Apr 5

sepavloff added a comment to D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

Any feedback?

Mon, Apr 5, 9:26 PM · Restricted Project

Sun, Apr 4

sepavloff added a comment to D82525: [FPEnv] Intrinsics for access to FP control modes.

Ping.

Sun, Apr 4, 9:09 PM · Restricted Project

Thu, Apr 1

sepavloff updated the diff for D99083: [RISCV] Introduce floating point control and state registers.

Rebased ad added variants with immediate

Thu, Apr 1, 11:43 PM · Restricted Project
sepavloff updated the diff for D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

Rebased and added variants with immediate

Thu, Apr 1, 11:24 PM · Restricted Project
sepavloff added inline comments to D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.
Thu, Apr 1, 10:01 AM · Restricted Project

Wed, Mar 31

sepavloff added inline comments to D99083: [RISCV] Introduce floating point control and state registers.
Wed, Mar 31, 11:50 PM · Restricted Project
sepavloff updated the diff for D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

Removed instructions Read_CSR, Write_CSR and Swap_CSR

Wed, Mar 31, 8:51 AM · Restricted Project
sepavloff added a comment to D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.
In D98936#2661228, @asb wrote:

Are there ever any cases where you _wouldn't_ want a CSR-specific pseudo in order to have control over the scheduling of it specifically? This feels a bit like a middle-ground that's the worst of both worlds to me.

Hi @jrtc27 - could you please elaborate a little on the concern that the approach in this path might be the worst of both worlds? I'm not sure I fully follow. Thanks.

If you want to have different scheduling for different CSRs, do you not need per-CSR pseudos in order to express that? This diff is ostensibly to allow for that in future, but is at a much coarser read/write/swap granularity, so doesn't really get you much over and above just scheduling CSRRW itself as a whole, just adds more complexity for little gain. IMO any CSRs we need scheduling info for should just get their own dedicated read/write/swap pseudos as and when they're needed.

The patch D99083 demonstrates the solution for FP state/control resisters. Every register and every access get separate pseudos, each of which can have their own scheduling properties.

That looks like the kind of thing I'm imagining. So can we remove the Read/Write/Swap_CSR defs from this diff and just keep the Read/Write/SwapSysReg classes for use with such pseudos?

Wed, Mar 31, 7:57 AM · Restricted Project
sepavloff added a comment to D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.
In D98936#2661228, @asb wrote:

Are there ever any cases where you _wouldn't_ want a CSR-specific pseudo in order to have control over the scheduling of it specifically? This feels a bit like a middle-ground that's the worst of both worlds to me.

Hi @jrtc27 - could you please elaborate a little on the concern that the approach in this path might be the worst of both worlds? I'm not sure I fully follow. Thanks.

If you want to have different scheduling for different CSRs, do you not need per-CSR pseudos in order to express that? This diff is ostensibly to allow for that in future, but is at a much coarser read/write/swap granularity, so doesn't really get you much over and above just scheduling CSRRW itself as a whole, just adds more complexity for little gain. IMO any CSRs we need scheduling info for should just get their own dedicated read/write/swap pseudos as and when they're needed.

Wed, Mar 31, 7:47 AM · Restricted Project
sepavloff added a comment to D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

Ping.

Wed, Mar 31, 5:48 AM · Restricted Project
sepavloff updated the summary of D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.
Wed, Mar 31, 5:15 AM · Restricted Project
sepavloff updated the diff for D94163: [RISCV] Set dependency on floating point CSRs, 1/3.

Updated patch for alternative CSR solution

Wed, Mar 31, 3:03 AM · Restricted Project

Tue, Mar 30

sepavloff updated the diff for D83036: [X86][FPEnv] Lowering of {get,set,reset}_fpmode.

Changed mode type in test fpenv32.ll from i32 to i64 to match glibc types

Tue, Mar 30, 10:04 PM · Restricted Project
sepavloff updated the diff for D83036: [X86][FPEnv] Lowering of {get,set,reset}_fpmode.

Rebased patch. Fixed issue of getConstantPool.

Tue, Mar 30, 7:46 AM · Restricted Project
sepavloff updated the diff for D82525: [FPEnv] Intrinsics for access to FP control modes.

Rebased patch

Tue, Mar 30, 3:16 AM · Restricted Project

Wed, Mar 24

sepavloff committed rGddb0bcbdff03: Add missing cases in RISCVMCExpr::getVariantKindName (authored by sepavloff).
Add missing cases in RISCVMCExpr::getVariantKindName
Wed, Mar 24, 10:58 PM
sepavloff closed D98929: Add missing cases in RISCVMCExpr::getVariantKindName.
Wed, Mar 24, 10:58 PM · Restricted Project
sepavloff updated the diff for D98929: Add missing cases in RISCVMCExpr::getVariantKindName.

Remove changes in RISCVMCExpr::getVariantKindForName

Wed, Mar 24, 4:30 AM · Restricted Project

Tue, Mar 23

sepavloff added a comment to D98929: Add missing cases in RISCVMCExpr::getVariantKindName.

Does this tiny patch require some additional changes?

Tue, Mar 23, 9:08 PM · Restricted Project
sepavloff updated the diff for D90854: [RISCV] Custom lowering of FLT_ROUNDS_.

Adapted the patch for alternative CSR implementation

Tue, Mar 23, 8:12 AM · Restricted Project
sepavloff added a comment to D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

Are there ever any cases where you _wouldn't_ want a CSR-specific pseudo in order to have control over the scheduling of it specifically? This feels a bit like a middle-ground that's the worst of both worlds to me.

Tue, Mar 23, 2:30 AM · Restricted Project
sepavloff updated the diff for D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

Updated patch

Tue, Mar 23, 2:07 AM · Restricted Project

Mon, Mar 22

sepavloff added inline comments to D99057: [TableGen] Allow BitsInit to init integer in pseudo expansion.
Mon, Mar 22, 10:56 PM · Restricted Project
sepavloff committed rGcf0f2884a1d9: [TableGen] Tiny enhancement (authored by sepavloff).
[TableGen] Tiny enhancement
Mon, Mar 22, 10:50 PM
sepavloff committed rG61fa35c3f7e8: [TableGen] Allow BitsInit to init integer in pseudo expansion (authored by sepavloff).
[TableGen] Allow BitsInit to init integer in pseudo expansion
Mon, Mar 22, 9:52 PM
sepavloff closed D99057: [TableGen] Allow BitsInit to init integer in pseudo expansion.
Mon, Mar 22, 9:52 PM · Restricted Project
sepavloff added a comment to D99057: [TableGen] Allow BitsInit to init integer in pseudo expansion.

I presume this change passes all the TableGen tests?

Mon, Mar 22, 9:46 AM · Restricted Project
sepavloff updated the diff for D99057: [TableGen] Allow BitsInit to init integer in pseudo expansion.

Addressed reviewer's notes

Mon, Mar 22, 9:12 AM · Restricted Project
sepavloff requested review of D99083: [RISCV] Introduce floating point control and state registers.
Mon, Mar 22, 8:57 AM · Restricted Project
sepavloff added a comment to D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

So to provide alternate scheduling information, we need scheduler predicates to inspect the operands to find the system register?

Mon, Mar 22, 8:17 AM · Restricted Project
sepavloff updated the diff for D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

Updated patch

Mon, Mar 22, 7:48 AM · Restricted Project
sepavloff requested review of D99057: [TableGen] Allow BitsInit to init integer in pseudo expansion.
Mon, Mar 22, 12:53 AM · Restricted Project

Mar 19 2021

sepavloff updated the diff for D98929: Add missing cases in RISCVMCExpr::getVariantKindName.

Removed unneeded assert

Mar 19 2021, 11:22 AM · Restricted Project
sepavloff updated the diff for D98929: Add missing cases in RISCVMCExpr::getVariantKindName.

Use llvm_unreachable instead of bogus return

Mar 19 2021, 10:55 AM · Restricted Project
sepavloff added a comment to D98929: Add missing cases in RISCVMCExpr::getVariantKindName.

Is it possible to test this?

Mar 19 2021, 10:45 AM · Restricted Project
sepavloff updated the diff for D98929: Add missing cases in RISCVMCExpr::getVariantKindName.

Updated patch

Mar 19 2021, 10:39 AM · Restricted Project
sepavloff added a comment to D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

CSR addresses are uimm12s not simm12s

Mar 19 2021, 8:04 AM · Restricted Project
sepavloff updated the diff for D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

Updated patch

Mar 19 2021, 8:02 AM · Restricted Project
sepavloff updated the diff for D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

Use simm12 for numbers of system registers

Mar 19 2021, 3:29 AM · Restricted Project
sepavloff added a comment to D90853: [RISCV] Add DAG nodes to represent read/write CSR.

An alternative implementation of the same functionality is provided in D98936.

Mar 19 2021, 3:17 AM · Restricted Project
sepavloff added a comment to D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

This is an alternative implementation of the functionality implemented in D90853.

Mar 19 2021, 3:16 AM · Restricted Project
sepavloff requested review of D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.
Mar 19 2021, 3:14 AM · Restricted Project
sepavloff requested review of D98929: Add missing cases in RISCVMCExpr::getVariantKindName.
Mar 19 2021, 1:59 AM · Restricted Project

Mar 17 2021

sepavloff updated the diff for D82525: [FPEnv] Intrinsics for access to FP control modes.

Added helper functions

Mar 17 2021, 9:38 AM · Restricted Project
sepavloff updated the diff for D71741: Add size of FP environment to DataLayout.

Use more consistent name: s/getFPControlModesSize/getFPControlModeSize/

Mar 17 2021, 9:34 AM · Restricted Project

Mar 16 2021

sepavloff added a comment to D90853: [RISCV] Add DAG nodes to represent read/write CSR.

My point is that:

  • Using X0 as destination is an encoding trick to save opcode space, there is no sense to expose it to higher levels, like DAG or MIR.
  • Machine instruction or DAG node which have X0 as destination register breaks DAG or MIR design, as such instruction actually is not a definitions for X0.

AArch64 has a pass that replaces defs with X0, AArch64DeadRegisterDefinitionsPass. This is how a subtract becomes a compare. So it is not unprecedented.

Mar 16 2021, 10:15 AM · Restricted Project
sepavloff added a comment to D94163: [RISCV] Set dependency on floating point CSRs, 1/3.
In D94163#2603738, @asb wrote:

We're also still unclear about the advantage of changing codegen to default to a static rounding mode (which might be a surprising change, as all software compiled to date on both GCC and LLVM has used used the dynamic rounding mode by default).

Instructions in assembler without explicit rounding mode specification get dynamic rounding mode as now. Lowering of FP operations like fadd uses static rounding mode RNE, because these operations assume default floating point environment (https://llvm.org/docs/LangRef.html#floating-point-environment). Using static rounding mode has some advantages over assuming frm to have particular value. The code that requires default rounding mode does not require setting rfm in a program where some pieces uses non-default rounding mode. Such code works as designed even if it is called from a region where other rounding mode is set. Such implementation simplifies implementation of things like #pragma STDC FENV_ROUND and make programs more robust.

That's going to break huge piles of C/C++ code that sets the (dynamic) rounding mode and expects it to have an effect on subsequent computations. I do not think that is a good idea.

Mar 16 2021, 10:03 AM · Restricted Project
sepavloff updated the summary of D71741: Add size of FP environment to DataLayout.
Mar 16 2021, 6:55 AM · Restricted Project
sepavloff updated the diff for D71741: Add size of FP environment to DataLayout.

Rebased patch. Added size of control modes.

Mar 16 2021, 6:52 AM · Restricted Project

Mar 14 2021

sepavloff added a comment to D90853: [RISCV] Add DAG nodes to represent read/write CSR.

Hi all,

Mar 14 2021, 11:19 PM · Restricted Project

Mar 5 2021

sepavloff added inline comments to D83036: [X86][FPEnv] Lowering of {get,set,reset}_fpmode.
Mar 5 2021, 10:17 AM · Restricted Project
sepavloff added inline comments to D83036: [X86][FPEnv] Lowering of {get,set,reset}_fpmode.
Mar 5 2021, 8:14 AM · Restricted Project

Mar 4 2021

sepavloff added a comment to D82525: [FPEnv] Intrinsics for access to FP control modes.

Is there any guarantee that femode_t will be the same layout for a given target in different C library implementations?

There are cases when size of fenv_t differs in different libraries. ARM uses unsigned int in glibc but unsigned long in musl.

Is unsigned long 32-bits in this case?

Yes, ARM gcc 10.2(linux) generates 4 for sizeof(unsigned long).

Mar 4 2021, 10:55 PM · Restricted Project
sepavloff added a comment to D94163: [RISCV] Set dependency on floating point CSRs, 1/3.
In D94163#2603738, @asb wrote:

We discussed this briefly in the RISC-V call as I noted this patchset has been sat open for some time. One thing that might be helpful is whether you could say a little bit more about the goal for this patchset.

Mar 4 2021, 10:48 PM · Restricted Project
sepavloff added inline comments to D83036: [X86][FPEnv] Lowering of {get,set,reset}_fpmode.
Mar 4 2021, 8:10 PM · Restricted Project
sepavloff added a comment to D82525: [FPEnv] Intrinsics for access to FP control modes.

Is there any guarantee that femode_t will be the same layout for a given target in different C library implementations?

Strictly speaking there is no such guarantee. However the obvious implementation of femode_t is the type used to store content of FP control register. Most of 16 targets supported by glibc use unsigned int as femode_t. Exceptions are alpha, ia64, sparc (unsigned long) and powerpc (double). In these cases femode_t is identical to fenv_t.

Isn't X86 using this struct which is 8 bytes?

typedef struct
  {
    unsigned short int __control_word;
    unsigned short int __glibc_reserved;
    unsigned int __mxcsr;
  }
femode_t;
Mar 4 2021, 7:43 PM · Restricted Project
sepavloff added a comment to D82525: [FPEnv] Intrinsics for access to FP control modes.

From langref it isn't obvious if the following transform is valid or not

%z = fadd_strict %x, %y
call @llvm.set.fpmode.i16(i16 %fpenv)
  =>
call @llvm.set.fpmode.i16(i16 %fpenv)
%z = fadd_strict %x, %y
Mar 4 2021, 5:40 AM · Restricted Project

Mar 3 2021

sepavloff updated the diff for D82525: [FPEnv] Intrinsics for access to FP control modes.

Extended documentation, fixed chain treatment.

Mar 3 2021, 11:28 PM · Restricted Project
sepavloff updated the diff for D83036: [X86][FPEnv] Lowering of {get,set,reset}_fpmode.

Rebased patch

Mar 3 2021, 9:54 AM · Restricted Project
sepavloff updated the summary of D82525: [FPEnv] Intrinsics for access to FP control modes.
Mar 3 2021, 5:06 AM · Restricted Project
sepavloff updated the summary of D82525: [FPEnv] Intrinsics for access to FP control modes.
Mar 3 2021, 5:05 AM · Restricted Project
sepavloff updated the diff for D82525: [FPEnv] Intrinsics for access to FP control modes.

Rebased and simplified a bit.

Mar 3 2021, 5:04 AM · Restricted Project

Mar 2 2021

sepavloff added inline comments to D74730: [FPEnv][X86] Implement lowering of llvm.set.rounding.
Mar 2 2021, 12:55 AM · Restricted Project
sepavloff updated the diff for D74730: [FPEnv][X86] Implement lowering of llvm.set.rounding.

Updated comment

Mar 2 2021, 12:53 AM · Restricted Project

Mar 1 2021

sepavloff updated the diff for D74730: [FPEnv][X86] Implement lowering of llvm.set.rounding.

Rebased patch

Mar 1 2021, 4:18 AM · Restricted Project

Feb 26 2021

sepavloff committed rG04c3071c16d7: [Driver] Flush file in locked area (authored by sepavloff).
[Driver] Flush file in locked area
Feb 26 2021, 4:04 AM
sepavloff updated the diff for D94165: [RISCV] Set dependency on floating point CSRs, 3/3.

Reduced number of instruction variants from 3 to 2 (generic and default)

Feb 26 2021, 2:41 AM · Restricted Project
sepavloff updated the diff for D94164: [RISCV] Set dependency on floating point CSRs, 2/3.

Reduced number of instruction variants from 3 to 2 (generic and default)

Feb 26 2021, 2:39 AM · Restricted Project
sepavloff updated the summary of D94163: [RISCV] Set dependency on floating point CSRs, 1/3.
Feb 26 2021, 2:37 AM · Restricted Project
sepavloff updated the diff for D94163: [RISCV] Set dependency on floating point CSRs, 1/3.

Reduced number of instruction variants from 3 to 2 (generic and default)

Feb 26 2021, 2:35 AM · Restricted Project

Feb 24 2021

sepavloff added inline comments to D97094: [Driver] Print process statistics report on CC_PRINT_PROC_STAT env variable..
Feb 24 2021, 6:30 AM · Restricted Project

Feb 20 2021

sepavloff added inline comments to D97094: [Driver] Print process statistics report on CC_PRINT_PROC_STAT env variable..
Feb 20 2021, 1:41 AM · Restricted Project
sepavloff added reviewers for D97094: [Driver] Print process statistics report on CC_PRINT_PROC_STAT env variable.: rjmccall, aganea, hans, MaskRay.
Feb 20 2021, 1:40 AM · Restricted Project

Feb 18 2021

sepavloff committed rG2c4f60e45b38: [FPEnv][AArch64] Implement lowering of llvm.set.rounding (authored by sepavloff).
[FPEnv][AArch64] Implement lowering of llvm.set.rounding
Feb 18 2021, 10:18 PM
sepavloff closed D96836: [FPEnv][AArch64] Implement lowering of llvm.set.rounding.
Feb 18 2021, 10:17 PM · Restricted Project
sepavloff added inline comments to D96836: [FPEnv][AArch64] Implement lowering of llvm.set.rounding.
Feb 18 2021, 2:15 AM · Restricted Project
sepavloff updated the diff for D96836: [FPEnv][AArch64] Implement lowering of llvm.set.rounding.

Changed variable type from unsigned to int

Feb 18 2021, 2:05 AM · Restricted Project

Feb 17 2021

sepavloff added inline comments to D96836: [FPEnv][AArch64] Implement lowering of llvm.set.rounding.
Feb 17 2021, 8:00 AM · Restricted Project

Feb 16 2021

sepavloff requested review of D96836: [FPEnv][AArch64] Implement lowering of llvm.set.rounding.
Feb 16 2021, 9:37 PM · Restricted Project

Feb 12 2021

sepavloff added inline comments to D96501: [FPEnv][ARM] Implement lowering of llvm.set.rounding.
Feb 12 2021, 8:39 PM · Restricted Project
sepavloff committed rG816053bc7175: [FPEnv][ARM] Implement lowering of llvm.set.rounding (authored by sepavloff).
[FPEnv][ARM] Implement lowering of llvm.set.rounding
Feb 12 2021, 8:18 PM
sepavloff closed D96501: [FPEnv][ARM] Implement lowering of llvm.set.rounding.
Feb 12 2021, 8:17 PM · Restricted Project
sepavloff added a comment to D96501: [FPEnv][ARM] Implement lowering of llvm.set.rounding.

The table-lookup strategy seems like overkill to me. As far as I can see, the integer mapping required is: 0→3, 3→2. 2→1, 1→0. In other words, all four input values (that can be handled at all) are just reduced by 1, mod 4. So instead of (147 >> (value << 1)) & 3, you could compute (value - 1) & 3, surely more cheaply.

Feb 12 2021, 2:49 AM · Restricted Project
sepavloff updated the diff for D96501: [FPEnv][ARM] Implement lowering of llvm.set.rounding.

Optimized FPSCR bits calculation

Feb 12 2021, 2:41 AM · Restricted Project

Feb 11 2021

sepavloff requested review of D96501: [FPEnv][ARM] Implement lowering of llvm.set.rounding.
Feb 11 2021, 6:55 AM · Restricted Project

Feb 3 2021

sepavloff added a comment to D94163: [RISCV] Set dependency on floating point CSRs, 1/3.

I still don't understand why the existence of static rounding modes in the ISA requires that we have to use them for the default environment. X86 doesn't have static rounding mode prior to AVX512 so uses dynamic in the default mode.

It is more convenient. Instructions with static rounding mode do not depend on frm so they may be scheduled more freely. Besides function with static only FP instructions may be safely called from non-default FP environment. Targets without static rounding mode don't have such possibility.

If there’s no write to frm then there shouldn’t be a scheduling issue.

Sure. Such issue rises when there is write to frm. Consider the following pseudo code:

float a = ...
for (int i = ...) {
  fesetround(FE_TOWARDZERO); // csrw frm, 1
  ...
  x[i] += floor(a); // fcvt ..., rdn

floor(a) is a loop invariant and could be hoisted off the loop. It is possible as fcvt uses static rounding. However if fcvt uses dynamic rounding, it depends on frm, which is changed above, so it cannot be moved out of the loop.

Why wouldn't that have been hoisted out of the loop by IR LICM? Machine LICM is primarily intended to move stack reloads and constant pool loads. It only runs on the outermost loop with a preheader.

Feb 3 2021, 10:35 PM · Restricted Project

Feb 1 2021

sepavloff updated the diff for D74730: [FPEnv][X86] Implement lowering of llvm.set.rounding.

Rebased patch

Feb 1 2021, 10:29 PM · Restricted Project
sepavloff added a comment to D94163: [RISCV] Set dependency on floating point CSRs, 1/3.

I still don't understand why the existence of static rounding modes in the ISA requires that we have to use them for the default environment. X86 doesn't have static rounding mode prior to AVX512 so uses dynamic in the default mode.

It is more convenient. Instructions with static rounding mode do not depend on frm so they may be scheduled more freely. Besides function with static only FP instructions may be safely called from non-default FP environment. Targets without static rounding mode don't have such possibility.

If there’s no write to frm then there shouldn’t be a scheduling issue.

Feb 1 2021, 9:10 PM · Restricted Project
sepavloff added a comment to D90853: [RISCV] Add DAG nodes to represent read/write CSR.

Hi Serge,

Using X0 as output is just a trick to have a new instruction without spending opcode. Actually such instruction does not define X0. What is the benefit of exposing this low-level encoding feature in high-level structures?

My suggestion was to avoid the situation where we have two machine instructions that overlap in their semantics. This entails that a later pass that analyses CSRs should take into account those write only forms in addition to the actual instructions. However, maybe this is not a practical issue. The number of CSR instructions is not large. It may also happen that SelectionDAG will never select a CSR write instruction that writes to X0. Or if it does, we would always use the new write-only form that you suggest.

Feb 1 2021, 5:01 AM · Restricted Project