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Modifiedllvm/include/llvm/CodeGen/MachineBasicBlock.h
Modifiedllvm/include/llvm/CodeGen/MachineInstr.h
Modifiedllvm/include/llvm/Support/TargetOpcodes.def
Modifiedllvm/include/llvm/Target/Target.td
Modifiedllvm/lib/CodeGen/DetectDeadLanes.cpp
Modifiedllvm/lib/CodeGen/ExpandPostRAPseudos.cpp
Modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
Modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
Modifiedllvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
Modifiedllvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
Modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp
Modifiedllvm/lib/CodeGen/MachineBasicBlock.cpp
Modifiedllvm/lib/CodeGen/MachineInstr.cpp
Modifiedllvm/lib/CodeGen/MachineSink.cpp
Modifiedllvm/lib/CodeGen/MachineVerifier.cpp
Modifiedllvm/lib/CodeGen/PeepholeOptimizer.cpp
Modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
Modifiedllvm/lib/CodeGen/RegAllocFast.cpp
Modifiedllvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
Modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
Modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Modifiedllvm/lib/Target/AArch64/AArch64CallLowering.cpp
Modifiedllvm/lib/Target/AArch64/AArch64FastISel.cpp
Modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
Modifiedllvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
Modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Modifiedllvm/lib/Target/Hexagon/BitTracker.cpp
Modifiedllvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
Modifiedllvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
Modifiedllvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
Modifiedllvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
Modifiedllvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
Modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
Modifiedllvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
Modifiedllvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
Modifiedllvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
Modifiedllvm/lib/Target/Hexagon/RDFCopy.cpp
Modifiedllvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
Modifiedllvm/lib/Target/Mips/MipsSEFrameLowering.cpp
Modifiedllvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
Modifiedllvm/lib/Target/X86/X86DomainReassignment.cpp
Modifiedllvm/lib/Target/X86/X86FlagsCopyLowering.cpp
Modifiedllvm/lib/Target/X86/X86FloatingPoint.cpp
Modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
Modifiedllvm/test/CodeGen/AArch64/callbr-asm-label.ll
Modifiedllvm/test/CodeGen/SystemZ/asm-20.ll
Modifiedllvm/test/CodeGen/X86/callbr-asm-label-addr.ll
Addedllvm/test/CodeGen/X86/callbr-asm-outputs-tcopy-spilling.ll
Modifiedllvm/test/CodeGen/X86/callbr-asm-outputs.ll