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llvm/include/llvm/CodeGen/TargetLowering.h
| Show First 20 Lines • Show All 1,306 Lines • ▼ Show 20 Lines | #include "llvm/IR/ConstrainedOps.def" | ||||
| /// Return true if the specified indexed load is legal on this target. | /// Return true if the specified indexed load is legal on this target. | ||||
| bool isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) const { | bool isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) const { | ||||
| return VT.isSimple() && | return VT.isSimple() && | ||||
| (getIndexedMaskedStoreAction(IdxMode, VT.getSimpleVT()) == Legal || | (getIndexedMaskedStoreAction(IdxMode, VT.getSimpleVT()) == Legal || | ||||
| getIndexedMaskedStoreAction(IdxMode, VT.getSimpleVT()) == Custom); | getIndexedMaskedStoreAction(IdxMode, VT.getSimpleVT()) == Custom); | ||||
| } | } | ||||
| // Returns true if VT is a legal index type for masked gathers/scatters | |||||
| // on this target | |||||
| virtual bool isLegalMaskedGSIndexType(EVT VT) const { | |||||
| return false; | |||||
| } | |||||
| /// Return how the condition code should be treated: either it is legal, needs | /// Return how the condition code should be treated: either it is legal, needs | ||||
| /// to be expanded to some other code sequence, or the target has a custom | /// to be expanded to some other code sequence, or the target has a custom | ||||
| /// expander for it. | /// expander for it. | ||||
| LegalizeAction | LegalizeAction | ||||
| getCondCodeAction(ISD::CondCode CC, MVT VT) const { | getCondCodeAction(ISD::CondCode CC, MVT VT) const { | ||||
| assert((unsigned)CC < array_lengthof(CondCodeActions) && | assert((unsigned)CC < array_lengthof(CondCodeActions) && | ||||
| ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) && | ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) && | ||||
| "Table isn't big enough!"); | "Table isn't big enough!"); | ||||
| ▲ Show 20 Lines • Show All 3,176 Lines • ▼ Show 20 Lines | |||||
| } | } | ||||
| // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits))) | // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits))) | ||||
| // If we're comparing for equality to zero and isCtlzFast is true, expose the | // If we're comparing for equality to zero and isCtlzFast is true, expose the | ||||
| // fact that this can be implemented as a ctlz/srl pair, so that the dag | // fact that this can be implemented as a ctlz/srl pair, so that the dag | ||||
| // combiner can fold the new nodes. | // combiner can fold the new nodes. | ||||
| SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const; | SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const; | ||||
| /// Give targets the chance to reduce the number of distinct addresing modes. | |||||
| virtual ISD::MemIndexType getCanonicalIndexType(ISD::MemIndexType IndexType, | |||||
| EVT MemVT, | |||||
| SDValue Offsets) const { | |||||
| return IndexType; | |||||
| } | |||||
| private: | private: | ||||
| SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, | SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, | ||||
| const SDLoc &DL, DAGCombinerInfo &DCI) const; | const SDLoc &DL, DAGCombinerInfo &DCI) const; | ||||
| SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, | SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, | ||||
| const SDLoc &DL, DAGCombinerInfo &DCI) const; | const SDLoc &DL, DAGCombinerInfo &DCI) const; | ||||
| SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0, | SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0, | ||||
| SDValue N1, ISD::CondCode Cond, | SDValue N1, ISD::CondCode Cond, | ||||
| Show All 35 Lines | |||||