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Differential D99965

[RISCV][Clang] Add more RVV load/store intrinsic functions.
ClosedPublic

Authored by khchen on Apr 6 2021, 9:06 AM.

Details

Reviewers
craig.topper
rogfer01
HsiangKai
evandro
liaolucy
jrtc27
Commits
rGe5a821926407: [RISCV][Clang] Add more RVV load/store intrinsic functions.
Summary

Support the following instructions.

  1. Mask load and store
  2. Vector Strided Instructions
  3. Vector Indexed Store Instructions

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Diff Detail

Event Timeline

khchen created this revision.Apr 6 2021, 9:06 AM
Herald added subscribers: vkmr, frasercrmck, dexonsmith and 22 others. · View Herald TranscriptApr 6 2021, 9:06 AM
khchen requested review of this revision.Apr 6 2021, 9:06 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 6 2021, 9:06 AM
Herald added subscribers: cfe-commits, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B97320: Diff 335537.Apr 6 2021, 10:05 AM
craig.topper accepted this revision.Apr 7 2021, 1:53 PM

LGTM

This revision is now accepted and ready to land.Apr 7 2021, 1:53 PM
khchen updated this revision to Diff 336666.Apr 11 2021, 7:26 AM

rebase

Harbormaster completed remote builds in B98151: Diff 336666.Apr 11 2021, 8:03 AM
Closed by commit rGe5a821926407: [RISCV][Clang] Add more RVV load/store intrinsic functions. (authored by khchen). · Explain WhyApr 11 2021, 7:30 PM
This revision was automatically updated to reflect the committed changes.
khchen added a commit: rGe5a821926407: [RISCV][Clang] Add more RVV load/store intrinsic functions..

Revision Contents

PathSize
clang/
include/
clang/
Basic/
206 lines
test/
CodeGen/
RISCV/
rvv-intrinsics-overloaded/
965 lines
536 lines
6523 lines
1813 lines
6523 lines
rvv-intrinsics/
112 lines
1862 lines
112 lines
6523 lines
1813 lines
6523 lines

Diff 336723

clang/include/clang/Basic/riscv_vector.td

Show First 20 Lines • Show All 493 Lines • ▼ Show 20 Linesdefvar EEWList = [["8", "(Log2EEW:3)"],
["16", "(Log2EEW:4)"], ["16", "(Log2EEW:4)"],
["32", "(Log2EEW:5)"], ["32", "(Log2EEW:5)"],
["64", "(Log2EEW:6)"]]; ["64", "(Log2EEW:6)"]];
class IsFloat<string type> { class IsFloat<string type> {
bit val = !or(!eq(type, "h"), !eq(type, "f"), !eq(type, "d")); bit val = !or(!eq(type, "h"), !eq(type, "f"), !eq(type, "d"));
} }
multiclass RVVVLEBuiltin<list<string> types> { let HasNoMaskedOverloaded = false,
let Name = NAME # "_v",
IRName = "vle",
IRNameMask ="vle_mask",
HasNoMaskedOverloaded = false,
ManualCodegen = [{ ManualCodegen = [{
IntrinsicTypes = {ResultType, Ops[1]->getType()}; IntrinsicTypes = {ResultType, Ops[1]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo()); Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
}], }],
ManualCodegenMask= [{ ManualCodegenMask= [{
IntrinsicTypes = {ResultType, Ops[3]->getType()}; IntrinsicTypes = {ResultType, Ops[3]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
}] in { }] in {
class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> {
let Name = "vle1_v";
let IRName = "vle1";
let HasMask = false;
}
multiclass RVVVLEBuiltin<list<string> types> {
let Name = NAME # "_v",
IRName = "vle",
IRNameMask ="vle_mask" in {
foreach type = types in { foreach type = types in {
def : RVVBuiltin<"v", "vPCe", type>; def : RVVBuiltin<"v", "vPCe", type>;
if !not(IsFloat<type>.val) then { if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "UvPCUe", type>; def : RVVBuiltin<"Uv", "UvPCUe", type>;
} }
} }
} }
} }
multiclass RVVIndexedLoad<string op> {
let ManualCodegen = [{
IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
}],
ManualCodegenMask = [{
IntrinsicTypes = {ResultType, Ops[2]->getType(), Ops[4]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
}] in {
foreach type = TypeList in {
foreach eew_list = EEWList in {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
let Name = op # eew # "_v", IRName = op, IRNameMask = op # "_mask" in {
def: RVVBuiltin<"v", "vPCe" # eew_type # "Uv", type>;
if !not(IsFloat<type>.val) then {
def: RVVBuiltin<"Uv", "UvPCUe" # eew_type # "Uv", type>;
}
}
}
}
}
} }
multiclass RVVVLEFFBuiltin<list<string> types> { multiclass RVVVLEFFBuiltin<list<string> types> {
let Name = NAME # "_v", let Name = NAME # "_v",
IRName = "vleff", IRName = "vleff",
IRNameMask = "vleff_mask", IRNameMask = "vleff_mask",
HasNoMaskedOverloaded = false, HasNoMaskedOverloaded = false,
ManualCodegen = [{ ManualCodegen = [{
Show All 35 Lines foreach type = types in {
// Skip floating types for unsigned versions. // Skip floating types for unsigned versions.
if !not(IsFloat<type>.val) then { if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "UvPCUePz", type>; def : RVVBuiltin<"Uv", "UvPCUePz", type>;
} }
} }
} }
} }
multiclass RVVVSEBuiltin<list<string> types> { multiclass RVVVLSEBuiltin<list<string> types> {
let Name = NAME # "_v", let Name = NAME # "_v",
IRName = "vse", IRName = "vlse",
IRNameMask = "vse_mask", IRNameMask ="vlse_mask",
HasMaskedOffOperand = false, HasNoMaskedOverloaded = false,
ManualCodegen = [{
IntrinsicTypes = {ResultType, Ops[2]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
}],
ManualCodegenMask= [{
IntrinsicTypes = {ResultType, Ops[4]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
}] in {
foreach type = types in {
def : RVVBuiltin<"v", "vPCet", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "UvPCUet", type>;
}
}
}
}
multiclass RVVIndexedLoad<string op> {
let ManualCodegen = [{
IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
}],
ManualCodegenMask = [{
IntrinsicTypes = {ResultType, Ops[2]->getType(), Ops[4]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
}] in {
foreach type = TypeList in {
foreach eew_list = EEWList in {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
let Name = op # eew # "_v", IRName = op, IRNameMask = op # "_mask" in {
def: RVVBuiltin<"v", "vPCe" # eew_type # "Uv", type>;
if !not(IsFloat<type>.val) then {
def: RVVBuiltin<"Uv", "UvPCUe" # eew_type # "Uv", type>;
}
}
}
}
}
}
let HasMaskedOffOperand = false,
PermuteOperands = [1, 0], // C/C++ Operand: (ptr, value, vl). Builtin: (value, ptr, vl) PermuteOperands = [1, 0], // C/C++ Operand: (ptr, value, vl). Builtin: (value, ptr, vl)
ManualCodegen = [{ ManualCodegen = [{
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType()}; IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType()};
}], }],
ManualCodegenMask= [{ ManualCodegenMask= [{
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[3]->getType()}; IntrinsicTypes = {Ops[0]->getType(), Ops[3]->getType()};
}] in { }] in {
class RVVVSEMaskBuiltin : RVVBuiltin<"m", "0mPUe", "c"> {
let Name = "vse1_v";
let IRName = "vse1";
let HasMask = false;
}
multiclass RVVVSEBuiltin<list<string> types> {
let Name = NAME # "_v",
IRName = "vse",
IRNameMask = "vse_mask" in {
foreach type = types in { foreach type = types in {
def : RVVBuiltin<"v", "0vPe", type>; def : RVVBuiltin<"v", "0vPe", type>;
if !not(IsFloat<type>.val) then { if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0UvPUe", type>; def : RVVBuiltin<"Uv", "0UvPUe", type>;
} }
} }
} }
} }
}
multiclass RVVVSSEBuiltin<list<string> types> {
let Name = NAME # "_v",
IRName = "vsse",
IRNameMask = "vsse_mask",
HasMaskedOffOperand = false,
PermuteOperands = [1, 2, 0], // C/C++ Operand: (ptr, stride, value, vl). Builtin: (value, ptr, stride, vl)
ManualCodegen = [{
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[3]->getType()};
}],
ManualCodegenMask= [{
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[4]->getType()};
}] in {
foreach type = types in {
def : RVVBuiltin<"v", "0vPet", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0UvPUet", type>;
}
}
}
}
multiclass RVVIndexedStore<string op> {
let HasMaskedOffOperand = false,
PermuteOperands = [1, 2, 0], // C/C++ Operand: (ptr, index, value, vl). Builtin: (value, ptr, index, vl)
ManualCodegen = [{
Ops[1] = Builder.CreateBitCast(Ops[1],Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType(), Ops[3]->getType()};
}],
ManualCodegenMask= [{
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType(), Ops[4]->getType()};
}] in {
foreach type = TypeList in {
foreach eew_list = EEWList in {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
let Name = op # eew # "_v", IRName = op, IRNameMask = op # "_mask" in {
def : RVVBuiltin<"v", "0vPe" # eew_type # "Uv", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0UvPUe" # eew_type # "Uv", type>;
}
}
}
}
}
}
// 6. Configuration-Setting Instructions // 6. Configuration-Setting Instructions
// 6.1. vsetvli/vsetvl instructions // 6.1. vsetvli/vsetvl instructions
let HasVL = false, let HasVL = false,
HasMask = false, HasMask = false,
HasSideEffects = true, HasSideEffects = true,
Log2LMUL = [0], Log2LMUL = [0],
ManualCodegen = [{IntrinsicTypes = {ResultType};}] in // Set XLEN type ManualCodegen = [{IntrinsicTypes = {ResultType};}] in // Set XLEN type
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
#define vsetvlmax_e64m8() __builtin_rvv_vsetvlimax(3, 3) #define vsetvlmax_e64m8() __builtin_rvv_vsetvlimax(3, 3)
}] in }] in
def vsetvlimax : RVVBuiltin<"", "zKzKz", "i">; def vsetvlimax : RVVBuiltin<"", "zKzKz", "i">;
} }
// 7. Vector Loads and Stores // 7. Vector Loads and Stores
// 7.4. Vector Unit-Stride Instructions // 7.4. Vector Unit-Stride Instructions
def vle1: RVVVLEMaskBuiltin;
defm vle8: RVVVLEBuiltin<["c"]>; defm vle8: RVVVLEBuiltin<["c"]>;
defm vle16: RVVVLEBuiltin<["s"]>; defm vle16: RVVVLEBuiltin<["s"]>;
defm vle32: RVVVLEBuiltin<["i","f"]>; defm vle32: RVVVLEBuiltin<["i","f"]>;
defm vle64: RVVVLEBuiltin<["l","d"]>; defm vle64: RVVVLEBuiltin<["l","d"]>;
defm vle8ff: RVVVLEFFBuiltin<["c"]>; def vse1 : RVVVSEMaskBuiltin;
defm vle16ff: RVVVLEFFBuiltin<["s"]>;
defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
defm vse8 : RVVVSEBuiltin<["c"]>; defm vse8 : RVVVSEBuiltin<["c"]>;
defm vse16: RVVVSEBuiltin<["s"]>; defm vse16: RVVVSEBuiltin<["s"]>;
defm vse32: RVVVSEBuiltin<["i","f"]>; defm vse32: RVVVSEBuiltin<["i","f"]>;
defm vse64: RVVVSEBuiltin<["l","d"]>; defm vse64: RVVVSEBuiltin<["l","d"]>;
// 7.5. Vector Strided Instructions
defm vlse8: RVVVLSEBuiltin<["c"]>;
defm vlse16: RVVVLSEBuiltin<["s"]>;
defm vlse32: RVVVLSEBuiltin<["i","f"]>;
defm vlse64: RVVVLSEBuiltin<["l","d"]>;
defm vsse8 : RVVVSSEBuiltin<["c"]>;
defm vsse16: RVVVSSEBuiltin<["s"]>;
defm vsse32: RVVVSSEBuiltin<["i","f"]>;
defm vsse64: RVVVSSEBuiltin<["l","d"]>;
// 7.6. Vector Indexed Instructions // 7.6. Vector Indexed Instructions
defm : RVVIndexedLoad<"vluxei">; defm : RVVIndexedLoad<"vluxei">;
defm : RVVIndexedLoad<"vloxei">; defm : RVVIndexedLoad<"vloxei">;
defm : RVVIndexedStore<"vsuxei">;
defm : RVVIndexedStore<"vsoxei">;
// 7.7. Unit-stride Fault-Only-First Loads
defm vle8ff: RVVVLEFFBuiltin<["c"]>;
defm vle16ff: RVVVLEFFBuiltin<["s"]>;
defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
// 12. Vector Integer Arithmetic Instructions // 12. Vector Integer Arithmetic Instructions
// 12.1. Vector Single-Width Integer Add and Subtract // 12.1. Vector Single-Width Integer Add and Subtract
defm vadd : RVVIntBinBuiltinSet; defm vadd : RVVIntBinBuiltinSet;
defm vsub : RVVIntBinBuiltinSet; defm vsub : RVVIntBinBuiltinSet;
defm vrsub : RVVOutOp1BuiltinSet<"vrsub", "csil", defm vrsub : RVVOutOp1BuiltinSet<"vrsub", "csil",
[["vx", "v", "vve"], [["vx", "v", "vve"],
["vx", "Uv", "UvUvUe"]]>; ["vx", "Uv", "UvUvUe"]]>;
▲ Show 20 Lines • Show All 296 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vlse8_v_i8mf8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8:#.*]]
// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8:#.*]]
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
//
vint8mf8_t test_vlse8_v_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
//
vint8mf4_t test_vlse8_v_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
//
vint8mf2_t test_vlse8_v_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
//
vint8m1_t test_vlse8_v_i8m1_m(vbool8_t mask, vint8m1_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
//
vint8m2_t test_vlse8_v_i8m2_m(vbool4_t mask, vint8m2_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
//
vint8m4_t test_vlse8_v_i8m4_m(vbool2_t mask, vint8m4_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
//
vint8m8_t test_vlse8_v_i8m8_m(vbool1_t mask, vint8m8_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
//
vint16mf4_t test_vlse16_v_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff,
const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
//
vint16mf2_t test_vlse16_v_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff,
const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
//
vint16m1_t test_vlse16_v_i16m1_m(vbool16_t mask, vint16m1_t maskedoff,
const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
vint16m2_t test_vlse16_v_i16m2_m(vbool8_t mask, vint16m2_t maskedoff,
const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
//
vint16m4_t test_vlse16_v_i16m4_m(vbool4_t mask, vint16m4_t maskedoff,
const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
//
vint16m8_t test_vlse16_v_i16m8_m(vbool2_t mask, vint16m8_t maskedoff,
const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
//
vint32mf2_t test_vlse32_v_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff,
const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
//
vint32m1_t test_vlse32_v_i32m1_m(vbool32_t mask, vint32m1_t maskedoff,
const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
vint32m2_t test_vlse32_v_i32m2_m(vbool16_t mask, vint32m2_t maskedoff,
const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
//
vint32m4_t test_vlse32_v_i32m4_m(vbool8_t mask, vint32m4_t maskedoff,
const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
//
vint32m8_t test_vlse32_v_i32m8_m(vbool4_t mask, vint32m8_t maskedoff,
const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_i64m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_i64m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
//
vint64m1_t test_vlse64_v_i64m1_m(vbool64_t mask, vint64m1_t maskedoff,
const int64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_i64m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_i64m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
vint64m2_t test_vlse64_v_i64m2_m(vbool32_t mask, vint64m2_t maskedoff,
const int64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_i64m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_i64m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
//
vint64m4_t test_vlse64_v_i64m4_m(vbool16_t mask, vint64m4_t maskedoff,
const int64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_i64m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_i64m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
//
vint64m8_t test_vlse64_v_i64m8_m(vbool8_t mask, vint64m8_t maskedoff,
const int64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8mf8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8mf8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
//
vuint8mf8_t test_vlse8_v_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
//
vuint8mf4_t test_vlse8_v_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
//
vuint8mf2_t test_vlse8_v_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
//
vuint8m1_t test_vlse8_v_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
//
vuint8m2_t test_vlse8_v_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
//
vuint8m4_t test_vlse8_v_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
//
vuint8m8_t test_vlse8_v_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
//
vuint16mf4_t test_vlse16_v_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff,
const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
//
vuint16mf2_t test_vlse16_v_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff,
const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
//
vuint16m1_t test_vlse16_v_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff,
const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
vuint16m2_t test_vlse16_v_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff,
const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
//
vuint16m4_t test_vlse16_v_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff,
const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
//
vuint16m8_t test_vlse16_v_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff,
const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
//
vuint32mf2_t test_vlse32_v_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff,
const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
//
vuint32m1_t test_vlse32_v_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
vuint32m2_t test_vlse32_v_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
//
vuint32m4_t test_vlse32_v_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
//
vuint32m8_t test_vlse32_v_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_u64m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_u64m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
//
vuint64m1_t test_vlse64_v_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
const uint64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_u64m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_u64m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
vuint64m2_t test_vlse64_v_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
const uint64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_u64m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_u64m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
//
vuint64m4_t test_vlse64_v_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
const uint64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_u64m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_u64m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
//
vuint64m8_t test_vlse64_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
const uint64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.i32(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
//
vfloat32mf2_t test_vlse32_v_f32mf2_m(vbool64_t mask, vfloat32mf2_t maskedoff,
const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.i32(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
//
vfloat32m1_t test_vlse32_v_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff,
const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.i32(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
//
vfloat32m2_t test_vlse32_v_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff,
const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.i32(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
//
vfloat32m4_t test_vlse32_v_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff,
const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.i32(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
//
vfloat32m8_t test_vlse32_v_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff,
const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_f64m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.i32(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_f64m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
//
vfloat64m1_t test_vlse64_v_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff,
const double *base, ptrdiff_t bstride,
size_t vl) {
return vlse64(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_f64m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.i32(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_f64m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
//
vfloat64m2_t test_vlse64_v_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff,
const double *base, ptrdiff_t bstride,
size_t vl) {
return vlse64(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_f64m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.i32(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_f64m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
//
vfloat64m4_t test_vlse64_v_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff,
const double *base, ptrdiff_t bstride,
size_t vl) {
return vlse64(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_f64m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.i32(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_f64m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
//
vfloat64m8_t test_vlse64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
const double *base, ptrdiff_t bstride,
size_t vl) {
return vlse64(mask, maskedoff, base, bstride, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s // RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
// ASM-NOT: warning // ASM-NOT: warning
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vse8_v_i8mf8( // CHECK-RV32-LABEL: @test_vse8_v_i8mf8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11:[0-9]+]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11:#.*]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8mf8( // CHECK-RV64-LABEL: @test_vse8_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11:[0-9]+]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11:#.*]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8mf8(int8_t *base, vint8mf8_t value, size_t vl) { void test_vse8_v_i8mf8(int8_t *base, vint8mf8_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8mf4( // CHECK-RV32-LABEL: @test_vse8_v_i8mf4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8mf4( // CHECK-RV64-LABEL: @test_vse8_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8mf4(int8_t *base, vint8mf4_t value, size_t vl) { void test_vse8_v_i8mf4(int8_t *base, vint8mf4_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8mf2( // CHECK-RV32-LABEL: @test_vse8_v_i8mf2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8mf2( // CHECK-RV64-LABEL: @test_vse8_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8mf2(int8_t *base, vint8mf2_t value, size_t vl) { void test_vse8_v_i8mf2(int8_t *base, vint8mf2_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8m1( // CHECK-RV32-LABEL: @test_vse8_v_i8m1(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8m1( // CHECK-RV64-LABEL: @test_vse8_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8m1(int8_t *base, vint8m1_t value, size_t vl) { void test_vse8_v_i8m1(int8_t *base, vint8m1_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8m2( // CHECK-RV32-LABEL: @test_vse8_v_i8m2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8m2( // CHECK-RV64-LABEL: @test_vse8_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8m2(int8_t *base, vint8m2_t value, size_t vl) { void test_vse8_v_i8m2(int8_t *base, vint8m2_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8m4( // CHECK-RV32-LABEL: @test_vse8_v_i8m4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8m4( // CHECK-RV64-LABEL: @test_vse8_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8m4(int8_t *base, vint8m4_t value, size_t vl) { void test_vse8_v_i8m4(int8_t *base, vint8m4_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8m8( // CHECK-RV32-LABEL: @test_vse8_v_i8m8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8m8( // CHECK-RV64-LABEL: @test_vse8_v_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8m8(int8_t *base, vint8m8_t value, size_t vl) { void test_vse8_v_i8m8(int8_t *base, vint8m8_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_i16mf4( // CHECK-RV32-LABEL: @test_vse16_v_i16mf4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_i16mf4( // CHECK-RV64-LABEL: @test_vse16_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_i16mf4(int16_t *base, vint16mf4_t value, size_t vl) { void test_vse16_v_i16mf4(int16_t *base, vint16mf4_t value, size_t vl) {
return vse16(base, value, vl); return vse16(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_i16mf2( // CHECK-RV32-LABEL: @test_vse16_v_i16mf2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_i16mf2( // CHECK-RV64-LABEL: @test_vse16_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_i16mf2(int16_t *base, vint16mf2_t value, size_t vl) { void test_vse16_v_i16mf2(int16_t *base, vint16mf2_t value, size_t vl) {
return vse16(base, value, vl); return vse16(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_i16m1( // CHECK-RV32-LABEL: @test_vse16_v_i16m1(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_i16m1( // CHECK-RV64-LABEL: @test_vse16_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_i16m1(int16_t *base, vint16m1_t value, size_t vl) { void test_vse16_v_i16m1(int16_t *base, vint16m1_t value, size_t vl) {
return vse16(base, value, vl); return vse16(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_i16m2( // CHECK-RV32-LABEL: @test_vse16_v_i16m2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_i16m2( // CHECK-RV64-LABEL: @test_vse16_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_i16m2(int16_t *base, vint16m2_t value, size_t vl) { void test_vse16_v_i16m2(int16_t *base, vint16m2_t value, size_t vl) {
return vse16(base, value, vl); return vse16(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_i16m4( // CHECK-RV32-LABEL: @test_vse16_v_i16m4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_i16m4( // CHECK-RV64-LABEL: @test_vse16_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_i16m4(int16_t *base, vint16m4_t value, size_t vl) { void test_vse16_v_i16m4(int16_t *base, vint16m4_t value, size_t vl) {
return vse16(base, value, vl); return vse16(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_i16m8( // CHECK-RV32-LABEL: @test_vse16_v_i16m8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_i16m8( // CHECK-RV64-LABEL: @test_vse16_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_i16m8(int16_t *base, vint16m8_t value, size_t vl) { void test_vse16_v_i16m8(int16_t *base, vint16m8_t value, size_t vl) {
return vse16(base, value, vl); return vse16(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_i32mf2( // CHECK-RV32-LABEL: @test_vse32_v_i32mf2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_i32mf2( // CHECK-RV64-LABEL: @test_vse32_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_i32mf2(int32_t *base, vint32mf2_t value, size_t vl) { void test_vse32_v_i32mf2(int32_t *base, vint32mf2_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_i32m1( // CHECK-RV32-LABEL: @test_vse32_v_i32m1(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_i32m1( // CHECK-RV64-LABEL: @test_vse32_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_i32m1(int32_t *base, vint32m1_t value, size_t vl) { void test_vse32_v_i32m1(int32_t *base, vint32m1_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_i32m2( // CHECK-RV32-LABEL: @test_vse32_v_i32m2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_i32m2( // CHECK-RV64-LABEL: @test_vse32_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_i32m2(int32_t *base, vint32m2_t value, size_t vl) { void test_vse32_v_i32m2(int32_t *base, vint32m2_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_i32m4( // CHECK-RV32-LABEL: @test_vse32_v_i32m4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_i32m4( // CHECK-RV64-LABEL: @test_vse32_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_i32m4(int32_t *base, vint32m4_t value, size_t vl) { void test_vse32_v_i32m4(int32_t *base, vint32m4_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_i32m8( // CHECK-RV32-LABEL: @test_vse32_v_i32m8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_i32m8( // CHECK-RV64-LABEL: @test_vse32_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_i32m8(int32_t *base, vint32m8_t value, size_t vl) { void test_vse32_v_i32m8(int32_t *base, vint32m8_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_i64m1( // CHECK-RV32-LABEL: @test_vse64_v_i64m1(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_i64m1( // CHECK-RV64-LABEL: @test_vse64_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_i64m1(int64_t *base, vint64m1_t value, size_t vl) { void test_vse64_v_i64m1(int64_t *base, vint64m1_t value, size_t vl) {
return vse64(base, value, vl); return vse64(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_i64m2( // CHECK-RV32-LABEL: @test_vse64_v_i64m2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_i64m2( // CHECK-RV64-LABEL: @test_vse64_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_i64m2(int64_t *base, vint64m2_t value, size_t vl) { void test_vse64_v_i64m2(int64_t *base, vint64m2_t value, size_t vl) {
return vse64(base, value, vl); return vse64(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_i64m4( // CHECK-RV32-LABEL: @test_vse64_v_i64m4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_i64m4( // CHECK-RV64-LABEL: @test_vse64_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_i64m4(int64_t *base, vint64m4_t value, size_t vl) { void test_vse64_v_i64m4(int64_t *base, vint64m4_t value, size_t vl) {
return vse64(base, value, vl); return vse64(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_i64m8( // CHECK-RV32-LABEL: @test_vse64_v_i64m8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_i64m8( // CHECK-RV64-LABEL: @test_vse64_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_i64m8(int64_t *base, vint64m8_t value, size_t vl) { void test_vse64_v_i64m8(int64_t *base, vint64m8_t value, size_t vl) {
return vse64(base, value, vl); return vse64(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8mf8( // CHECK-RV32-LABEL: @test_vse8_v_u8mf8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8mf8( // CHECK-RV64-LABEL: @test_vse8_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8mf8(uint8_t *base, vuint8mf8_t value, size_t vl) { void test_vse8_v_u8mf8(uint8_t *base, vuint8mf8_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8mf4( // CHECK-RV32-LABEL: @test_vse8_v_u8mf4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8mf4( // CHECK-RV64-LABEL: @test_vse8_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8mf4(uint8_t *base, vuint8mf4_t value, size_t vl) { void test_vse8_v_u8mf4(uint8_t *base, vuint8mf4_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8mf2( // CHECK-RV32-LABEL: @test_vse8_v_u8mf2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8mf2( // CHECK-RV64-LABEL: @test_vse8_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8mf2(uint8_t *base, vuint8mf2_t value, size_t vl) { void test_vse8_v_u8mf2(uint8_t *base, vuint8mf2_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8m1( // CHECK-RV32-LABEL: @test_vse8_v_u8m1(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8m1( // CHECK-RV64-LABEL: @test_vse8_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8m1(uint8_t *base, vuint8m1_t value, size_t vl) { void test_vse8_v_u8m1(uint8_t *base, vuint8m1_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8m2( // CHECK-RV32-LABEL: @test_vse8_v_u8m2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8m2( // CHECK-RV64-LABEL: @test_vse8_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8m2(uint8_t *base, vuint8m2_t value, size_t vl) { void test_vse8_v_u8m2(uint8_t *base, vuint8m2_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8m4( // CHECK-RV32-LABEL: @test_vse8_v_u8m4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8m4( // CHECK-RV64-LABEL: @test_vse8_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8m4(uint8_t *base, vuint8m4_t value, size_t vl) { void test_vse8_v_u8m4(uint8_t *base, vuint8m4_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8m8( // CHECK-RV32-LABEL: @test_vse8_v_u8m8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8m8( // CHECK-RV64-LABEL: @test_vse8_v_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8m8(uint8_t *base, vuint8m8_t value, size_t vl) { void test_vse8_v_u8m8(uint8_t *base, vuint8m8_t value, size_t vl) {
return vse8(base, value, vl); return vse8(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_u16mf4( // CHECK-RV32-LABEL: @test_vse16_v_u16mf4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_u16mf4( // CHECK-RV64-LABEL: @test_vse16_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_u16mf4(uint16_t *base, vuint16mf4_t value, size_t vl) { void test_vse16_v_u16mf4(uint16_t *base, vuint16mf4_t value, size_t vl) {
return vse16(base, value, vl); return vse16(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_u16mf2( // CHECK-RV32-LABEL: @test_vse16_v_u16mf2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_u16mf2( // CHECK-RV64-LABEL: @test_vse16_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_u16mf2(uint16_t *base, vuint16mf2_t value, size_t vl) { void test_vse16_v_u16mf2(uint16_t *base, vuint16mf2_t value, size_t vl) {
return vse16(base, value, vl); return vse16(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_u16m1( // CHECK-RV32-LABEL: @test_vse16_v_u16m1(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_u16m1( // CHECK-RV64-LABEL: @test_vse16_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_u16m1(uint16_t *base, vuint16m1_t value, size_t vl) { void test_vse16_v_u16m1(uint16_t *base, vuint16m1_t value, size_t vl) {
return vse16(base, value, vl); return vse16(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_u16m2( // CHECK-RV32-LABEL: @test_vse16_v_u16m2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_u16m2( // CHECK-RV64-LABEL: @test_vse16_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_u16m2(uint16_t *base, vuint16m2_t value, size_t vl) { void test_vse16_v_u16m2(uint16_t *base, vuint16m2_t value, size_t vl) {
return vse16(base, value, vl); return vse16(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_u16m4( // CHECK-RV32-LABEL: @test_vse16_v_u16m4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_u16m4( // CHECK-RV64-LABEL: @test_vse16_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_u16m4(uint16_t *base, vuint16m4_t value, size_t vl) { void test_vse16_v_u16m4(uint16_t *base, vuint16m4_t value, size_t vl) {
return vse16(base, value, vl); return vse16(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_u16m8( // CHECK-RV32-LABEL: @test_vse16_v_u16m8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_u16m8( // CHECK-RV64-LABEL: @test_vse16_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_u16m8(uint16_t *base, vuint16m8_t value, size_t vl) { void test_vse16_v_u16m8(uint16_t *base, vuint16m8_t value, size_t vl) {
return vse16(base, value, vl); return vse16(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_u32mf2( // CHECK-RV32-LABEL: @test_vse32_v_u32mf2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_u32mf2( // CHECK-RV64-LABEL: @test_vse32_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_u32mf2(uint32_t *base, vuint32mf2_t value, size_t vl) { void test_vse32_v_u32mf2(uint32_t *base, vuint32mf2_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_u32m1( // CHECK-RV32-LABEL: @test_vse32_v_u32m1(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_u32m1( // CHECK-RV64-LABEL: @test_vse32_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_u32m1(uint32_t *base, vuint32m1_t value, size_t vl) { void test_vse32_v_u32m1(uint32_t *base, vuint32m1_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_u32m2( // CHECK-RV32-LABEL: @test_vse32_v_u32m2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_u32m2( // CHECK-RV64-LABEL: @test_vse32_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_u32m2(uint32_t *base, vuint32m2_t value, size_t vl) { void test_vse32_v_u32m2(uint32_t *base, vuint32m2_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_u32m4( // CHECK-RV32-LABEL: @test_vse32_v_u32m4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_u32m4( // CHECK-RV64-LABEL: @test_vse32_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_u32m4(uint32_t *base, vuint32m4_t value, size_t vl) { void test_vse32_v_u32m4(uint32_t *base, vuint32m4_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_u32m8( // CHECK-RV32-LABEL: @test_vse32_v_u32m8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_u32m8( // CHECK-RV64-LABEL: @test_vse32_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_u32m8(uint32_t *base, vuint32m8_t value, size_t vl) { void test_vse32_v_u32m8(uint32_t *base, vuint32m8_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_u64m1( // CHECK-RV32-LABEL: @test_vse64_v_u64m1(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_u64m1( // CHECK-RV64-LABEL: @test_vse64_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_u64m1(uint64_t *base, vuint64m1_t value, size_t vl) { void test_vse64_v_u64m1(uint64_t *base, vuint64m1_t value, size_t vl) {
return vse64(base, value, vl); return vse64(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_u64m2( // CHECK-RV32-LABEL: @test_vse64_v_u64m2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_u64m2( // CHECK-RV64-LABEL: @test_vse64_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_u64m2(uint64_t *base, vuint64m2_t value, size_t vl) { void test_vse64_v_u64m2(uint64_t *base, vuint64m2_t value, size_t vl) {
return vse64(base, value, vl); return vse64(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_u64m4( // CHECK-RV32-LABEL: @test_vse64_v_u64m4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_u64m4( // CHECK-RV64-LABEL: @test_vse64_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_u64m4(uint64_t *base, vuint64m4_t value, size_t vl) { void test_vse64_v_u64m4(uint64_t *base, vuint64m4_t value, size_t vl) {
return vse64(base, value, vl); return vse64(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_u64m8( // CHECK-RV32-LABEL: @test_vse64_v_u64m8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_u64m8( // CHECK-RV64-LABEL: @test_vse64_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_u64m8(uint64_t *base, vuint64m8_t value, size_t vl) { void test_vse64_v_u64m8(uint64_t *base, vuint64m8_t value, size_t vl) {
return vse64(base, value, vl); return vse64(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_f32mf2( // CHECK-RV32-LABEL: @test_vse32_v_f32mf2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1f32.i32(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1f32.i32(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_f32mf2( // CHECK-RV64-LABEL: @test_vse32_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1f32.i64(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1f32.i64(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_f32mf2(float *base, vfloat32mf2_t value, size_t vl) { void test_vse32_v_f32mf2(float *base, vfloat32mf2_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_f32m1( // CHECK-RV32-LABEL: @test_vse32_v_f32m1(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2f32.i32(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2f32.i32(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_f32m1( // CHECK-RV64-LABEL: @test_vse32_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2f32.i64(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2f32.i64(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_f32m1(float *base, vfloat32m1_t value, size_t vl) { void test_vse32_v_f32m1(float *base, vfloat32m1_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_f32m2( // CHECK-RV32-LABEL: @test_vse32_v_f32m2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4f32.i32(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4f32.i32(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_f32m2( // CHECK-RV64-LABEL: @test_vse32_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4f32.i64(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4f32.i64(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_f32m2(float *base, vfloat32m2_t value, size_t vl) { void test_vse32_v_f32m2(float *base, vfloat32m2_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_f32m4( // CHECK-RV32-LABEL: @test_vse32_v_f32m4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8f32.i32(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8f32.i32(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_f32m4( // CHECK-RV64-LABEL: @test_vse32_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8f32.i64(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8f32.i64(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_f32m4(float *base, vfloat32m4_t value, size_t vl) { void test_vse32_v_f32m4(float *base, vfloat32m4_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_f32m8( // CHECK-RV32-LABEL: @test_vse32_v_f32m8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16f32.i32(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv16f32.i32(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_f32m8( // CHECK-RV64-LABEL: @test_vse32_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_f32m8(float *base, vfloat32m8_t value, size_t vl) { void test_vse32_v_f32m8(float *base, vfloat32m8_t value, size_t vl) {
return vse32(base, value, vl); return vse32(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_f64m1( // CHECK-RV32-LABEL: @test_vse64_v_f64m1(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1f64.i32(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv1f64.i32(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_f64m1( // CHECK-RV64-LABEL: @test_vse64_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_f64m1(double *base, vfloat64m1_t value, size_t vl) { void test_vse64_v_f64m1(double *base, vfloat64m1_t value, size_t vl) {
return vse64(base, value, vl); return vse64(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_f64m2( // CHECK-RV32-LABEL: @test_vse64_v_f64m2(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2f64.i32(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv2f64.i32(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_f64m2( // CHECK-RV64-LABEL: @test_vse64_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2f64.i64(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2f64.i64(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_f64m2(double *base, vfloat64m2_t value, size_t vl) { void test_vse64_v_f64m2(double *base, vfloat64m2_t value, size_t vl) {
return vse64(base, value, vl); return vse64(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_f64m4( // CHECK-RV32-LABEL: @test_vse64_v_f64m4(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4f64.i32(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv4f64.i32(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_f64m4( // CHECK-RV64-LABEL: @test_vse64_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4f64.i64(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4f64.i64(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_f64m4(double *base, vfloat64m4_t value, size_t vl) { void test_vse64_v_f64m4(double *base, vfloat64m4_t value, size_t vl) {
return vse64(base, value, vl); return vse64(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_f64m8( // CHECK-RV32-LABEL: @test_vse64_v_f64m8(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8f64.i32(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.nxv8f64.i32(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_f64m8( // CHECK-RV64-LABEL: @test_vse64_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8f64.i64(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8f64.i64(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_f64m8(double *base, vfloat64m8_t value, size_t vl) { void test_vse64_v_f64m8(double *base, vfloat64m8_t value, size_t vl) {
return vse64(base, value, vl); return vse64(base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8mf8_m( // CHECK-RV32-LABEL: @test_vse8_v_i8mf8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8mf8_m( // CHECK-RV64-LABEL: @test_vse8_v_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8mf8_m(vbool64_t mask, int8_t *base, vint8mf8_t value, size_t vl) { void test_vse8_v_i8mf8_m(vbool64_t mask, int8_t *base, vint8mf8_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8mf4_m( // CHECK-RV32-LABEL: @test_vse8_v_i8mf4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8mf4_m( // CHECK-RV64-LABEL: @test_vse8_v_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8mf4_m(vbool32_t mask, int8_t *base, vint8mf4_t value, size_t vl) { void test_vse8_v_i8mf4_m(vbool32_t mask, int8_t *base, vint8mf4_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8mf2_m( // CHECK-RV32-LABEL: @test_vse8_v_i8mf2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8mf2_m( // CHECK-RV64-LABEL: @test_vse8_v_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8mf2_m(vbool16_t mask, int8_t *base, vint8mf2_t value, size_t vl) { void test_vse8_v_i8mf2_m(vbool16_t mask, int8_t *base, vint8mf2_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8m1_m( // CHECK-RV32-LABEL: @test_vse8_v_i8m1_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8m1_m( // CHECK-RV64-LABEL: @test_vse8_v_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8m1_m(vbool8_t mask, int8_t *base, vint8m1_t value, size_t vl) { void test_vse8_v_i8m1_m(vbool8_t mask, int8_t *base, vint8m1_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8m2_m( // CHECK-RV32-LABEL: @test_vse8_v_i8m2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8m2_m( // CHECK-RV64-LABEL: @test_vse8_v_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8m2_m(vbool4_t mask, int8_t *base, vint8m2_t value, size_t vl) { void test_vse8_v_i8m2_m(vbool4_t mask, int8_t *base, vint8m2_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8m4_m( // CHECK-RV32-LABEL: @test_vse8_v_i8m4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8m4_m( // CHECK-RV64-LABEL: @test_vse8_v_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8m4_m(vbool2_t mask, int8_t *base, vint8m4_t value, size_t vl) { void test_vse8_v_i8m4_m(vbool2_t mask, int8_t *base, vint8m4_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_i8m8_m( // CHECK-RV32-LABEL: @test_vse8_v_i8m8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_i8m8_m( // CHECK-RV64-LABEL: @test_vse8_v_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_i8m8_m(vbool1_t mask, int8_t *base, vint8m8_t value, size_t vl) { void test_vse8_v_i8m8_m(vbool1_t mask, int8_t *base, vint8m8_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_i16mf4_m( // CHECK-RV32-LABEL: @test_vse16_v_i16mf4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_i16mf4_m( // CHECK-RV64-LABEL: @test_vse16_v_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_i16mf4_m(vbool64_t mask, int16_t *base, vint16mf4_t value, size_t vl) { void test_vse16_v_i16mf4_m(vbool64_t mask, int16_t *base, vint16mf4_t value, size_t vl) {
return vse16(mask, base, value, vl); return vse16(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_i16mf2_m( // CHECK-RV32-LABEL: @test_vse16_v_i16mf2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_i16mf2_m( // CHECK-RV64-LABEL: @test_vse16_v_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_i16mf2_m(vbool32_t mask, int16_t *base, vint16mf2_t value, size_t vl) { void test_vse16_v_i16mf2_m(vbool32_t mask, int16_t *base, vint16mf2_t value, size_t vl) {
return vse16(mask, base, value, vl); return vse16(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_i16m1_m( // CHECK-RV32-LABEL: @test_vse16_v_i16m1_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_i16m1_m( // CHECK-RV64-LABEL: @test_vse16_v_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_i16m1_m(vbool16_t mask, int16_t *base, vint16m1_t value, size_t vl) { void test_vse16_v_i16m1_m(vbool16_t mask, int16_t *base, vint16m1_t value, size_t vl) {
return vse16(mask, base, value, vl); return vse16(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_i16m2_m( // CHECK-RV32-LABEL: @test_vse16_v_i16m2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_i16m2_m( // CHECK-RV64-LABEL: @test_vse16_v_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_i16m2_m(vbool8_t mask, int16_t *base, vint16m2_t value, size_t vl) { void test_vse16_v_i16m2_m(vbool8_t mask, int16_t *base, vint16m2_t value, size_t vl) {
return vse16(mask, base, value, vl); return vse16(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_i16m4_m( // CHECK-RV32-LABEL: @test_vse16_v_i16m4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_i16m4_m( // CHECK-RV64-LABEL: @test_vse16_v_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_i16m4_m(vbool4_t mask, int16_t *base, vint16m4_t value, size_t vl) { void test_vse16_v_i16m4_m(vbool4_t mask, int16_t *base, vint16m4_t value, size_t vl) {
return vse16(mask, base, value, vl); return vse16(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_i16m8_m( // CHECK-RV32-LABEL: @test_vse16_v_i16m8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_i16m8_m( // CHECK-RV64-LABEL: @test_vse16_v_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_i16m8_m(vbool2_t mask, int16_t *base, vint16m8_t value, size_t vl) { void test_vse16_v_i16m8_m(vbool2_t mask, int16_t *base, vint16m8_t value, size_t vl) {
return vse16(mask, base, value, vl); return vse16(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_i32mf2_m( // CHECK-RV32-LABEL: @test_vse32_v_i32mf2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_i32mf2_m( // CHECK-RV64-LABEL: @test_vse32_v_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_i32mf2_m(vbool64_t mask, int32_t *base, vint32mf2_t value, size_t vl) { void test_vse32_v_i32mf2_m(vbool64_t mask, int32_t *base, vint32mf2_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_i32m1_m( // CHECK-RV32-LABEL: @test_vse32_v_i32m1_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_i32m1_m( // CHECK-RV64-LABEL: @test_vse32_v_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_i32m1_m(vbool32_t mask, int32_t *base, vint32m1_t value, size_t vl) { void test_vse32_v_i32m1_m(vbool32_t mask, int32_t *base, vint32m1_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_i32m2_m( // CHECK-RV32-LABEL: @test_vse32_v_i32m2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_i32m2_m( // CHECK-RV64-LABEL: @test_vse32_v_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_i32m2_m(vbool16_t mask, int32_t *base, vint32m2_t value, size_t vl) { void test_vse32_v_i32m2_m(vbool16_t mask, int32_t *base, vint32m2_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_i32m4_m( // CHECK-RV32-LABEL: @test_vse32_v_i32m4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_i32m4_m( // CHECK-RV64-LABEL: @test_vse32_v_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_i32m4_m(vbool8_t mask, int32_t *base, vint32m4_t value, size_t vl) { void test_vse32_v_i32m4_m(vbool8_t mask, int32_t *base, vint32m4_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_i32m8_m( // CHECK-RV32-LABEL: @test_vse32_v_i32m8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_i32m8_m( // CHECK-RV64-LABEL: @test_vse32_v_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_i32m8_m(vbool4_t mask, int32_t *base, vint32m8_t value, size_t vl) { void test_vse32_v_i32m8_m(vbool4_t mask, int32_t *base, vint32m8_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_i64m1_m( // CHECK-RV32-LABEL: @test_vse64_v_i64m1_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_i64m1_m( // CHECK-RV64-LABEL: @test_vse64_v_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_i64m1_m(vbool64_t mask, int64_t *base, vint64m1_t value, size_t vl) { void test_vse64_v_i64m1_m(vbool64_t mask, int64_t *base, vint64m1_t value, size_t vl) {
return vse64(mask, base, value, vl); return vse64(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_i64m2_m( // CHECK-RV32-LABEL: @test_vse64_v_i64m2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_i64m2_m( // CHECK-RV64-LABEL: @test_vse64_v_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_i64m2_m(vbool32_t mask, int64_t *base, vint64m2_t value, size_t vl) { void test_vse64_v_i64m2_m(vbool32_t mask, int64_t *base, vint64m2_t value, size_t vl) {
return vse64(mask, base, value, vl); return vse64(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_i64m4_m( // CHECK-RV32-LABEL: @test_vse64_v_i64m4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_i64m4_m( // CHECK-RV64-LABEL: @test_vse64_v_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_i64m4_m(vbool16_t mask, int64_t *base, vint64m4_t value, size_t vl) { void test_vse64_v_i64m4_m(vbool16_t mask, int64_t *base, vint64m4_t value, size_t vl) {
return vse64(mask, base, value, vl); return vse64(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_i64m8_m( // CHECK-RV32-LABEL: @test_vse64_v_i64m8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_i64m8_m( // CHECK-RV64-LABEL: @test_vse64_v_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_i64m8_m(vbool8_t mask, int64_t *base, vint64m8_t value, size_t vl) { void test_vse64_v_i64m8_m(vbool8_t mask, int64_t *base, vint64m8_t value, size_t vl) {
return vse64(mask, base, value, vl); return vse64(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8mf8_m( // CHECK-RV32-LABEL: @test_vse8_v_u8mf8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8mf8_m( // CHECK-RV64-LABEL: @test_vse8_v_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8mf8_m(vbool64_t mask, uint8_t *base, vuint8mf8_t value, size_t vl) { void test_vse8_v_u8mf8_m(vbool64_t mask, uint8_t *base, vuint8mf8_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8mf4_m( // CHECK-RV32-LABEL: @test_vse8_v_u8mf4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8mf4_m( // CHECK-RV64-LABEL: @test_vse8_v_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8mf4_m(vbool32_t mask, uint8_t *base, vuint8mf4_t value, size_t vl) { void test_vse8_v_u8mf4_m(vbool32_t mask, uint8_t *base, vuint8mf4_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8mf2_m( // CHECK-RV32-LABEL: @test_vse8_v_u8mf2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8mf2_m( // CHECK-RV64-LABEL: @test_vse8_v_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8mf2_m(vbool16_t mask, uint8_t *base, vuint8mf2_t value, size_t vl) { void test_vse8_v_u8mf2_m(vbool16_t mask, uint8_t *base, vuint8mf2_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8m1_m( // CHECK-RV32-LABEL: @test_vse8_v_u8m1_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8m1_m( // CHECK-RV64-LABEL: @test_vse8_v_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8m1_m(vbool8_t mask, uint8_t *base, vuint8m1_t value, size_t vl) { void test_vse8_v_u8m1_m(vbool8_t mask, uint8_t *base, vuint8m1_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8m2_m( // CHECK-RV32-LABEL: @test_vse8_v_u8m2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8m2_m( // CHECK-RV64-LABEL: @test_vse8_v_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8m2_m(vbool4_t mask, uint8_t *base, vuint8m2_t value, size_t vl) { void test_vse8_v_u8m2_m(vbool4_t mask, uint8_t *base, vuint8m2_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8m4_m( // CHECK-RV32-LABEL: @test_vse8_v_u8m4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8m4_m( // CHECK-RV64-LABEL: @test_vse8_v_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8m4_m(vbool2_t mask, uint8_t *base, vuint8m4_t value, size_t vl) { void test_vse8_v_u8m4_m(vbool2_t mask, uint8_t *base, vuint8m4_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse8_v_u8m8_m( // CHECK-RV32-LABEL: @test_vse8_v_u8m8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse8_v_u8m8_m( // CHECK-RV64-LABEL: @test_vse8_v_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse8_v_u8m8_m(vbool1_t mask, uint8_t *base, vuint8m8_t value, size_t vl) { void test_vse8_v_u8m8_m(vbool1_t mask, uint8_t *base, vuint8m8_t value, size_t vl) {
return vse8(mask, base, value, vl); return vse8(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_u16mf4_m( // CHECK-RV32-LABEL: @test_vse16_v_u16mf4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_u16mf4_m( // CHECK-RV64-LABEL: @test_vse16_v_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_u16mf4_m(vbool64_t mask, uint16_t *base, vuint16mf4_t value, size_t vl) { void test_vse16_v_u16mf4_m(vbool64_t mask, uint16_t *base, vuint16mf4_t value, size_t vl) {
return vse16(mask, base, value, vl); return vse16(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_u16mf2_m( // CHECK-RV32-LABEL: @test_vse16_v_u16mf2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_u16mf2_m( // CHECK-RV64-LABEL: @test_vse16_v_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_u16mf2_m(vbool32_t mask, uint16_t *base, vuint16mf2_t value, size_t vl) { void test_vse16_v_u16mf2_m(vbool32_t mask, uint16_t *base, vuint16mf2_t value, size_t vl) {
return vse16(mask, base, value, vl); return vse16(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_u16m1_m( // CHECK-RV32-LABEL: @test_vse16_v_u16m1_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_u16m1_m( // CHECK-RV64-LABEL: @test_vse16_v_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_u16m1_m(vbool16_t mask, uint16_t *base, vuint16m1_t value, size_t vl) { void test_vse16_v_u16m1_m(vbool16_t mask, uint16_t *base, vuint16m1_t value, size_t vl) {
return vse16(mask, base, value, vl); return vse16(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_u16m2_m( // CHECK-RV32-LABEL: @test_vse16_v_u16m2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_u16m2_m( // CHECK-RV64-LABEL: @test_vse16_v_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_u16m2_m(vbool8_t mask, uint16_t *base, vuint16m2_t value, size_t vl) { void test_vse16_v_u16m2_m(vbool8_t mask, uint16_t *base, vuint16m2_t value, size_t vl) {
return vse16(mask, base, value, vl); return vse16(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_u16m4_m( // CHECK-RV32-LABEL: @test_vse16_v_u16m4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_u16m4_m( // CHECK-RV64-LABEL: @test_vse16_v_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_u16m4_m(vbool4_t mask, uint16_t *base, vuint16m4_t value, size_t vl) { void test_vse16_v_u16m4_m(vbool4_t mask, uint16_t *base, vuint16m4_t value, size_t vl) {
return vse16(mask, base, value, vl); return vse16(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse16_v_u16m8_m( // CHECK-RV32-LABEL: @test_vse16_v_u16m8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse16_v_u16m8_m( // CHECK-RV64-LABEL: @test_vse16_v_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse16_v_u16m8_m(vbool2_t mask, uint16_t *base, vuint16m8_t value, size_t vl) { void test_vse16_v_u16m8_m(vbool2_t mask, uint16_t *base, vuint16m8_t value, size_t vl) {
return vse16(mask, base, value, vl); return vse16(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_u32mf2_m( // CHECK-RV32-LABEL: @test_vse32_v_u32mf2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_u32mf2_m( // CHECK-RV64-LABEL: @test_vse32_v_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_u32mf2_m(vbool64_t mask, uint32_t *base, vuint32mf2_t value, size_t vl) { void test_vse32_v_u32mf2_m(vbool64_t mask, uint32_t *base, vuint32mf2_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_u32m1_m( // CHECK-RV32-LABEL: @test_vse32_v_u32m1_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_u32m1_m( // CHECK-RV64-LABEL: @test_vse32_v_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_u32m1_m(vbool32_t mask, uint32_t *base, vuint32m1_t value, size_t vl) { void test_vse32_v_u32m1_m(vbool32_t mask, uint32_t *base, vuint32m1_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_u32m2_m( // CHECK-RV32-LABEL: @test_vse32_v_u32m2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_u32m2_m( // CHECK-RV64-LABEL: @test_vse32_v_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_u32m2_m(vbool16_t mask, uint32_t *base, vuint32m2_t value, size_t vl) { void test_vse32_v_u32m2_m(vbool16_t mask, uint32_t *base, vuint32m2_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_u32m4_m( // CHECK-RV32-LABEL: @test_vse32_v_u32m4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_u32m4_m( // CHECK-RV64-LABEL: @test_vse32_v_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_u32m4_m(vbool8_t mask, uint32_t *base, vuint32m4_t value, size_t vl) { void test_vse32_v_u32m4_m(vbool8_t mask, uint32_t *base, vuint32m4_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_u32m8_m( // CHECK-RV32-LABEL: @test_vse32_v_u32m8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_u32m8_m( // CHECK-RV64-LABEL: @test_vse32_v_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_u32m8_m(vbool4_t mask, uint32_t *base, vuint32m8_t value, size_t vl) { void test_vse32_v_u32m8_m(vbool4_t mask, uint32_t *base, vuint32m8_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_u64m1_m( // CHECK-RV32-LABEL: @test_vse64_v_u64m1_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_u64m1_m( // CHECK-RV64-LABEL: @test_vse64_v_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_u64m1_m(vbool64_t mask, uint64_t *base, vuint64m1_t value, size_t vl) { void test_vse64_v_u64m1_m(vbool64_t mask, uint64_t *base, vuint64m1_t value, size_t vl) {
return vse64(mask, base, value, vl); return vse64(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_u64m2_m( // CHECK-RV32-LABEL: @test_vse64_v_u64m2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_u64m2_m( // CHECK-RV64-LABEL: @test_vse64_v_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_u64m2_m(vbool32_t mask, uint64_t *base, vuint64m2_t value, size_t vl) { void test_vse64_v_u64m2_m(vbool32_t mask, uint64_t *base, vuint64m2_t value, size_t vl) {
return vse64(mask, base, value, vl); return vse64(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_u64m4_m( // CHECK-RV32-LABEL: @test_vse64_v_u64m4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_u64m4_m( // CHECK-RV64-LABEL: @test_vse64_v_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_u64m4_m(vbool16_t mask, uint64_t *base, vuint64m4_t value, size_t vl) { void test_vse64_v_u64m4_m(vbool16_t mask, uint64_t *base, vuint64m4_t value, size_t vl) {
return vse64(mask, base, value, vl); return vse64(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_u64m8_m( // CHECK-RV32-LABEL: @test_vse64_v_u64m8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_u64m8_m( // CHECK-RV64-LABEL: @test_vse64_v_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_u64m8_m(vbool8_t mask, uint64_t *base, vuint64m8_t value, size_t vl) { void test_vse64_v_u64m8_m(vbool8_t mask, uint64_t *base, vuint64m8_t value, size_t vl) {
return vse64(mask, base, value, vl); return vse64(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_f32mf2_m( // CHECK-RV32-LABEL: @test_vse32_v_f32mf2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1f32.i32(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1f32.i32(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_f32mf2_m( // CHECK-RV64-LABEL: @test_vse32_v_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1f32.i64(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1f32.i64(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_f32mf2_m(vbool64_t mask, float *base, vfloat32mf2_t value, size_t vl) { void test_vse32_v_f32mf2_m(vbool64_t mask, float *base, vfloat32mf2_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_f32m1_m( // CHECK-RV32-LABEL: @test_vse32_v_f32m1_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2f32.i32(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2f32.i32(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_f32m1_m( // CHECK-RV64-LABEL: @test_vse32_v_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2f32.i64(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2f32.i64(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_f32m1_m(vbool32_t mask, float *base, vfloat32m1_t value, size_t vl) { void test_vse32_v_f32m1_m(vbool32_t mask, float *base, vfloat32m1_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_f32m2_m( // CHECK-RV32-LABEL: @test_vse32_v_f32m2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4f32.i32(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4f32.i32(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_f32m2_m( // CHECK-RV64-LABEL: @test_vse32_v_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4f32.i64(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4f32.i64(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_f32m2_m(vbool16_t mask, float *base, vfloat32m2_t value, size_t vl) { void test_vse32_v_f32m2_m(vbool16_t mask, float *base, vfloat32m2_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_f32m4_m( // CHECK-RV32-LABEL: @test_vse32_v_f32m4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8f32.i32(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8f32.i32(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_f32m4_m( // CHECK-RV64-LABEL: @test_vse32_v_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8f32.i64(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8f32.i64(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_f32m4_m(vbool8_t mask, float *base, vfloat32m4_t value, size_t vl) { void test_vse32_v_f32m4_m(vbool8_t mask, float *base, vfloat32m4_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse32_v_f32m8_m( // CHECK-RV32-LABEL: @test_vse32_v_f32m8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16f32.i32(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv16f32.i32(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse32_v_f32m8_m( // CHECK-RV64-LABEL: @test_vse32_v_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16f32.i64(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16f32.i64(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse32_v_f32m8_m(vbool4_t mask, float *base, vfloat32m8_t value, size_t vl) { void test_vse32_v_f32m8_m(vbool4_t mask, float *base, vfloat32m8_t value, size_t vl) {
return vse32(mask, base, value, vl); return vse32(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_f64m1_m( // CHECK-RV32-LABEL: @test_vse64_v_f64m1_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1f64.i32(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv1f64.i32(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_f64m1_m( // CHECK-RV64-LABEL: @test_vse64_v_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1f64.i64(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1f64.i64(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_f64m1_m(vbool64_t mask, double *base, vfloat64m1_t value, size_t vl) { void test_vse64_v_f64m1_m(vbool64_t mask, double *base, vfloat64m1_t value, size_t vl) {
return vse64(mask, base, value, vl); return vse64(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_f64m2_m( // CHECK-RV32-LABEL: @test_vse64_v_f64m2_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2f64.i32(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv2f64.i32(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_f64m2_m( // CHECK-RV64-LABEL: @test_vse64_v_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2f64.i64(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2f64.i64(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_f64m2_m(vbool32_t mask, double *base, vfloat64m2_t value, size_t vl) { void test_vse64_v_f64m2_m(vbool32_t mask, double *base, vfloat64m2_t value, size_t vl) {
return vse64(mask, base, value, vl); return vse64(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_f64m4_m( // CHECK-RV32-LABEL: @test_vse64_v_f64m4_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4f64.i32(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv4f64.i32(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_f64m4_m( // CHECK-RV64-LABEL: @test_vse64_v_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4f64.i64(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4f64.i64(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_f64m4_m(vbool16_t mask, double *base, vfloat64m4_t value, size_t vl) { void test_vse64_v_f64m4_m(vbool16_t mask, double *base, vfloat64m4_t value, size_t vl) {
return vse64(mask, base, value, vl); return vse64(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse64_v_f64m8_m( // CHECK-RV32-LABEL: @test_vse64_v_f64m8_m(
// CHECK-RV32-NEXT: entry: // CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8f64.i32(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV32-NEXT: call void @llvm.riscv.vse.mask.nxv8f64.i32(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void // CHECK-RV32-NEXT: ret void
// //
// CHECK-RV64-LABEL: @test_vse64_v_f64m8_m( // CHECK-RV64-LABEL: @test_vse64_v_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8f64.i64(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) #[[ATTR11]] // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8f64.i64(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_f64m8_m(vbool8_t mask, double *base, vfloat64m8_t value, size_t vl) { void test_vse64_v_f64m8_m(vbool8_t mask, double *base, vfloat64m8_t value, size_t vl) {
return vse64(mask, base, value, vl); return vse64(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse1_v_b1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv64i1.i32(<vscale x 64 x i1> [[VALUE:%.*]], <vscale x 64 x i1>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv64i1.i64(<vscale x 64 x i1> [[VALUE:%.*]], <vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b1(uint8_t *base, vbool1_t value, size_t vl) {
return vse1(base, value, vl);
}
// CHECK-RV32-LABEL: @test_vse1_v_b2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv32i1.i32(<vscale x 32 x i1> [[VALUE:%.*]], <vscale x 32 x i1>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv32i1.i64(<vscale x 32 x i1> [[VALUE:%.*]], <vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b2(uint8_t *base, vbool2_t value, size_t vl) {
return vse1(base, value, vl);
}
// CHECK-RV32-LABEL: @test_vse1_v_b4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv16i1.i32(<vscale x 16 x i1> [[VALUE:%.*]], <vscale x 16 x i1>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv16i1.i64(<vscale x 16 x i1> [[VALUE:%.*]], <vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b4(uint8_t *base, vbool4_t value, size_t vl) {
return vse1(base, value, vl);
}
// CHECK-RV32-LABEL: @test_vse1_v_b8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv8i1.i32(<vscale x 8 x i1> [[VALUE:%.*]], <vscale x 8 x i1>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv8i1.i64(<vscale x 8 x i1> [[VALUE:%.*]], <vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b8(uint8_t *base, vbool8_t value, size_t vl) {
return vse1(base, value, vl);
}
// CHECK-RV32-LABEL: @test_vse1_v_b16(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv4i1.i32(<vscale x 4 x i1> [[VALUE:%.*]], <vscale x 4 x i1>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv4i1.i64(<vscale x 4 x i1> [[VALUE:%.*]], <vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b16(uint8_t *base, vbool16_t value, size_t vl) {
return vse1(base, value, vl);
}
// CHECK-RV32-LABEL: @test_vse1_v_b32(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv2i1.i32(<vscale x 2 x i1> [[VALUE:%.*]], <vscale x 2 x i1>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv2i1.i64(<vscale x 2 x i1> [[VALUE:%.*]], <vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b32(uint8_t *base, vbool32_t value, size_t vl) {
return vse1(base, value, vl);
}
// CHECK-RV32-LABEL: @test_vse1_v_b64(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv1i1.i32(<vscale x 1 x i1> [[VALUE:%.*]], <vscale x 1 x i1>* [[TMP0]], i32 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv1i1.i64(<vscale x 1 x i1> [[VALUE:%.*]], <vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]]) [[ATTR11]]
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b64(uint8_t *base, vbool64_t value, size_t vl) {
return vse1(base, value, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c

  • This file was added.
This file has a very large number of changes (6,523 lines). Show File Contents

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8:#.*]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8mf8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8:#.*]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8mf8(int8_t *base, ptrdiff_t bstride, vint8mf8_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8mf4(int8_t *base, ptrdiff_t bstride, vint8mf4_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8mf2(int8_t *base, ptrdiff_t bstride, vint8mf2_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m1(int8_t *base, ptrdiff_t bstride, vint8m1_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m2(int8_t *base, ptrdiff_t bstride, vint8m2_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m4(int8_t *base, ptrdiff_t bstride, vint8m4_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m8(int8_t *base, ptrdiff_t bstride, vint8m8_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16mf4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16mf4(int16_t *base, ptrdiff_t bstride, vint16mf4_t value,
size_t vl) {
return vsse16(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16mf2(int16_t *base, ptrdiff_t bstride, vint16mf2_t value,
size_t vl) {
return vsse16(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m1(int16_t *base, ptrdiff_t bstride, vint16m1_t value,
size_t vl) {
return vsse16(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m2(int16_t *base, ptrdiff_t bstride, vint16m2_t value,
size_t vl) {
return vsse16(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m4(int16_t *base, ptrdiff_t bstride, vint16m4_t value,
size_t vl) {
return vsse16(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m8(int16_t *base, ptrdiff_t bstride, vint16m8_t value,
size_t vl) {
return vsse16(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32mf2(int32_t *base, ptrdiff_t bstride, vint32mf2_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m1(int32_t *base, ptrdiff_t bstride, vint32m1_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m2(int32_t *base, ptrdiff_t bstride, vint32m2_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m4(int32_t *base, ptrdiff_t bstride, vint32m4_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m8(int32_t *base, ptrdiff_t bstride, vint32m8_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m1(int64_t *base, ptrdiff_t bstride, vint64m1_t value,
size_t vl) {
return vsse64(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m2(int64_t *base, ptrdiff_t bstride, vint64m2_t value,
size_t vl) {
return vsse64(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m4(int64_t *base, ptrdiff_t bstride, vint64m4_t value,
size_t vl) {
return vsse64(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m8(int64_t *base, ptrdiff_t bstride, vint64m8_t value,
size_t vl) {
return vsse64(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8mf8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8mf8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8mf8(uint8_t *base, ptrdiff_t bstride, vuint8mf8_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8mf4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8mf4(uint8_t *base, ptrdiff_t bstride, vuint8mf4_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8mf2(uint8_t *base, ptrdiff_t bstride, vuint8mf2_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m1(uint8_t *base, ptrdiff_t bstride, vuint8m1_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m2(uint8_t *base, ptrdiff_t bstride, vuint8m2_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m4(uint8_t *base, ptrdiff_t bstride, vuint8m4_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m8(uint8_t *base, ptrdiff_t bstride, vuint8m8_t value,
size_t vl) {
return vsse8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16mf4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16mf4(uint16_t *base, ptrdiff_t bstride, vuint16mf4_t value,
size_t vl) {
return vsse16(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16mf2(uint16_t *base, ptrdiff_t bstride, vuint16mf2_t value,
size_t vl) {
return vsse16(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m1(uint16_t *base, ptrdiff_t bstride, vuint16m1_t value,
size_t vl) {
return vsse16(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m2(uint16_t *base, ptrdiff_t bstride, vuint16m2_t value,
size_t vl) {
return vsse16(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m4(uint16_t *base, ptrdiff_t bstride, vuint16m4_t value,
size_t vl) {
return vsse16(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m8(uint16_t *base, ptrdiff_t bstride, vuint16m8_t value,
size_t vl) {
return vsse16(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32mf2(uint32_t *base, ptrdiff_t bstride, vuint32mf2_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m1(uint32_t *base, ptrdiff_t bstride, vuint32m1_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m2(uint32_t *base, ptrdiff_t bstride, vuint32m2_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m4(uint32_t *base, ptrdiff_t bstride, vuint32m4_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m8(uint32_t *base, ptrdiff_t bstride, vuint32m8_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m1(uint64_t *base, ptrdiff_t bstride, vuint64m1_t value,
size_t vl) {
return vsse64(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m2(uint64_t *base, ptrdiff_t bstride, vuint64m2_t value,
size_t vl) {
return vsse64(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m4(uint64_t *base, ptrdiff_t bstride, vuint64m4_t value,
size_t vl) {
return vsse64(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m8(uint64_t *base, ptrdiff_t bstride, vuint64m8_t value,
size_t vl) {
return vsse64(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1f32.i32(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1f32.i64(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32mf2(float *base, ptrdiff_t bstride, vfloat32mf2_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2f32.i32(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2f32.i64(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m1(float *base, ptrdiff_t bstride, vfloat32m1_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4f32.i32(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4f32.i64(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m2(float *base, ptrdiff_t bstride, vfloat32m2_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8f32.i32(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8f32.i64(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m4(float *base, ptrdiff_t bstride, vfloat32m4_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16f32.i32(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16f32.i64(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m8(float *base, ptrdiff_t bstride, vfloat32m8_t value,
size_t vl) {
return vsse32(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1f64.i32(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1f64.i64(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m1(double *base, ptrdiff_t bstride, vfloat64m1_t value,
size_t vl) {
return vsse64(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2f64.i32(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2f64.i64(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m2(double *base, ptrdiff_t bstride, vfloat64m2_t value,
size_t vl) {
return vsse64(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4f64.i32(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4f64.i64(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m4(double *base, ptrdiff_t bstride, vfloat64m4_t value,
size_t vl) {
return vsse64(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8f64.i32(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8f64.i64(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m8(double *base, ptrdiff_t bstride, vfloat64m8_t value,
size_t vl) {
return vsse64(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8mf8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8mf8_m(vbool64_t mask, int8_t *base, ptrdiff_t bstride,
vint8mf8_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8mf4_m(vbool32_t mask, int8_t *base, ptrdiff_t bstride,
vint8mf4_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8mf2_m(vbool16_t mask, int8_t *base, ptrdiff_t bstride,
vint8mf2_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m1_m(vbool8_t mask, int8_t *base, ptrdiff_t bstride,
vint8m1_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m2_m(vbool4_t mask, int8_t *base, ptrdiff_t bstride,
vint8m2_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m4_m(vbool2_t mask, int8_t *base, ptrdiff_t bstride,
vint8m4_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m8_m(vbool1_t mask, int8_t *base, ptrdiff_t bstride,
vint8m8_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16mf4_m(vbool64_t mask, int16_t *base, ptrdiff_t bstride,
vint16mf4_t value, size_t vl) {
return vsse16(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16mf2_m(vbool32_t mask, int16_t *base, ptrdiff_t bstride,
vint16mf2_t value, size_t vl) {
return vsse16(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m1_m(vbool16_t mask, int16_t *base, ptrdiff_t bstride,
vint16m1_t value, size_t vl) {
return vsse16(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m2_m(vbool8_t mask, int16_t *base, ptrdiff_t bstride,
vint16m2_t value, size_t vl) {
return vsse16(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m4_m(vbool4_t mask, int16_t *base, ptrdiff_t bstride,
vint16m4_t value, size_t vl) {
return vsse16(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m8_m(vbool2_t mask, int16_t *base, ptrdiff_t bstride,
vint16m8_t value, size_t vl) {
return vsse16(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32mf2_m(vbool64_t mask, int32_t *base, ptrdiff_t bstride,
vint32mf2_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m1_m(vbool32_t mask, int32_t *base, ptrdiff_t bstride,
vint32m1_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m2_m(vbool16_t mask, int32_t *base, ptrdiff_t bstride,
vint32m2_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m4_m(vbool8_t mask, int32_t *base, ptrdiff_t bstride,
vint32m4_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m8_m(vbool4_t mask, int32_t *base, ptrdiff_t bstride,
vint32m8_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m1_m(vbool64_t mask, int64_t *base, ptrdiff_t bstride,
vint64m1_t value, size_t vl) {
return vsse64(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m2_m(vbool32_t mask, int64_t *base, ptrdiff_t bstride,
vint64m2_t value, size_t vl) {
return vsse64(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m4_m(vbool16_t mask, int64_t *base, ptrdiff_t bstride,
vint64m4_t value, size_t vl) {
return vsse64(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m8_m(vbool8_t mask, int64_t *base, ptrdiff_t bstride,
vint64m8_t value, size_t vl) {
return vsse64(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8mf8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8mf8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8mf8_m(vbool64_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8mf8_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8mf4_m(vbool32_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8mf4_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8mf2_m(vbool16_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8mf2_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m1_m(vbool8_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8m1_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m2_m(vbool4_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8m2_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m4_m(vbool2_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8m4_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m8_m(vbool1_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8m8_t value, size_t vl) {
return vsse8(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16mf4_m(vbool64_t mask, uint16_t *base, ptrdiff_t bstride,
vuint16mf4_t value, size_t vl) {
return vsse16(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16mf2_m(vbool32_t mask, uint16_t *base, ptrdiff_t bstride,
vuint16mf2_t value, size_t vl) {
return vsse16(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m1_m(vbool16_t mask, uint16_t *base, ptrdiff_t bstride,
vuint16m1_t value, size_t vl) {
return vsse16(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m2_m(vbool8_t mask, uint16_t *base, ptrdiff_t bstride,
vuint16m2_t value, size_t vl) {
return vsse16(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m4_m(vbool4_t mask, uint16_t *base, ptrdiff_t bstride,
vuint16m4_t value, size_t vl) {
return vsse16(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m8_m(vbool2_t mask, uint16_t *base, ptrdiff_t bstride,
vuint16m8_t value, size_t vl) {
return vsse16(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32mf2_m(vbool64_t mask, uint32_t *base, ptrdiff_t bstride,
vuint32mf2_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m1_m(vbool32_t mask, uint32_t *base, ptrdiff_t bstride,
vuint32m1_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m2_m(vbool16_t mask, uint32_t *base, ptrdiff_t bstride,
vuint32m2_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m4_m(vbool8_t mask, uint32_t *base, ptrdiff_t bstride,
vuint32m4_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m8_m(vbool4_t mask, uint32_t *base, ptrdiff_t bstride,
vuint32m8_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m1_m(vbool64_t mask, uint64_t *base, ptrdiff_t bstride,
vuint64m1_t value, size_t vl) {
return vsse64(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m2_m(vbool32_t mask, uint64_t *base, ptrdiff_t bstride,
vuint64m2_t value, size_t vl) {
return vsse64(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m4_m(vbool16_t mask, uint64_t *base, ptrdiff_t bstride,
vuint64m4_t value, size_t vl) {
return vsse64(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m8_m(vbool8_t mask, uint64_t *base, ptrdiff_t bstride,
vuint64m8_t value, size_t vl) {
return vsse64(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1f32.i32(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1f32.i64(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32mf2_m(vbool64_t mask, float *base, ptrdiff_t bstride,
vfloat32mf2_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2f32.i32(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2f32.i64(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m1_m(vbool32_t mask, float *base, ptrdiff_t bstride,
vfloat32m1_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4f32.i32(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4f32.i64(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m2_m(vbool16_t mask, float *base, ptrdiff_t bstride,
vfloat32m2_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8f32.i32(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8f32.i64(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m4_m(vbool8_t mask, float *base, ptrdiff_t bstride,
vfloat32m4_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16f32.i32(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16f32.i64(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m8_m(vbool4_t mask, float *base, ptrdiff_t bstride,
vfloat32m8_t value, size_t vl) {
return vsse32(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1f64.i32(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1f64.i64(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m1_m(vbool64_t mask, double *base, ptrdiff_t bstride,
vfloat64m1_t value, size_t vl) {
return vsse64(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2f64.i32(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2f64.i64(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m2_m(vbool32_t mask, double *base, ptrdiff_t bstride,
vfloat64m2_t value, size_t vl) {
return vsse64(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4f64.i32(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4f64.i64(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m4_m(vbool16_t mask, double *base, ptrdiff_t bstride,
vfloat64m4_t value, size_t vl) {
return vsse64(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8f64.i32(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8f64.i64(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR8]]
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m8_m(vbool8_t mask, double *base, ptrdiff_t bstride,
vfloat64m8_t value, size_t vl) {
return vsse64(mask, base, bstride, value, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c

  • This file was added.
This file has a very large number of changes (6,523 lines). Show File Contents

clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c

Show First 20 Lines • Show All 1,699 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vle64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t vl) { vfloat64m8_t test_vle64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t vl) {
return vle64_v_f64m8_m(mask, maskedoff, base, vl); return vle64_v_f64m8_m(mask, maskedoff, base, vl);
} }
// CHECK-RV32-LABEL: @test_vle1_v_b1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vle1.nxv64i1.i32(<vscale x 64 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 64 x i1> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vle1_v_b1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vle1.nxv64i1.i64(<vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP1]]
//
vbool1_t test_vle1_v_b1(const uint8_t *base, size_t vl) {
return vle1_v_b1(base, vl);
}
// CHECK-RV32-LABEL: @test_vle1_v_b2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vle1.nxv32i1.i32(<vscale x 32 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 32 x i1> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vle1_v_b2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vle1.nxv32i1.i64(<vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP1]]
//
vbool2_t test_vle1_v_b2(const uint8_t *base, size_t vl) {
return vle1_v_b2(base, vl);
}
// CHECK-RV32-LABEL: @test_vle1_v_b4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vle1.nxv16i1.i32(<vscale x 16 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vle1_v_b4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vle1.nxv16i1.i64(<vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP1]]
//
vbool4_t test_vle1_v_b4(const uint8_t *base, size_t vl) {
return vle1_v_b4(base, vl);
}
// CHECK-RV32-LABEL: @test_vle1_v_b8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vle1.nxv8i1.i32(<vscale x 8 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i1> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vle1_v_b8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vle1.nxv8i1.i64(<vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP1]]
//
vbool8_t test_vle1_v_b8(const uint8_t *base, size_t vl) {
return vle1_v_b8(base, vl);
}
// CHECK-RV32-LABEL: @test_vle1_v_b16(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vle1.nxv4i1.i32(<vscale x 4 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i1> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vle1_v_b16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vle1.nxv4i1.i64(<vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP1]]
//
vbool16_t test_vle1_v_b16(const uint8_t *base, size_t vl) {
return vle1_v_b16(base, vl);
}
// CHECK-RV32-LABEL: @test_vle1_v_b32(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vle1.nxv2i1.i32(<vscale x 2 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i1> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vle1_v_b32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vle1.nxv2i1.i64(<vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP1]]
//
vbool32_t test_vle1_v_b32(const uint8_t *base, size_t vl) {
return vle1_v_b32(base, vl);
}
// CHECK-RV32-LABEL: @test_vle1_v_b64(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vle1.nxv1i1.i32(<vscale x 1 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i1> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vle1_v_b64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vle1.nxv1i1.i64(<vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP1]]
//
vbool64_t test_vle1_v_b64(const uint8_t *base, size_t vl) {
return vle1_v_b64(base, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vlse8_v_i8mf8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.i32(<vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
//
vint8mf8_t test_vlse8_v_i8mf8(const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_i8mf8(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8mf4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.i32(<vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
//
vint8mf4_t test_vlse8_v_i8mf4(const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_i8mf4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.i32(<vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
//
vint8mf2_t test_vlse8_v_i8mf2(const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_i8mf2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.i32(<vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
//
vint8m1_t test_vlse8_v_i8m1(const int8_t *base, ptrdiff_t bstride, size_t vl) {
return vlse8_v_i8m1(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.i32(<vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
//
vint8m2_t test_vlse8_v_i8m2(const int8_t *base, ptrdiff_t bstride, size_t vl) {
return vlse8_v_i8m2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.i32(<vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
//
vint8m4_t test_vlse8_v_i8m4(const int8_t *base, ptrdiff_t bstride, size_t vl) {
return vlse8_v_i8m4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.i32(<vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
//
vint8m8_t test_vlse8_v_i8m8(const int8_t *base, ptrdiff_t bstride, size_t vl) {
return vlse8_v_i8m8(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16mf4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.i32(<vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
//
vint16mf4_t test_vlse16_v_i16mf4(const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_i16mf4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.i32(<vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
//
vint16mf2_t test_vlse16_v_i16mf2(const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_i16mf2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.i32(<vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
//
vint16m1_t test_vlse16_v_i16m1(const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_i16m1(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.i32(<vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
vint16m2_t test_vlse16_v_i16m2(const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_i16m2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.i32(<vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
//
vint16m4_t test_vlse16_v_i16m4(const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_i16m4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16.i32(<vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
//
vint16m8_t test_vlse16_v_i16m8(const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_i16m8(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i32(<vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
//
vint32mf2_t test_vlse32_v_i32mf2(const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_i32mf2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.i32(<vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
//
vint32m1_t test_vlse32_v_i32m1(const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_i32m1(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.i32(<vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
vint32m2_t test_vlse32_v_i32m2(const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_i32m2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.i32(<vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
//
vint32m4_t test_vlse32_v_i32m4(const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_i32m4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.i32(<vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
//
vint32m8_t test_vlse32_v_i32m8(const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_i32m8(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_i64m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.i32(<vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_i64m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
//
vint64m1_t test_vlse64_v_i64m1(const int64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_i64m1(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_i64m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.i32(<vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_i64m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
vint64m2_t test_vlse64_v_i64m2(const int64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_i64m2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_i64m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.i32(<vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_i64m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
//
vint64m4_t test_vlse64_v_i64m4(const int64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_i64m4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_i64m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.i32(<vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_i64m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
//
vint64m8_t test_vlse64_v_i64m8(const int64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_i64m8(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8mf8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.i32(<vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8mf8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
//
vuint8mf8_t test_vlse8_v_u8mf8(const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8mf8(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8mf4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.i32(<vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
//
vuint8mf4_t test_vlse8_v_u8mf4(const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8mf4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.i32(<vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
//
vuint8mf2_t test_vlse8_v_u8mf2(const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8mf2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.i32(<vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
//
vuint8m1_t test_vlse8_v_u8m1(const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8m1(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.i32(<vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
//
vuint8m2_t test_vlse8_v_u8m2(const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8m2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.i32(<vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
//
vuint8m4_t test_vlse8_v_u8m4(const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8m4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.i32(<vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
//
vuint8m8_t test_vlse8_v_u8m8(const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8m8(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16mf4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.i32(<vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
//
vuint16mf4_t test_vlse16_v_u16mf4(const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_u16mf4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.i32(<vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
//
vuint16mf2_t test_vlse16_v_u16mf2(const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_u16mf2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.i32(<vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
//
vuint16m1_t test_vlse16_v_u16m1(const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_u16m1(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.i32(<vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
vuint16m2_t test_vlse16_v_u16m2(const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_u16m2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.i32(<vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
//
vuint16m4_t test_vlse16_v_u16m4(const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_u16m4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16.i32(<vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
//
vuint16m8_t test_vlse16_v_u16m8(const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_u16m8(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i32(<vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
//
vuint32mf2_t test_vlse32_v_u32mf2(const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_u32mf2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.i32(<vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
//
vuint32m1_t test_vlse32_v_u32m1(const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_u32m1(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.i32(<vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
vuint32m2_t test_vlse32_v_u32m2(const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_u32m2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.i32(<vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
//
vuint32m4_t test_vlse32_v_u32m4(const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_u32m4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.i32(<vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
//
vuint32m8_t test_vlse32_v_u32m8(const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_u32m8(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_u64m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.i32(<vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_u64m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
//
vuint64m1_t test_vlse64_v_u64m1(const uint64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_u64m1(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_u64m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.i32(<vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_u64m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
vuint64m2_t test_vlse64_v_u64m2(const uint64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_u64m2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_u64m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.i32(<vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_u64m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
//
vuint64m4_t test_vlse64_v_u64m4(const uint64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_u64m4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_u64m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.i32(<vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_u64m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
//
vuint64m8_t test_vlse64_v_u64m8(const uint64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_u64m8(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.i32(<vscale x 1 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.i64(<vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
//
vfloat32mf2_t test_vlse32_v_f32mf2(const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_f32mf2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.i32(<vscale x 2 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.i64(<vscale x 2 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
//
vfloat32m1_t test_vlse32_v_f32m1(const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_f32m1(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.i32(<vscale x 4 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.i64(<vscale x 4 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
//
vfloat32m2_t test_vlse32_v_f32m2(const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_f32m2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.i32(<vscale x 8 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.i64(<vscale x 8 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
//
vfloat32m4_t test_vlse32_v_f32m4(const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_f32m4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.i32(<vscale x 16 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.i64(<vscale x 16 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
//
vfloat32m8_t test_vlse32_v_f32m8(const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_f32m8(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_f64m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.i32(<vscale x 1 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_f64m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.i64(<vscale x 1 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
//
vfloat64m1_t test_vlse64_v_f64m1(const double *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_f64m1(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_f64m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.i32(<vscale x 2 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_f64m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.i64(<vscale x 2 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
//
vfloat64m2_t test_vlse64_v_f64m2(const double *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_f64m2(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_f64m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.i32(<vscale x 4 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_f64m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.i64(<vscale x 4 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
//
vfloat64m4_t test_vlse64_v_f64m4(const double *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_f64m4(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_f64m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.i32(<vscale x 8 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_f64m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.i64(<vscale x 8 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
//
vfloat64m8_t test_vlse64_v_f64m8(const double *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_f64m8(base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8mf8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
//
vint8mf8_t test_vlse8_v_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_i8mf8_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
//
vint8mf4_t test_vlse8_v_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_i8mf4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
//
vint8mf2_t test_vlse8_v_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_i8mf2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
//
vint8m1_t test_vlse8_v_i8m1_m(vbool8_t mask, vint8m1_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_i8m1_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
//
vint8m2_t test_vlse8_v_i8m2_m(vbool4_t mask, vint8m2_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_i8m2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
//
vint8m4_t test_vlse8_v_i8m4_m(vbool2_t mask, vint8m4_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_i8m4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_i8m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_i8m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
//
vint8m8_t test_vlse8_v_i8m8_m(vbool1_t mask, vint8m8_t maskedoff,
const int8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_i8m8_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
//
vint16mf4_t test_vlse16_v_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff,
const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_i16mf4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
//
vint16mf2_t test_vlse16_v_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff,
const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_i16mf2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
//
vint16m1_t test_vlse16_v_i16m1_m(vbool16_t mask, vint16m1_t maskedoff,
const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_i16m1_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
vint16m2_t test_vlse16_v_i16m2_m(vbool8_t mask, vint16m2_t maskedoff,
const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_i16m2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
//
vint16m4_t test_vlse16_v_i16m4_m(vbool4_t mask, vint16m4_t maskedoff,
const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_i16m4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_i16m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_i16m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
//
vint16m8_t test_vlse16_v_i16m8_m(vbool2_t mask, vint16m8_t maskedoff,
const int16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_i16m8_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
//
vint32mf2_t test_vlse32_v_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff,
const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_i32mf2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
//
vint32m1_t test_vlse32_v_i32m1_m(vbool32_t mask, vint32m1_t maskedoff,
const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_i32m1_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
vint32m2_t test_vlse32_v_i32m2_m(vbool16_t mask, vint32m2_t maskedoff,
const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_i32m2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
//
vint32m4_t test_vlse32_v_i32m4_m(vbool8_t mask, vint32m4_t maskedoff,
const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_i32m4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_i32m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_i32m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
//
vint32m8_t test_vlse32_v_i32m8_m(vbool4_t mask, vint32m8_t maskedoff,
const int32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_i32m8_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_i64m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_i64m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
//
vint64m1_t test_vlse64_v_i64m1_m(vbool64_t mask, vint64m1_t maskedoff,
const int64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_i64m1_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_i64m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_i64m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
vint64m2_t test_vlse64_v_i64m2_m(vbool32_t mask, vint64m2_t maskedoff,
const int64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_i64m2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_i64m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_i64m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
//
vint64m4_t test_vlse64_v_i64m4_m(vbool16_t mask, vint64m4_t maskedoff,
const int64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_i64m4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_i64m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_i64m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
//
vint64m8_t test_vlse64_v_i64m8_m(vbool8_t mask, vint64m8_t maskedoff,
const int64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_i64m8_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8mf8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8mf8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
//
vuint8mf8_t test_vlse8_v_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8mf8_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
//
vuint8mf4_t test_vlse8_v_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8mf4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
//
vuint8mf2_t test_vlse8_v_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8mf2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
//
vuint8m1_t test_vlse8_v_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8m1_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
//
vuint8m2_t test_vlse8_v_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8m2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
//
vuint8m4_t test_vlse8_v_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8m4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse8_v_u8m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse8_v_u8m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
//
vuint8m8_t test_vlse8_v_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff,
const uint8_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse8_v_u8m8_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
//
vuint16mf4_t test_vlse16_v_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff,
const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_u16mf4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
//
vuint16mf2_t test_vlse16_v_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff,
const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_u16mf2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
//
vuint16m1_t test_vlse16_v_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff,
const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_u16m1_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
vuint16m2_t test_vlse16_v_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff,
const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_u16m2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
//
vuint16m4_t test_vlse16_v_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff,
const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_u16m4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse16_v_u16m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse16_v_u16m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
//
vuint16m8_t test_vlse16_v_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff,
const uint16_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse16_v_u16m8_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
//
vuint32mf2_t test_vlse32_v_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff,
const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_u32mf2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
//
vuint32m1_t test_vlse32_v_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_u32m1_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
vuint32m2_t test_vlse32_v_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_u32m2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
//
vuint32m4_t test_vlse32_v_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_u32m4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_u32m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_u32m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
//
vuint32m8_t test_vlse32_v_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
const uint32_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_u32m8_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_u64m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_u64m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
//
vuint64m1_t test_vlse64_v_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
const uint64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_u64m1_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_u64m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_u64m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
vuint64m2_t test_vlse64_v_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
const uint64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_u64m2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_u64m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_u64m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
//
vuint64m4_t test_vlse64_v_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
const uint64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_u64m4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_u64m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_u64m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
//
vuint64m8_t test_vlse64_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
const uint64_t *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_u64m8_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.i32(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
//
vfloat32mf2_t test_vlse32_v_f32mf2_m(vbool64_t mask, vfloat32mf2_t maskedoff,
const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_f32mf2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.i32(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
//
vfloat32m1_t test_vlse32_v_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff,
const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_f32m1_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.i32(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
//
vfloat32m2_t test_vlse32_v_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff,
const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_f32m2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.i32(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
//
vfloat32m4_t test_vlse32_v_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff,
const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_f32m4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse32_v_f32m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.i32(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse32_v_f32m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
//
vfloat32m8_t test_vlse32_v_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff,
const float *base, ptrdiff_t bstride,
size_t vl) {
return vlse32_v_f32m8_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_f64m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.i32(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_f64m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
//
vfloat64m1_t test_vlse64_v_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff,
const double *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_f64m1_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_f64m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.i32(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_f64m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
//
vfloat64m2_t test_vlse64_v_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff,
const double *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_f64m2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_f64m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.i32(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_f64m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
//
vfloat64m4_t test_vlse64_v_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff,
const double *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_f64m4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV32-LABEL: @test_vlse64_v_f64m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV32-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.i32(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP1]]
//
// CHECK-RV64-LABEL: @test_vlse64_v_f64m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
//
vfloat64m8_t test_vlse64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
const double *base, ptrdiff_t bstride,
size_t vl) {
return vlse64_v_f64m8_m(mask, maskedoff, base, bstride, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c

Show First 20 Lines • Show All 1,699 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8f64.i64(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8f64.i64(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void // CHECK-RV64-NEXT: ret void
// //
void test_vse64_v_f64m8_m(vbool8_t mask, double *base, vfloat64m8_t value, size_t vl) { void test_vse64_v_f64m8_m(vbool8_t mask, double *base, vfloat64m8_t value, size_t vl) {
return vse64_v_f64m8_m(mask, base, value, vl); return vse64_v_f64m8_m(mask, base, value, vl);
} }
// CHECK-RV32-LABEL: @test_vse1_v_b1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv64i1.i32(<vscale x 64 x i1> [[VALUE:%.*]], <vscale x 64 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv64i1.i64(<vscale x 64 x i1> [[VALUE:%.*]], <vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b1(uint8_t *base, vbool1_t value, size_t vl) {
return vse1_v_b1(base, value, vl);
}
// CHECK-RV32-LABEL: @test_vse1_v_b2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv32i1.i32(<vscale x 32 x i1> [[VALUE:%.*]], <vscale x 32 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv32i1.i64(<vscale x 32 x i1> [[VALUE:%.*]], <vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b2(uint8_t *base, vbool2_t value, size_t vl) {
return vse1_v_b2(base, value, vl);
}
// CHECK-RV32-LABEL: @test_vse1_v_b4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv16i1.i32(<vscale x 16 x i1> [[VALUE:%.*]], <vscale x 16 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv16i1.i64(<vscale x 16 x i1> [[VALUE:%.*]], <vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b4(uint8_t *base, vbool4_t value, size_t vl) {
return vse1_v_b4(base, value, vl);
}
// CHECK-RV32-LABEL: @test_vse1_v_b8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv8i1.i32(<vscale x 8 x i1> [[VALUE:%.*]], <vscale x 8 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv8i1.i64(<vscale x 8 x i1> [[VALUE:%.*]], <vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b8(uint8_t *base, vbool8_t value, size_t vl) {
return vse1_v_b8(base, value, vl);
}
// CHECK-RV32-LABEL: @test_vse1_v_b16(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv4i1.i32(<vscale x 4 x i1> [[VALUE:%.*]], <vscale x 4 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv4i1.i64(<vscale x 4 x i1> [[VALUE:%.*]], <vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b16(uint8_t *base, vbool16_t value, size_t vl) {
return vse1_v_b16(base, value, vl);
}
// CHECK-RV32-LABEL: @test_vse1_v_b32(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv2i1.i32(<vscale x 2 x i1> [[VALUE:%.*]], <vscale x 2 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv2i1.i64(<vscale x 2 x i1> [[VALUE:%.*]], <vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b32(uint8_t *base, vbool32_t value, size_t vl) {
return vse1_v_b32(base, value, vl);
}
// CHECK-RV32-LABEL: @test_vse1_v_b64(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vse1.nxv1i1.i32(<vscale x 1 x i1> [[VALUE:%.*]], <vscale x 1 x i1>* [[TMP0]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vse1_v_b64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv1i1.i64(<vscale x 1 x i1> [[VALUE:%.*]], <vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vse1_v_b64(uint8_t *base, vbool64_t value, size_t vl) {
return vse1_v_b64(base, value, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c

  • This file was added.
This file has a very large number of changes (6,523 lines). Show File Contents

clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8mf8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8mf8(int8_t *base, ptrdiff_t bstride, vint8mf8_t value,
size_t vl) {
return vsse8_v_i8mf8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8mf4(int8_t *base, ptrdiff_t bstride, vint8mf4_t value,
size_t vl) {
return vsse8_v_i8mf4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8mf2(int8_t *base, ptrdiff_t bstride, vint8mf2_t value,
size_t vl) {
return vsse8_v_i8mf2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m1(int8_t *base, ptrdiff_t bstride, vint8m1_t value,
size_t vl) {
return vsse8_v_i8m1(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m2(int8_t *base, ptrdiff_t bstride, vint8m2_t value,
size_t vl) {
return vsse8_v_i8m2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m4(int8_t *base, ptrdiff_t bstride, vint8m4_t value,
size_t vl) {
return vsse8_v_i8m4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m8(int8_t *base, ptrdiff_t bstride, vint8m8_t value,
size_t vl) {
return vsse8_v_i8m8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16mf4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16mf4(int16_t *base, ptrdiff_t bstride, vint16mf4_t value,
size_t vl) {
return vsse16_v_i16mf4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16mf2(int16_t *base, ptrdiff_t bstride, vint16mf2_t value,
size_t vl) {
return vsse16_v_i16mf2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m1(int16_t *base, ptrdiff_t bstride, vint16m1_t value,
size_t vl) {
return vsse16_v_i16m1(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m2(int16_t *base, ptrdiff_t bstride, vint16m2_t value,
size_t vl) {
return vsse16_v_i16m2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m4(int16_t *base, ptrdiff_t bstride, vint16m4_t value,
size_t vl) {
return vsse16_v_i16m4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m8(int16_t *base, ptrdiff_t bstride, vint16m8_t value,
size_t vl) {
return vsse16_v_i16m8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32mf2(int32_t *base, ptrdiff_t bstride, vint32mf2_t value,
size_t vl) {
return vsse32_v_i32mf2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m1(int32_t *base, ptrdiff_t bstride, vint32m1_t value,
size_t vl) {
return vsse32_v_i32m1(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m2(int32_t *base, ptrdiff_t bstride, vint32m2_t value,
size_t vl) {
return vsse32_v_i32m2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m4(int32_t *base, ptrdiff_t bstride, vint32m4_t value,
size_t vl) {
return vsse32_v_i32m4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m8(int32_t *base, ptrdiff_t bstride, vint32m8_t value,
size_t vl) {
return vsse32_v_i32m8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m1(int64_t *base, ptrdiff_t bstride, vint64m1_t value,
size_t vl) {
return vsse64_v_i64m1(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m2(int64_t *base, ptrdiff_t bstride, vint64m2_t value,
size_t vl) {
return vsse64_v_i64m2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m4(int64_t *base, ptrdiff_t bstride, vint64m4_t value,
size_t vl) {
return vsse64_v_i64m4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m8(int64_t *base, ptrdiff_t bstride, vint64m8_t value,
size_t vl) {
return vsse64_v_i64m8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8mf8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8mf8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8mf8(uint8_t *base, ptrdiff_t bstride, vuint8mf8_t value,
size_t vl) {
return vsse8_v_u8mf8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8mf4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8mf4(uint8_t *base, ptrdiff_t bstride, vuint8mf4_t value,
size_t vl) {
return vsse8_v_u8mf4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8mf2(uint8_t *base, ptrdiff_t bstride, vuint8mf2_t value,
size_t vl) {
return vsse8_v_u8mf2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m1(uint8_t *base, ptrdiff_t bstride, vuint8m1_t value,
size_t vl) {
return vsse8_v_u8m1(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m2(uint8_t *base, ptrdiff_t bstride, vuint8m2_t value,
size_t vl) {
return vsse8_v_u8m2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m4(uint8_t *base, ptrdiff_t bstride, vuint8m4_t value,
size_t vl) {
return vsse8_v_u8m4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m8(uint8_t *base, ptrdiff_t bstride, vuint8m8_t value,
size_t vl) {
return vsse8_v_u8m8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16mf4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16mf4(uint16_t *base, ptrdiff_t bstride, vuint16mf4_t value,
size_t vl) {
return vsse16_v_u16mf4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16mf2(uint16_t *base, ptrdiff_t bstride, vuint16mf2_t value,
size_t vl) {
return vsse16_v_u16mf2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m1(uint16_t *base, ptrdiff_t bstride, vuint16m1_t value,
size_t vl) {
return vsse16_v_u16m1(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m2(uint16_t *base, ptrdiff_t bstride, vuint16m2_t value,
size_t vl) {
return vsse16_v_u16m2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m4(uint16_t *base, ptrdiff_t bstride, vuint16m4_t value,
size_t vl) {
return vsse16_v_u16m4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m8(uint16_t *base, ptrdiff_t bstride, vuint16m8_t value,
size_t vl) {
return vsse16_v_u16m8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32mf2(uint32_t *base, ptrdiff_t bstride, vuint32mf2_t value,
size_t vl) {
return vsse32_v_u32mf2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m1(uint32_t *base, ptrdiff_t bstride, vuint32m1_t value,
size_t vl) {
return vsse32_v_u32m1(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m2(uint32_t *base, ptrdiff_t bstride, vuint32m2_t value,
size_t vl) {
return vsse32_v_u32m2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m4(uint32_t *base, ptrdiff_t bstride, vuint32m4_t value,
size_t vl) {
return vsse32_v_u32m4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m8(uint32_t *base, ptrdiff_t bstride, vuint32m8_t value,
size_t vl) {
return vsse32_v_u32m8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m1(uint64_t *base, ptrdiff_t bstride, vuint64m1_t value,
size_t vl) {
return vsse64_v_u64m1(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m2(uint64_t *base, ptrdiff_t bstride, vuint64m2_t value,
size_t vl) {
return vsse64_v_u64m2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m4(uint64_t *base, ptrdiff_t bstride, vuint64m4_t value,
size_t vl) {
return vsse64_v_u64m4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m8(uint64_t *base, ptrdiff_t bstride, vuint64m8_t value,
size_t vl) {
return vsse64_v_u64m8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32mf2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1f32.i32(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1f32.i64(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32mf2(float *base, ptrdiff_t bstride, vfloat32mf2_t value,
size_t vl) {
return vsse32_v_f32mf2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2f32.i32(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2f32.i64(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m1(float *base, ptrdiff_t bstride, vfloat32m1_t value,
size_t vl) {
return vsse32_v_f32m1(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4f32.i32(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4f32.i64(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m2(float *base, ptrdiff_t bstride, vfloat32m2_t value,
size_t vl) {
return vsse32_v_f32m2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8f32.i32(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8f32.i64(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m4(float *base, ptrdiff_t bstride, vfloat32m4_t value,
size_t vl) {
return vsse32_v_f32m4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv16f32.i32(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16f32.i64(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m8(float *base, ptrdiff_t bstride, vfloat32m8_t value,
size_t vl) {
return vsse32_v_f32m8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv1f64.i32(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1f64.i64(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m1(double *base, ptrdiff_t bstride, vfloat64m1_t value,
size_t vl) {
return vsse64_v_f64m1(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv2f64.i32(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2f64.i64(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m2(double *base, ptrdiff_t bstride, vfloat64m2_t value,
size_t vl) {
return vsse64_v_f64m2(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv4f64.i32(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4f64.i64(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m4(double *base, ptrdiff_t bstride, vfloat64m4_t value,
size_t vl) {
return vsse64_v_f64m4(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.nxv8f64.i32(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8f64.i64(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m8(double *base, ptrdiff_t bstride, vfloat64m8_t value,
size_t vl) {
return vsse64_v_f64m8(base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8mf8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8mf8_m(vbool64_t mask, int8_t *base, ptrdiff_t bstride,
vint8mf8_t value, size_t vl) {
return vsse8_v_i8mf8_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8mf4_m(vbool32_t mask, int8_t *base, ptrdiff_t bstride,
vint8mf4_t value, size_t vl) {
return vsse8_v_i8mf4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8mf2_m(vbool16_t mask, int8_t *base, ptrdiff_t bstride,
vint8mf2_t value, size_t vl) {
return vsse8_v_i8mf2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m1_m(vbool8_t mask, int8_t *base, ptrdiff_t bstride,
vint8m1_t value, size_t vl) {
return vsse8_v_i8m1_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m2_m(vbool4_t mask, int8_t *base, ptrdiff_t bstride,
vint8m2_t value, size_t vl) {
return vsse8_v_i8m2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m4_m(vbool2_t mask, int8_t *base, ptrdiff_t bstride,
vint8m4_t value, size_t vl) {
return vsse8_v_i8m4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_i8m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_i8m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_i8m8_m(vbool1_t mask, int8_t *base, ptrdiff_t bstride,
vint8m8_t value, size_t vl) {
return vsse8_v_i8m8_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16mf4_m(vbool64_t mask, int16_t *base, ptrdiff_t bstride,
vint16mf4_t value, size_t vl) {
return vsse16_v_i16mf4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16mf2_m(vbool32_t mask, int16_t *base, ptrdiff_t bstride,
vint16mf2_t value, size_t vl) {
return vsse16_v_i16mf2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m1_m(vbool16_t mask, int16_t *base, ptrdiff_t bstride,
vint16m1_t value, size_t vl) {
return vsse16_v_i16m1_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m2_m(vbool8_t mask, int16_t *base, ptrdiff_t bstride,
vint16m2_t value, size_t vl) {
return vsse16_v_i16m2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m4_m(vbool4_t mask, int16_t *base, ptrdiff_t bstride,
vint16m4_t value, size_t vl) {
return vsse16_v_i16m4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_i16m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_i16m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_i16m8_m(vbool2_t mask, int16_t *base, ptrdiff_t bstride,
vint16m8_t value, size_t vl) {
return vsse16_v_i16m8_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32mf2_m(vbool64_t mask, int32_t *base, ptrdiff_t bstride,
vint32mf2_t value, size_t vl) {
return vsse32_v_i32mf2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m1_m(vbool32_t mask, int32_t *base, ptrdiff_t bstride,
vint32m1_t value, size_t vl) {
return vsse32_v_i32m1_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m2_m(vbool16_t mask, int32_t *base, ptrdiff_t bstride,
vint32m2_t value, size_t vl) {
return vsse32_v_i32m2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m4_m(vbool8_t mask, int32_t *base, ptrdiff_t bstride,
vint32m4_t value, size_t vl) {
return vsse32_v_i32m4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_i32m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_i32m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_i32m8_m(vbool4_t mask, int32_t *base, ptrdiff_t bstride,
vint32m8_t value, size_t vl) {
return vsse32_v_i32m8_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m1_m(vbool64_t mask, int64_t *base, ptrdiff_t bstride,
vint64m1_t value, size_t vl) {
return vsse64_v_i64m1_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m2_m(vbool32_t mask, int64_t *base, ptrdiff_t bstride,
vint64m2_t value, size_t vl) {
return vsse64_v_i64m2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m4_m(vbool16_t mask, int64_t *base, ptrdiff_t bstride,
vint64m4_t value, size_t vl) {
return vsse64_v_i64m4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_i64m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_i64m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_i64m8_m(vbool8_t mask, int64_t *base, ptrdiff_t bstride,
vint64m8_t value, size_t vl) {
return vsse64_v_i64m8_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8mf8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i8.i32(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8mf8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8mf8_m(vbool64_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8mf8_t value, size_t vl) {
return vsse8_v_u8mf8_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i8.i32(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i8.i64(<vscale x 2 x i8> [[VALUE:%.*]], <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8mf4_m(vbool32_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8mf4_t value, size_t vl) {
return vsse8_v_u8mf4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i8.i32(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i8.i64(<vscale x 4 x i8> [[VALUE:%.*]], <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8mf2_m(vbool16_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8mf2_t value, size_t vl) {
return vsse8_v_u8mf2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i8.i32(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i8.i64(<vscale x 8 x i8> [[VALUE:%.*]], <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m1_m(vbool8_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8m1_t value, size_t vl) {
return vsse8_v_u8m1_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16i8.i32(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16i8.i64(<vscale x 16 x i8> [[VALUE:%.*]], <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m2_m(vbool4_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8m2_t value, size_t vl) {
return vsse8_v_u8m2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv32i8.i32(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv32i8.i64(<vscale x 32 x i8> [[VALUE:%.*]], <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m4_m(vbool2_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8m4_t value, size_t vl) {
return vsse8_v_u8m4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse8_v_u8m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv64i8.i32(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse8_v_u8m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv64i8.i64(<vscale x 64 x i8> [[VALUE:%.*]], <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse8_v_u8m8_m(vbool1_t mask, uint8_t *base, ptrdiff_t bstride,
vuint8m8_t value, size_t vl) {
return vsse8_v_u8m8_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16mf4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i16.i32(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i16.i64(<vscale x 1 x i16> [[VALUE:%.*]], <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16mf4_m(vbool64_t mask, uint16_t *base, ptrdiff_t bstride,
vuint16mf4_t value, size_t vl) {
return vsse16_v_u16mf4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i16.i32(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i16.i64(<vscale x 2 x i16> [[VALUE:%.*]], <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16mf2_m(vbool32_t mask, uint16_t *base, ptrdiff_t bstride,
vuint16mf2_t value, size_t vl) {
return vsse16_v_u16mf2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i16.i32(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i16.i64(<vscale x 4 x i16> [[VALUE:%.*]], <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m1_m(vbool16_t mask, uint16_t *base, ptrdiff_t bstride,
vuint16m1_t value, size_t vl) {
return vsse16_v_u16m1_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i16.i32(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i16.i64(<vscale x 8 x i16> [[VALUE:%.*]], <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m2_m(vbool8_t mask, uint16_t *base, ptrdiff_t bstride,
vuint16m2_t value, size_t vl) {
return vsse16_v_u16m2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16i16.i32(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16i16.i64(<vscale x 16 x i16> [[VALUE:%.*]], <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m4_m(vbool4_t mask, uint16_t *base, ptrdiff_t bstride,
vuint16m4_t value, size_t vl) {
return vsse16_v_u16m4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse16_v_u16m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv32i16.i32(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse16_v_u16m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv32i16.i64(<vscale x 32 x i16> [[VALUE:%.*]], <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse16_v_u16m8_m(vbool2_t mask, uint16_t *base, ptrdiff_t bstride,
vuint16m8_t value, size_t vl) {
return vsse16_v_u16m8_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i32.i32(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i32.i64(<vscale x 1 x i32> [[VALUE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32mf2_m(vbool64_t mask, uint32_t *base, ptrdiff_t bstride,
vuint32mf2_t value, size_t vl) {
return vsse32_v_u32mf2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i32.i32(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i32.i64(<vscale x 2 x i32> [[VALUE:%.*]], <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m1_m(vbool32_t mask, uint32_t *base, ptrdiff_t bstride,
vuint32m1_t value, size_t vl) {
return vsse32_v_u32m1_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i32.i32(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i32.i64(<vscale x 4 x i32> [[VALUE:%.*]], <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m2_m(vbool16_t mask, uint32_t *base, ptrdiff_t bstride,
vuint32m2_t value, size_t vl) {
return vsse32_v_u32m2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i32.i32(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i32.i64(<vscale x 8 x i32> [[VALUE:%.*]], <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m4_m(vbool8_t mask, uint32_t *base, ptrdiff_t bstride,
vuint32m4_t value, size_t vl) {
return vsse32_v_u32m4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_u32m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16i32.i32(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_u32m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16i32.i64(<vscale x 16 x i32> [[VALUE:%.*]], <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_u32m8_m(vbool4_t mask, uint32_t *base, ptrdiff_t bstride,
vuint32m8_t value, size_t vl) {
return vsse32_v_u32m8_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1i64.i32(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1i64.i64(<vscale x 1 x i64> [[VALUE:%.*]], <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m1_m(vbool64_t mask, uint64_t *base, ptrdiff_t bstride,
vuint64m1_t value, size_t vl) {
return vsse64_v_u64m1_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2i64.i32(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2i64.i64(<vscale x 2 x i64> [[VALUE:%.*]], <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m2_m(vbool32_t mask, uint64_t *base, ptrdiff_t bstride,
vuint64m2_t value, size_t vl) {
return vsse64_v_u64m2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4i64.i32(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4i64.i64(<vscale x 4 x i64> [[VALUE:%.*]], <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m4_m(vbool16_t mask, uint64_t *base, ptrdiff_t bstride,
vuint64m4_t value, size_t vl) {
return vsse64_v_u64m4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_u64m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8i64.i32(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_u64m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8i64.i64(<vscale x 8 x i64> [[VALUE:%.*]], <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_u64m8_m(vbool8_t mask, uint64_t *base, ptrdiff_t bstride,
vuint64m8_t value, size_t vl) {
return vsse64_v_u64m8_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32mf2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1f32.i32(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32mf2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1f32.i64(<vscale x 1 x float> [[VALUE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32mf2_m(vbool64_t mask, float *base, ptrdiff_t bstride,
vfloat32mf2_t value, size_t vl) {
return vsse32_v_f32mf2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2f32.i32(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2f32.i64(<vscale x 2 x float> [[VALUE:%.*]], <vscale x 2 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m1_m(vbool32_t mask, float *base, ptrdiff_t bstride,
vfloat32m1_t value, size_t vl) {
return vsse32_v_f32m1_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4f32.i32(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4f32.i64(<vscale x 4 x float> [[VALUE:%.*]], <vscale x 4 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m2_m(vbool16_t mask, float *base, ptrdiff_t bstride,
vfloat32m2_t value, size_t vl) {
return vsse32_v_f32m2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8f32.i32(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8f32.i64(<vscale x 8 x float> [[VALUE:%.*]], <vscale x 8 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m4_m(vbool8_t mask, float *base, ptrdiff_t bstride,
vfloat32m4_t value, size_t vl) {
return vsse32_v_f32m4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse32_v_f32m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv16f32.i32(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse32_v_f32m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16f32.i64(<vscale x 16 x float> [[VALUE:%.*]], <vscale x 16 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse32_v_f32m8_m(vbool4_t mask, float *base, ptrdiff_t bstride,
vfloat32m8_t value, size_t vl) {
return vsse32_v_f32m8_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m1_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv1f64.i32(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1f64.i64(<vscale x 1 x double> [[VALUE:%.*]], <vscale x 1 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m1_m(vbool64_t mask, double *base, ptrdiff_t bstride,
vfloat64m1_t value, size_t vl) {
return vsse64_v_f64m1_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m2_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv2f64.i32(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m2_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2f64.i64(<vscale x 2 x double> [[VALUE:%.*]], <vscale x 2 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m2_m(vbool32_t mask, double *base, ptrdiff_t bstride,
vfloat64m2_t value, size_t vl) {
return vsse64_v_f64m2_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m4_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv4f64.i32(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4f64.i64(<vscale x 4 x double> [[VALUE:%.*]], <vscale x 4 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m4_m(vbool16_t mask, double *base, ptrdiff_t bstride,
vfloat64m4_t value, size_t vl) {
return vsse64_v_f64m4_m(mask, base, bstride, value, vl);
}
// CHECK-RV32-LABEL: @test_vsse64_v_f64m8_m(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV32-NEXT: call void @llvm.riscv.vsse.mask.nxv8f64.i32(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], i32 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret void
//
// CHECK-RV64-LABEL: @test_vsse64_v_f64m8_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8f64.i64(<vscale x 8 x double> [[VALUE:%.*]], <vscale x 8 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
void test_vsse64_v_f64m8_m(vbool8_t mask, double *base, ptrdiff_t bstride,
vfloat64m8_t value, size_t vl) {
return vsse64_v_f64m8_m(mask, base, bstride, value, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c

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