Index: lib/Target/X86/X86ISelDAGToDAG.cpp
===================================================================
--- lib/Target/X86/X86ISelDAGToDAG.cpp
+++ lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1512,9 +1512,8 @@
         IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
         IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
       LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
-      if (!selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
-        return false;
-      return true;
+      return selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp,
+                        Segment);
     }
   }
 
@@ -2145,10 +2144,7 @@
       InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
                                    MVT::Other, ChainOps);
   }
-  if (!ChainCheck)
-    return false;
-
-  return true;
+  return ChainCheck;
 }
 
 /// Get the appropriate X86 opcode for an in-memory increment or decrement.
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -2500,10 +2500,7 @@
 
   CallSite CS(CI);
   CallingConv::ID CalleeCC = CS.getCallingConv();
-  if (!mayTailCallThisCC(CalleeCC))
-    return false;
-
-  return true;
+  return mayTailCallThisCC(CalleeCC);
 }
 
 SDValue
@@ -3642,9 +3639,7 @@
     return false;
 
   if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
-    if (canGuaranteeTCO(CalleeCC) && CCMatch)
-      return true;
-    return false;
+    return canGuaranteeTCO(CalleeCC) && CCMatch;
   }
 
   // Look for obvious safe cases to perform tail call optimization that do not
@@ -4118,9 +4113,7 @@
   assert(Ty->isIntegerTy());
 
   unsigned BitSize = Ty->getPrimitiveSizeInBits();
-  if (BitSize == 0 || BitSize > 64)
-    return false;
-  return true;
+  return !(BitSize == 0 || BitSize > 64);
 }
 
 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
Index: lib/Target/X86/X86InstrInfo.cpp
===================================================================
--- lib/Target/X86/X86InstrInfo.cpp
+++ lib/Target/X86/X86InstrInfo.cpp
@@ -2485,11 +2485,8 @@
     isKill = Src.isKill();
     isUndef = Src.isUndef();
 
-    if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
-        !MF.getRegInfo().constrainRegClass(NewSrc, RC))
-      return false;
-
-    return true;
+    return !(TargetRegisterInfo::isVirtualRegister(NewSrc) &&
+             !MF.getRegInfo().constrainRegClass(NewSrc, RC));
   }
 
   // This is for an LEA64_32r and incoming registers are 32-bit. One way or