[AArch64] Use 64-bit movi for zeroing halfs/floats

[SjoerdMeijer]

Summary

This was using the .2d variant, but using the "movi d0" variant that zeros 64 bits is faster on some cores.

This is a prep step for D99586 to always using movi for zeroing floats.

[david-arm]

llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

1105

Should this be moved to the else case? It looks like we're adding the same immediate twice for the H and S cases.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

1105

Thanks for taking a look. This movi variant takes an optional shift immediate value, so indeed for the H and S we need to add 0 immediates. That probably deserves a comment, so will add that.

[dmgreen]

I think the exact suggestion was to use MOVID instead. I'm not sure how much it matters, but it may be a simpler instruction for some cores. This would then match what GCC emits.

[SjoerdMeijer]

In D99710#2663415, @dmgreen wrote:

I think the exact suggestion was to use MOVID instead. I'm not sure how much it matters, but it may be a simpler instruction for some cores. This would then match what GCC emits.

Well, that's not what GCC does at moment, not yet at least, but it is indeed another way of doing it. But let's go for the movi d0.

[SjoerdMeijer]

Now using "movi d0".

[dmgreen]

Thanks. This LGTM, so long as the Apple folks here are happy with changing the instruction issued.

llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll

33

We may want to do the same with neon movi's, as the instructions set all bits to 0 in either case.

[SjoerdMeijer]

Thanks, and I will wait a few days with committing.

llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

void AArch64AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI) {
 
   OutStreamer->AddComment("on-fault: " + HandlerLabel->getName());
   OutStreamer->emitInstruction(MI, getSubtargetInfo());
 }
 
 void AArch64AsmPrinter::EmitFMov0(const MachineInstr &MI) {
   Register DestReg = MI.getOperand(0).getReg();
   if (STI->hasZeroCycleZeroingFP() && !STI->hasZeroCycleZeroingFPWorkaround()) {
-    // Convert H/S/D register to corresponding Q register
+    // Convert H/S register to corresponding D register
     if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31)
-      DestReg = AArch64::Q0 + (DestReg - AArch64::H0);
+      DestReg = AArch64::D0 + (DestReg - AArch64::H0);
     else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31)
-      DestReg = AArch64::Q0 + (DestReg - AArch64::S0);
-    else {
+      DestReg = AArch64::D0 + (DestReg - AArch64::S0);
+    else
       assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31);
-      DestReg = AArch64::Q0 + (DestReg - AArch64::D0);
-    }
+
     MCInst MOVI;
-    MOVI.setOpcode(AArch64::MOVIv2d_ns);
+    MOVI.setOpcode(AArch64::MOVID);
     MOVI.addOperand(MCOperand::createReg(DestReg));
     MOVI.addOperand(MCOperand::createImm(0));
     EmitToStreamer(*OutStreamer, MOVI);
   } else {
     MCInst FMov;
     switch (MI.getOpcode()) {
     default: llvm_unreachable("Unexpected opcode");
     case AArch64::FMOVH0:
       FMov.setOpcode(AArch64::FMOVWHr);
       FMov.addOperand(MCOperand::createReg(DestReg));

llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll

 ; NONEFP: fmov s1, wzr
 ; NONEFP: fmov d2, xzr
 ; NONEFP: movi{{(.16b)?}} v3{{(.2d)?}}, #0
 ; NONE16: fmov h0, wzr
 ; NONE16: fmov s1, wzr
 ; NONE16: fmov d2, xzr
 ; NONE16: movi{{(.16b)?}} v3{{(.2d)?}}, #0
 ; ZEROFP-DAG: ldr h0,{{.*}}
-; ZEROFP-DAG: movi v{{[0-3]+}}.2d, #0
-; ZEROFP-DAG: movi v{{[0-3]+}}.2d, #0
-; ZEROFP-DAG: movi v{{[0-3]+}}.2d, #0
-; ZERO16: movi v{{[0-3]+}}.2d, #0
-; ZERO16: movi v{{[0-3]+}}.2d, #0
-; ZERO16: movi v{{[0-3]+}}.2d, #0
-; ZERO16: movi v{{[0-3]+}}.2d, #0
+; ZEROFP-DAG: movi d1, #0
+; ZEROFP-DAG: movi d2, #0
+; ZEROFP-DAG: movi v3.2d, #0
+; ZERO16: movi d0, #0
+; ZERO16: movi d1, #0
+; ZERO16: movi d2, #0
+; ZERO16: movi v3.2d, #0
   tail call void @bar(half 0.000000e+00, float 0.000000e+00, double 0.000000e+00, <2 x double> <double 0.000000e+00, double 0.000000e+00>) nounwind
   ret void
 }
 
 define void @t2() nounwind ssp {
 entry:
 ; ALL-LABEL: t2:
 ; NONEGP: mov w0, wzr
; ZEROGP: mov x1, #0
   tail call void @barl(i64 0, i64 0) nounwind
   ret void
 }
 
 define void @t4() nounwind ssp {
 ; ALL-LABEL: t4:
 ; NONEFP: fmov s{{[0-3]+}}, wzr
 ; NONEFP: fmov s{{[0-3]+}}, wzr
-; ZEROFP: movi v{{[0-3]+}}.2d, #0
-; ZEROFP: movi v{{[0-3]+}}.2d, #0
+; ZEROFP: movi d0, #0
+; ZEROFP: movi d1, #0
   tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind
   ret void
 }
 
 declare double @sin(double)
 
 ; We used to produce spills+reloads for a Q register with zero cycle zeroing
 ; enabled.

 ; ZEROGP: mov x0, #0
   ret i64 0
 }
 
 define float @tf32() {
 entry:
 ; ALL-LABEL: tf32:
 ; NONEFP: mov s0, wzr
-; ZEROFP: movi v0.2d, #0
+; ZEROFP: movi d0, #0
   ret float 0.0
 }
 
 define double @td64() {
 entry:
 ; ALL-LABEL: td64:
 ; NONEFP: mov d0, xzr
-; ZEROFP: movi v0.2d, #0
+; ZEROFP: movi d0, #0
   ret double 0.0
 }
 
 define <8 x i8> @tv8i8() {
 entry:
 ; ALL-LABEL: tv8i8:
 ; ALL: movi{{(.16b)?}} v0{{(.2d)?}}, #0
   ret <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>

llvm/test/CodeGen/AArch64/f16-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-NOZCZ
 ; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16,+zcz | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-ZCZ
 ; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
 
 define half @Const0() {
 ; CHECK-NOZCZ-LABEL: Const0:
 ; CHECK-NOZCZ:       // %bb.0: // %entry
 ; CHECK-NOZCZ-NEXT:    fmov h0, wzr
 ; CHECK-NOZCZ-NEXT:    ret
 ;
 ; CHECK-ZCZ-LABEL: Const0:
 ; CHECK-ZCZ:       // %bb.0: // %entry
-; CHECK-ZCZ-NEXT:    movi v0.2d, #0000000000000000
+; CHECK-ZCZ-NEXT:    movi d0, #0
 ; CHECK-ZCZ-NEXT:    ret
 ;
 ; CHECK-NOFP16-LABEL: Const0:
 ; CHECK-NOFP16:       // %bb.0: // %entry
 ; CHECK-NOFP16-NEXT:    adrp x8, .LCPI0_0
 ; CHECK-NOFP16-NEXT:    ldr h0, [x8, :lo12:.LCPI0_0]
 ; CHECK-NOFP16-NEXT:    ret
 entry: