[ARM] Use lrdsb for more thumb1 loads.

[dmgreen]

Summary

Given a sextload i16, we can usually generate ldrsh [rn. rm]. If we don't naturally have a rn, rm addressing mode, we can either generate ldrh rn, #0; sxth or mov rm, #0; ldrsh [rn. rm].

We currently generate the first, always creating a sxth. They are both the same number of instructions, but If we generate the second then the mov #0 will likely be CSE'd or pulled out of a loop, etc.

This adjusts the ISel patterns to do that, creating a mov instead of a sxth.

[SjoerdMeijer]

Make sense to me, but was just wondering if you haven't seen any regressions? If the constant is hoisted, it could contribute to higher register pressure and spilling?

[dmgreen]

Yeah as with any change like this, where register allocation is affected, some things will get better and some worse. It's always going to be a bit chaotic like that just because you might spill in a different place, and we only have 8 regs. In general this is an improvement in the testing I ran.

[SjoerdMeijer]

Okay, it's a bit of an indirect way, but fair enough I think.

llvm/lib/Target/ARM/ARMInstrThumb.td

 
 // post-inc STR -> STM r0!, {r1}. The layout of this (because it doesn't def
 // multiple registers) is the same in ISel as MachineInstr, so there's no need
 // for a pseudo.
 def : T1Pat<(post_store tGPR:$Rt, tGPR:$Rn, 4),
             (tSTMIA_UPD tGPR:$Rn, tGPR:$Rt)>;
 
 // If it's impossible to use [r,r] address mode for sextload, select to
-// ldr{b|h} + sxt{b|h} instead.
-def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
-            (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
-      Requires<[IsThumb, IsThumb1Only, HasV6]>;
-def : T1Pat<(sextloadi8 t_addrmode_rr:$addr),
-            (tSXTB (tLDRBr t_addrmode_rr:$addr))>,
+// ldsr{b|h} r, 0 instead, in a hope that the mov 0 will be more likely to be
+// commoned out than a sxth.
+let AddedComplexity = 10 in {
+def : T1Pat<(sextloadi8 tGPR:$Rn),
+            (tLDRSB tGPR:$Rn, (tMOVi8 0))>,
       Requires<[IsThumb, IsThumb1Only, HasV6]>;
-def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
-            (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
-      Requires<[IsThumb, IsThumb1Only, HasV6]>;
-def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),
-            (tSXTH (tLDRHr t_addrmode_rr:$addr))>,
+def : T1Pat<(sextloadi16 tGPR:$Rn),
+            (tLDRSH tGPR:$Rn, (tMOVi8 0))>,
       Requires<[IsThumb, IsThumb1Only, HasV6]>;
+}
 
 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
             (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
 def : T1Pat<(sextloadi8 t_addrmode_rr:$addr),
             (tASRri (tLSLri (tLDRBr t_addrmode_rr:$addr), 24), 24)>;
 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
             (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
 def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),

llvm/test/CodeGen/ARM/load.ll

entry:
   store i32 %x, i32* %arrayidx, align 4
   ret void
 }
 
 
 ; Immediate offset of zero
 
 ; CHECK-LABEL: ldrsb_ri_zero
-; CHECK-T1: ldrb    r0, [r0]
-; CHECK-T1: sxtb    r0, r0
+; CHECK-T1: movs    r1, #0
+; CHECK-T1: ldrsb   r0, [r0, r1]
 ; CHECK-T2: ldrsb.w r0, [r0]
 define i32 @ldrsb_ri_zero(i8* %p) {
 entry:
   %0 = load i8, i8* %p, align 1
   %conv = sext i8 %0 to i32
   ret i32 %conv
 }
 
 ; CHECK-LABEL: ldrsh_ri_zero
-; CHECK-T1: ldrh    r0, [r0]
-; CHECK-T1: sxth    r0, r0
+; CHECK-T1: movs    r1, #0
+; CHECK-T1: ldrsh   r0, [r0, r1]
 ; CHECK-T2: ldrsh.w r0, [r0]
 define i32 @ldrsh_ri_zero(i16* %p) {
 entry:
   %0 = load i16, i16* %p, align 2
   %conv = sext i16 %0 to i32
   ret i32 %conv
 }
 

llvm/test/CodeGen/ARM/select-imm.ll

 ; ARMT2: mov  r2, r0
 ; ARMT2: add  r2, r2, #1
 ; ARMT2: add  r1, r1, #1
 ; ARMT2: uxtb r3, r2
 ; ARMT2: cmp  r3, r0
 
 ; THUMB1-LABEL: t9:
 ; THUMB1: bl f
-; THUMB1: sxtb r1, r4
-; THUMB1: uxtb r0, r1
+; THUMB1: uxtb r0, r4
 ; THUMB1: cmp  r0, r0
-; THUMB1: adds r1, r1, #1
+; THUMB1: adds r1, r4, #1
 ; THUMB1: mov  r2, r0
 ; THUMB1: adds r1, r1, #1
 ; THUMB1: adds r2, r2, #1
 ; THUMB1: uxtb r3, r2
 ; THUMB1: cmp  r3, r0
 
 ; THUMB2-LABEL: t9:
 ; THUMB2: bl f

llvm/test/CodeGen/Thumb/ldr_ext.ll

; V6: ldrh
     ret i32 %tmp1.s
 }
 
 define i32 @test3(i8* %t0) nounwind {
 ; V5: ldrb
 ; V5: lsls
 ; V5: asrs
 
-; V6: ldrb
-; V6: sxtb
+; V6: mov
+; V6: ldrsb
     %tmp.s = load i8, i8* %t0
     %tmp1.s = sext i8 %tmp.s to i32
     ret i32 %tmp1.s
 }
 
 define i32 @test4(i16* %t0) nounwind {
 ; V5: ldrh
 ; V5: lsls
 ; V5: asrs
 
-; V6: ldrh
-; V6: sxth
+; V6: mov
+; V6: ldrsh
     %tmp.s = load i16, i16* %t0
     %tmp1.s = sext i16 %tmp.s to i32
     ret i32 %tmp1.s
 }
 
 define i32 @test5() nounwind {
 ; V5: movs r0, #0
 ; V5: ldrsh
 
 ; V6: movs r0, #0
 ; V6: ldrsh
     %tmp.s = load i16, i16* null
     %tmp1.s = sext i16 %tmp.s to i32
     ret i32 %tmp1.s
 }