diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td --- a/llvm/lib/Target/M68k/M68kInstrInfo.td +++ b/llvm/lib/Target/M68k/M68kInstrInfo.td @@ -206,14 +206,14 @@ def MxARD16_TC : MxRegOp; def MxARD32_TC : MxRegOp; -// TODO finish parser wiring -def MxMemAsmOperand : AsmOperandClass { - let Name = "MxMemOp"; +class MxOpClass : AsmOperandClass { + let Name = name; + let ParserMethod = "parse"#name; } class MxMemOp + AsmOperandClass parserMatchClass = ImmAsmOperand> : Operand, MxOperand { let PrintMethod = printMethod; let MIOperandInfo = ops; @@ -225,13 +225,14 @@ // register specified by the register field. The reference is classified as // a data reference with the exception of the jump and jump-to-subroutine // instructions. -def MxARI8 : MxMemOp<(ops AR32), MxSize8, "j", "printARI8Mem">; -def MxARI16 : MxMemOp<(ops AR32), MxSize16, "j", "printARI16Mem">; -def MxARI32 : MxMemOp<(ops AR32), MxSize32, "j", "printARI32Mem">; +def MxARI : MxOpClass<"ARI">; +def MxARI8 : MxMemOp<(ops AR32), MxSize8, "j", "printARI8Mem", MxARI>; +def MxARI16 : MxMemOp<(ops AR32), MxSize16, "j", "printARI16Mem", MxARI>; +def MxARI32 : MxMemOp<(ops AR32), MxSize32, "j", "printARI32Mem", MxARI>; -def MxARI8_TC : MxMemOp<(ops AR32_TC), MxSize8, "j", "printARI8Mem">; -def MxARI16_TC : MxMemOp<(ops AR32_TC), MxSize16, "j", "printARI16Mem">; -def MxARI32_TC : MxMemOp<(ops AR32_TC), MxSize32, "j", "printARI32Mem">; +def MxARI8_TC : MxMemOp<(ops AR32_TC), MxSize8, "j", "printARI8Mem", MxARI>; +def MxARI16_TC : MxMemOp<(ops AR32_TC), MxSize16, "j", "printARI16Mem", MxARI>; +def MxARI32_TC : MxMemOp<(ops AR32_TC), MxSize32, "j", "printARI32Mem", MxARI>; // ADDRESS REGISTER INDIRECT WITH POSTINCREMENT. The address of the operand is // in the address register specified by the register field. After the operand @@ -240,13 +241,14 @@ // is the stack pointer and the operand size is byte, the address is incremented // by two rather than one to keep the stack pointer on a word boundary. // The reference is classified as a data reference. -def MxARIPI8 : MxMemOp<(ops AR32), MxSize8, "o", "printARIPI8Mem">; -def MxARIPI16 : MxMemOp<(ops AR32), MxSize16, "o", "printARIPI16Mem">; -def MxARIPI32 : MxMemOp<(ops AR32), MxSize32, "o", "printARIPI32Mem">; +def MxARIPI : MxOpClass<"ARIPI">; +def MxARIPI8 : MxMemOp<(ops AR32), MxSize8, "o", "printARIPI8Mem", MxARIPI>; +def MxARIPI16 : MxMemOp<(ops AR32), MxSize16, "o", "printARIPI16Mem", MxARIPI>; +def MxARIPI32 : MxMemOp<(ops AR32), MxSize32, "o", "printARIPI32Mem", MxARIPI>; -def MxARIPI8_TC : MxMemOp<(ops AR32_TC), MxSize8, "o", "printARIPI8Mem">; -def MxARIPI16_TC : MxMemOp<(ops AR32_TC), MxSize16, "o", "printARIPI16Mem">; -def MxARIPI32_TC : MxMemOp<(ops AR32_TC), MxSize32, "o", "printARIPI32Mem">; +def MxARIPI8_TC : MxMemOp<(ops AR32_TC), MxSize8, "o", "printARIPI8Mem", MxARIPI>; +def MxARIPI16_TC : MxMemOp<(ops AR32_TC), MxSize16, "o", "printARIPI16Mem", MxARIPI>; +def MxARIPI32_TC : MxMemOp<(ops AR32_TC), MxSize32, "o", "printARIPI32Mem", MxARIPI>; // ADDRESS REGISTER INDIRECT WITH PREDECREMENT. The address of the operand is in // the address register specified by the register field. Before the operand @@ -255,26 +257,28 @@ // the stack pointer and the operand size is byte, the address is decremented by // two rather than one to keep the stack pointer on a word boundary. // The reference is classified as a data reference. -def MxARIPD8 : MxMemOp<(ops AR32), MxSize8, "e", "printARIPD8Mem">; -def MxARIPD16 : MxMemOp<(ops AR32), MxSize16, "e", "printARIPD16Mem">; -def MxARIPD32 : MxMemOp<(ops AR32), MxSize32, "e", "printARIPD32Mem">; +def MxARIPD : MxOpClass<"ARIPD">; +def MxARIPD8 : MxMemOp<(ops AR32), MxSize8, "e", "printARIPD8Mem", MxARIPD>; +def MxARIPD16 : MxMemOp<(ops AR32), MxSize16, "e", "printARIPD16Mem", MxARIPD>; +def MxARIPD32 : MxMemOp<(ops AR32), MxSize32, "e", "printARIPD32Mem", MxARIPD>; -def MxARIPD8_TC : MxMemOp<(ops AR32_TC), MxSize8, "e", "printARIPD8Mem">; -def MxARIPD16_TC : MxMemOp<(ops AR32_TC), MxSize16, "e", "printARIPD16Mem">; -def MxARIPD32_TC : MxMemOp<(ops AR32_TC), MxSize32, "e", "printARIPD32Mem">; +def MxARIPD8_TC : MxMemOp<(ops AR32_TC), MxSize8, "e", "printARIPD8Mem", MxARIPD>; +def MxARIPD16_TC : MxMemOp<(ops AR32_TC), MxSize16, "e", "printARIPD16Mem", MxARIPD>; +def MxARIPD32_TC : MxMemOp<(ops AR32_TC), MxSize32, "e", "printARIPD32Mem", MxARIPD>; // ADDRESS REGISTER INDIRECT WITH DISPLACEMENT. This addressing mode requires one // word of extension. The address of the operand is the sum of the address in // the address register and the sign-extended 16-bit displacement integer in the // extension word. The reference is classified as a data reference with the // exception of the jump and jump-to-subroutine instructions. -def MxARID8 : MxMemOp<(ops i16imm, AR32), MxSize8, "p", "printARID8Mem">; -def MxARID16 : MxMemOp<(ops i16imm, AR32), MxSize16, "p", "printARID16Mem">; -def MxARID32 : MxMemOp<(ops i16imm, AR32), MxSize32, "p", "printARID32Mem">; +def MxARID : MxOpClass<"ARID">; +def MxARID8 : MxMemOp<(ops i16imm, AR32), MxSize8, "p", "printARID8Mem", MxARID>; +def MxARID16 : MxMemOp<(ops i16imm, AR32), MxSize16, "p", "printARID16Mem", MxARID>; +def MxARID32 : MxMemOp<(ops i16imm, AR32), MxSize32, "p", "printARID32Mem", MxARID>; -def MxARID8_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize8, "p", "printARID8Mem">; -def MxARID16_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize16, "p", "printARID16Mem">; -def MxARID32_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize32, "p", "printARID32Mem">; +def MxARID8_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize8, "p", "printARID8Mem", MxARID>; +def MxARID16_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize16, "p", "printARID16Mem", MxARID>; +def MxARID32_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize32, "p", "printARID32Mem", MxARID>; // ADDRESS REGISTER INDIRECT WITH INDEX. This addressing mode requires one word // of extension. The address of the operand is the sum of the address in the @@ -282,21 +286,23 @@ // bits of the extension word, and the contents of the index register. // The reference is classified as a data reference with the exception of the // jump and jump-to-subroutine instructions -def MxARII8 : MxMemOp<(ops i8imm, AR32, XR32), MxSize8, "f", "printARII8Mem">; -def MxARII16 : MxMemOp<(ops i8imm, AR32, XR32), MxSize16, "f", "printARII16Mem">; -def MxARII32 : MxMemOp<(ops i8imm, AR32, XR32), MxSize32, "f", "printARII32Mem">; +def MxARII : MxOpClass<"ARII">; +def MxARII8 : MxMemOp<(ops i8imm, AR32, XR32), MxSize8, "f", "printARII8Mem", MxARII>; +def MxARII16 : MxMemOp<(ops i8imm, AR32, XR32), MxSize16, "f", "printARII16Mem", MxARII>; +def MxARII32 : MxMemOp<(ops i8imm, AR32, XR32), MxSize32, "f", "printARII32Mem", MxARII>; -def MxARII8_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize8, "f", "printARII8Mem">; -def MxARII16_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize16, "f", "printARII16Mem">; -def MxARII32_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize32, "f", "printARII32Mem">; +def MxARII8_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize8, "f", "printARII8Mem", MxARII>; +def MxARII16_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize16, "f", "printARII16Mem", MxARII>; +def MxARII32_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize32, "f", "printARII32Mem", MxARII>; // ABSOLUTE SHORT ADDRESS. This addressing mode requires one word of extension. // The address of the operand is the extension word. The 16-bit address is sign // extended before it is used. The reference is classified as a data reference // with the exception of the jump and jump-tosubroutine instructions. -def MxAS8 : MxMemOp<(ops OtherVT), MxSize8, "B", "printAS8Mem">; -def MxAS16 : MxMemOp<(ops OtherVT), MxSize16, "B", "printAS16Mem">; -def MxAS32 : MxMemOp<(ops OtherVT), MxSize32, "B", "printAS32Mem">; +def MxAddr : MxOpClass<"Addr">; +def MxAS8 : MxMemOp<(ops OtherVT), MxSize8, "B", "printAS8Mem", MxAddr>; +def MxAS16 : MxMemOp<(ops OtherVT), MxSize16, "B", "printAS16Mem", MxAddr>; +def MxAS32 : MxMemOp<(ops OtherVT), MxSize32, "B", "printAS32Mem", MxAddr>; // ABSOLUTE LONG ADDRESS. This addressing mode requires two words of extension. // The address of the operand is developed by the concatenation of the extension @@ -304,9 +310,12 @@ // order part of the address is the second extension word. The reference is // classified as a data reference with the exception of the jump and jump // to-subroutine instructions. -def MxAL8 : MxMemOp<(ops OtherVT), MxSize8, "b", "printAL8Mem">; -def MxAL16 : MxMemOp<(ops OtherVT), MxSize16, "b", "printAL16Mem">; -def MxAL32 : MxMemOp<(ops OtherVT), MxSize32, "b", "printAL32Mem">; +def MxAL8 : MxMemOp<(ops OtherVT), MxSize8, "b", "printAL8Mem", MxAddr>; +def MxAL16 : MxMemOp<(ops OtherVT), MxSize16, "b", "printAL16Mem", MxAddr>; +def MxAL32 : MxMemOp<(ops OtherVT), MxSize32, "b", "printAL32Mem", MxAddr>; + +def MxPCD : MxOpClass<"PCD">; +def MxPCI : MxOpClass<"PCI">; let OperandType = "OPERAND_PCREL" in { // PROGRAM COUNTER WITH DISPLACEMENT. This addressing mode requires one word of @@ -314,9 +323,9 @@ // counter and the Sign-extended 16-bit displacement integer in the extension // word. The value in the program counter is the address of the extension word. // The reference is classified as a program reference. -def MxPCD8 : MxMemOp<(ops i16imm), MxSize8, "q", "printPCD8Mem">; -def MxPCD16 : MxMemOp<(ops i16imm), MxSize16, "q", "printPCD16Mem">; -def MxPCD32 : MxMemOp<(ops i16imm), MxSize32, "q", "printPCD32Mem">; +def MxPCD8 : MxMemOp<(ops i16imm), MxSize8, "q", "printPCD8Mem", MxPCD>; +def MxPCD16 : MxMemOp<(ops i16imm), MxSize16, "q", "printPCD16Mem", MxPCD>; +def MxPCD32 : MxMemOp<(ops i16imm), MxSize32, "q", "printPCD32Mem", MxPCD>; // PROGRAM COUNTER WITH INDEX. This addressing mode requires one word of // extension. The address is the sum of the address in the program counter, the @@ -324,14 +333,18 @@ // word, and the contents of the index register. The value in the program // counter is the address of the extension word. This reference is classified as // a program reference. -def MxPCI8 : MxMemOp<(ops i8imm, XR32), MxSize8, "k", "printPCI8Mem">; -def MxPCI16 : MxMemOp<(ops i8imm, XR32), MxSize16, "k", "printPCI16Mem">; -def MxPCI32 : MxMemOp<(ops i8imm, XR32), MxSize32, "k", "printPCI32Mem">; +def MxPCI8 : MxMemOp<(ops i8imm, XR32), MxSize8, "k", "printPCI8Mem", MxPCI>; +def MxPCI16 : MxMemOp<(ops i8imm, XR32), MxSize16, "k", "printPCI16Mem", MxPCI>; +def MxPCI32 : MxMemOp<(ops i8imm, XR32), MxSize32, "k", "printPCI32Mem", MxPCI>; } // OPERAND_PCREL +def MxImm : MxOpClass<"MxImm">; + class MxOp : Operand, - MxOperand; + MxOperand { + let ParserMatchClass = MxImm; +} let OperandType = "OPERAND_IMMEDIATE", PrintMethod = "printImmediate" in { @@ -349,6 +362,7 @@ } // OPERAND_IMMEDIATE let OperandType = "OPERAND_PCREL", + ParserMatchClass = MxImm, PrintMethod = "printPCRelImm" in { // Branch targets have OtherVT type and print as pc-relative values.