[RISCV] Add SiFive-VIU75 for llvm

[arcbbb]

Summary

This patch adds support for the SiFive CPU VIU75.

details of the CPU can be found here:
https://www.sifive.com/cores/viu75

[jrtc27]

llvm/lib/Target/RISCV/RISCV.td

281–283

I don't think we should ever enable V and related extensions here for two reasons:

1. They're currently experimental, so -mcpu=sifive-viu75 bypasses -menable-experimental-extensions.

2. They're still drafts that are going to see changes and we don't maintain backwards compatibility between draft revisions, so as soon as there's a new draft spec we'll have to remove these extensions from this model as the core will no longer implement the spec version we do.

[khchen]

llvm/lib/Target/RISCV/RISCV.td

281–283

They're currently experimental, so -mcpu=sifive-viu75 bypasses -menable-experimental-extensions.

Agree.
I think maybe we could find a way to force users to give -menable-experimental-extensions in llc when they use a cpu which has experimental features, it will be acceptable for me.

or maybe the cpu naming should be -mcput=experimental-sifive-viu75 like -mattr=+experimental-v?

[arcbbb]

I think we can hold this for the time being until it is ratified or no longer experimental.

[asb]

llvm/lib/Target/RISCV/RISCV.td

281–283

I agree, if there's a desire to enable the unratified V extensions that's a discussion to be had with the wider LLVM community. It would be unfortunate if shipping devices ended up supporting unratified extension versions that don't match the ratified version, adding extra burden in terms of compiler support.

It may make sense for LLVM to support this (where there are users and people willing to maintain support), but we'd want an llvm-dev discussion about what kind of precedent it sets, expectations in ongoing support etc.

[arcbbb]

Thank you for all the suggestions.

It does require a discussion to draw the line when supporting a device with an unratified extension.
I abandon it because now it is deprecated.

llvm/lib/Target/RISCV/RISCV.td

 
 def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
                                                   FeatureStdExtM,
                                                   FeatureStdExtA,
                                                   FeatureStdExtF,
                                                   FeatureStdExtD,
                                                   FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-viu75", SiFive7Model, [Feature64Bit,
+                                                    FeatureStdExtM,
+                                                    FeatureStdExtA,
+                                                    FeatureStdExtF,
+                                                    FeatureStdExtD,
+                                                    FeatureStdExtC,
+                                                    FeatureStdExtV,
+                                                    FeatureStdExtZvlsseg,
+                                                    FeatureExtZvamo,
+                                                    FeatureExtZfh]>;
+
 //===----------------------------------------------------------------------===//
 // Define the RISC-V target.
 //===----------------------------------------------------------------------===//
 
 def RISCVInstrInfo : InstrInfo {
   let guessInstructionProperties = 0;
 }