diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-0.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-0.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-0.s
@@ -0,0 +1,5 @@
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --dispatch-stats --iterations=1000 < %s | FileCheck %s
+# CHECK: IPC:
+# CHECK-SAME: 1.00
+
+add	w8, w8, #1
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-1.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-1.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-1.s
@@ -0,0 +1,6 @@
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --dispatch-stats --iterations=1000 < %s | FileCheck %s
+# CHECK: IPC:
+# CHECK-SAME: 1.99
+
+add	w8, w8, #1
+add	w9, w9, #1
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-2.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-2.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-2.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --dispatch-stats --iterations=1000 < %s | FileCheck %s
+# CHECK: IPC:
+# CHECK-SAME: 2.00
+
+# Cortex-A55 has a secondary skewed ALU in the Ex1 stage for simple
+# ALU instructions that do not require shifting or saturation
+# resources. Results from the skewed ALU are available 1 cycle earlier.
+#
+# This features allows the first and the second instruction to be
+# dual-issued despite a register dependency (w8).
+#
+# MCA and LLVM scheduling model do not support this yet.
+#
+# XFAIL: *
+
+add	w8, w8, #1
+add	w10, w8, #1
+add	w12, w8, #1
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-3.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-3.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-3.s
@@ -0,0 +1,7 @@
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --dispatch-stats --iterations=1000 < %s | FileCheck %s
+# CHECK: IPC:
+# CHECK-SAME: 1.00
+
+add	w8, w8, #1
+add	w12, w8, #1
+mul	w10, w10, w10
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-4.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-4.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-4.s
@@ -0,0 +1,15 @@
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --dispatch-stats --iterations=1000 < %s | FileCheck %s
+# CHECK: IPC:
+# CHECK-SAME: 0.52
+
+# FIXME: DIV is not modeled precisely: on hardware it takes variable
+# number of cycles depending on its operands. LLVM scheduling model
+# only provides an average latency.
+#
+# XFAIL: *
+
+add	w8, w8, #1
+mov	w10, #4
+mov	w12, #8
+add	w12, w8, #1
+sdiv	w10, w12, w10
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-5.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-5.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-5.s
@@ -0,0 +1,16 @@
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --dispatch-stats --iterations=1000 < %s | FileCheck %s
+# CHECK: IPC:
+# CHECK-SAME: 0.50
+
+# FIXME: DIV is not modeled precisely: on hardware it takes variable
+# number of cycles depending on its operands. LLVM scheduling model
+# only provides an average latency.
+#
+# XFAIL: *
+
+add	w8, w8, #1
+mov	w10, #3
+mov	w12, #81
+add	w12, w8, #1
+mul	w10, w10, w10
+sdiv	w10, w12, w10
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-6.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-6.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-6.s
@@ -0,0 +1,7 @@
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --dispatch-stats --iterations=1000 < %s | FileCheck %s
+# CHECK: IPC:
+# CHECK-SAME: 1.00
+
+add	w8, w8, #1
+add	w12, w8, #1
+mul	w10, w12, w10
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-7.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-7.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-7.s
@@ -0,0 +1,8 @@
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --dispatch-stats --iterations=1000 < %s | FileCheck %s
+# CHECK: IPC:
+# CHECK-SAME: 1.33
+
+add	w8, w8, #1
+cmp	w8, #42
+add	w12, w8, #1
+mul	w10, w12, w10
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-8.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-8.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-8.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --dispatch-stats --iterations=1000 < %s | FileCheck %s
+# CHECK: IPC:
+# CHECK-SAME: 1.50
+
+# MCA reports IPC = 0.75, while hardware shows IPC = 1.50.
+#
+# 1) The skewed ALU on Cortex-A55 is not modeled: ADD and AND
+#    instructions should be issued in the same cycle.
+#    See A55-2.s test for more details.
+#
+# 2) Cortex-A55 manual mentions that there is a forwarding path from
+#    the ALU pipeline to the LD/ST pipeline. This is not implemented in
+#    the LLVM scheduling model.
+#
+# XFAIL: *
+
+add	w8, w8, #1
+and	w12, w8, #0x3f
+ldr	w14, [x10, w12, uxtw #2]