diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -428,19 +428,6 @@ } Insn = support::endian::read32le(Bytes.data()); - if (STI.getFeatureBits()[RISCV::FeatureStdExtZbkb] || - STI.getFeatureBits()[RISCV::FeatureStdExtZbkc] || - STI.getFeatureBits()[RISCV::FeatureStdExtZbkx]) { - LLVM_DEBUG(dbgs() << "Trying RVZbkb table (Float in Integer):\n"); - // Calling the auto-generated decoder function. - Result = - decodeInstruction(DecoderTableRVK32, MI, Insn, Address, this, STI); - if (Result != MCDisassembler::Fail) { - Size = 4; - return Result; - } - } - LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n"); Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); Size = 4; diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -143,27 +143,6 @@ "'Zbb' (Base 'B' Instructions) or " "'Zbp' (Permutation 'B' Instructions)">; -def FeatureStdExtZbkb - : SubtargetFeature<"experimental-zbkb", "HasStdExtZbkb", "true", - "'Zbkb' (Bitmanip instructions for Cryptography)">; -def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">, - AssemblerPredicate<(all_of FeatureStdExtZbkb), - "'Zbkb' (Bitmanip instructions for Cryptography)">; - -def FeatureStdExtZbkc - : SubtargetFeature<"experimental-zbkc", "HasStdExtZbkc", "true", - "'Zbkc' (Carry-less multiply instructions)">; -def HasStdExtZbkc : Predicate<"Subtarget->hasStdExtZbkc()">, - AssemblerPredicate<(all_of FeatureStdExtZbkc), - "'Zbkc' (Carry-less multiply instructions)">; - -def FeatureStdExtZbkx - : SubtargetFeature<"experimental-zbkx", "HasStdExtZbkx", "true", - "'Zbkx' (Crossbar permutation instructions)">; -def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">, - AssemblerPredicate<(all_of FeatureStdExtZbkx), - "'Zbkx' (Crossbar permutation instructions)">; - def FeatureStdExtZknd : SubtargetFeature<"experimental-zknd", "HasStdExtZknd", "true", "'Zknd' (NIST Suite: AES Decryption)">; @@ -217,10 +196,7 @@ def FeatureStdExtZkn : SubtargetFeature<"experimental-zkn", "HasStdExtZkn", "true", "'Zkn' (NIST Algorithm Suite)", - [FeatureStdExtZbkb, - FeatureStdExtZbkc, - FeatureStdExtZbkx, - FeatureStdExtZkne, + [FeatureStdExtZkne, FeatureStdExtZknd, FeatureStdExtZknh]>; def HasStdExtZkn : Predicate<"Subtarget->hasStdExtZkn()">, @@ -230,10 +206,7 @@ def FeatureStdExtZks : SubtargetFeature<"experimental-zks", "HasStdExtZks", "true", "'Zks' (ShangMi Algorithm Suite)", - [FeatureStdExtZbkb, - FeatureStdExtZbkc, - FeatureStdExtZbkx, - FeatureStdExtZksed, + [FeatureStdExtZksed, FeatureStdExtZksh]>; def HasStdExtZks : Predicate<"Subtarget->hasStdExtZks()">, AssemblerPredicate<(all_of FeatureStdExtZks), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td @@ -77,60 +77,6 @@ // Instructions //===----------------------------------------------------------------------===// -let DecoderNamespace = "RVK" in { -let Predicates = [HasStdExtZbkb] in { -def ROR_K : ALU_rr<0b0110000, 0b101, "ror">, - Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>; -def ROL_K : ALU_rr<0b0110000, 0b001, "rol">, - Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>; - -def RORI_K : RVKShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">, - Sched<[WriteRotateImm, ReadRotateImm]>; - -def ANDN_K : ALU_rr<0b0100000, 0b111, "andn">, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; -def ORN_K : ALU_rr<0b0100000, 0b110, "orn">, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; -def XNOR_K : ALU_rr<0b0100000, 0b100, "xnor">, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; - -def PACK_K : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>; -def PACKH_K : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>; - -def BREV8 : RVKUnary<0b011010000111, 0b101, "brev8">; -} // Predicates = [HasStdExtZbkb] - -let Predicates = [HasStdExtZbkb, IsRV32] in { -def REV8_RV32_K : RVKUnary<0b011010011000, 0b101, "rev8">; -def ZIP : RVKUnary<0b000010001111, 0b001, "zip">; -def UNZIP : RVKUnary<0b000010001111, 0b101, "unzip">; -} // Predicates = [HasStdExtZbkb, IsRV32] - -let Predicates = [HasStdExtZbkb, IsRV64] in { -def RORW_K : ALUW_rr<0b0110000, 0b101, "rorw">, - Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>; -def ROLW_K : ALUW_rr<0b0110000, 0b001, "rolw">, - Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>; - -def RORIW_K : RVKShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">, - Sched<[WriteRotateImm32, ReadRotateImm32]>; - -def PACKW_K : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>; - -def REV8_RV64_K : RVKUnary<0b011010111000, 0b101, "rev8">; -} // Predicates = [HasStdExtZbkb, IsRV64] - -let Predicates = [HasStdExtZbkc] in { -def CLMUL_K : ALU_rr<0b0000101, 0b001, "clmul">, Sched<[]>; -def CLMULH_K : ALU_rr<0b0000101, 0b011, "clmulh">, Sched<[]>; -} // Predicates = [HasStdExtZbkc] - -let Predicates = [HasStdExtZbkx] in { -def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>; -def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>; -} // Predicates = [HasStdExtZbkx] -} // DecoderNamespace = "RVK" - let Predicates = [HasStdExtZknd, IsRV32] in { def AES32DSI : RVKByteSelect<0b10101, "aes32dsi">; def AES32DSMI : RVKByteSelect<0b10111, "aes32dsmi">; diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td --- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -16,8 +16,7 @@ let IssueWidth = 1; // 1 micro-op is dispatched per cycle. let LoadLatency = 3; let MispredictPenalty = 3; - let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, - HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, + let UnsupportedFeatures = [HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, HasStdExtZkn, HasStdExtZks, HasStdExtZkt, HasStdExtZk, HasStdExtV, HasStdExtZvamo, diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -15,8 +15,7 @@ let LoadLatency = 3; let MispredictPenalty = 3; let CompleteModel = 0; - let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, - HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, + let UnsupportedFeatures = [HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, HasStdExtZkn, HasStdExtZks, HasStdExtZkt, HasStdExtZk, HasStdExtV, HasStdExtZvamo, diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -49,9 +49,6 @@ bool HasStdExtZbr = false; bool HasStdExtZbs = false; bool HasStdExtZbt = false; - bool HasStdExtZbkb = false; - bool HasStdExtZbkc = false; - bool HasStdExtZbkx = false; bool HasStdExtZknd = false; bool HasStdExtZkne = false; bool HasStdExtZknh = false; @@ -129,9 +126,6 @@ bool hasStdExtZbr() const { return HasStdExtZbr; } bool hasStdExtZbs() const { return HasStdExtZbs; } bool hasStdExtZbt() const { return HasStdExtZbt; } - bool hasStdExtZbkb() const { return HasStdExtZbkb; } - bool hasStdExtZbkc() const { return HasStdExtZbkc; } - bool hasStdExtZbkx() const { return HasStdExtZbkx; } bool hasStdExtZknd() const { return HasStdExtZknd; } bool hasStdExtZkne() const { return HasStdExtZkne; } bool hasStdExtZknh() const { return HasStdExtZknh; } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -18,9 +18,6 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbkb %s -o - | FileCheck --check-prefix=RV32ZBKB %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbkc %s -o - | FileCheck --check-prefix=RV32ZBKC %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbkx %s -o - | FileCheck --check-prefix=RV32ZBKX %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zknd %s -o - | FileCheck --check-prefix=RV32ZKND %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zkne %s -o - | FileCheck --check-prefix=RV32ZKNE %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zknh %s -o - | FileCheck --check-prefix=RV32ZKNH %s @@ -50,9 +47,6 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbkb %s -o - | FileCheck --check-prefix=RV64ZBKB %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbkc %s -o - | FileCheck --check-prefix=RV64ZBKC %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbkx %s -o - | FileCheck --check-prefix=RV64ZBKX %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zknd %s -o - | FileCheck --check-prefix=RV64ZKND %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zkne %s -o - | FileCheck --check-prefix=RV64ZKNE %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zknh %s -o - | FileCheck --check-prefix=RV64ZKNH %s @@ -83,19 +77,16 @@ ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93" ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0" ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93" -; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0" -; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0" -; RV32ZBKX: .attribute 5, "rv32i2p0_zbkx1p0" ; RV32ZKND: .attribute 5, "rv32i2p0_zknd1p0" ; RV32ZKNE: .attribute 5, "rv32i2p0_zkne1p0" ; RV32ZKNH: .attribute 5, "rv32i2p0_zknh1p0" ; RV32ZKSED: .attribute 5, "rv32i2p0_zksed1p0" ; RV32ZKSH: .attribute 5, "rv32i2p0_zksh1p0" ; RV32ZKR: .attribute 5, "rv32i2p0_zkr1p0" -; RV32ZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0" -; RV32ZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0" +; RV32ZKN: .attribute 5, "rv32i2p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0" +; RV32ZKS: .attribute 5, "rv32i2p0_zks1p0_zksed1p0_zksh1p0" ; RV32ZKT: .attribute 5, "rv32i2p0_zkt1p0" -; RV32ZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0" +; RV32ZK: .attribute 5, "rv32i2p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0" ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zfhmin0p1_zbb1p0_zvamo0p10_zvlsseg0p10" ; RV64M: .attribute 5, "rv64i2p0_m2p0" @@ -115,19 +106,16 @@ ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93" ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0" ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93" -; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0" -; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0" -; RV64ZBKX: .attribute 5, "rv64i2p0_zbkx1p0" ; RV64ZKND: .attribute 5, "rv64i2p0_zknd1p0" ; RV64ZKNE: .attribute 5, "rv64i2p0_zkne1p0" ; RV64ZKNH: .attribute 5, "rv64i2p0_zknh1p0" ; RV64ZKSED: .attribute 5, "rv64i2p0_zksed1p0" ; RV64ZKSH: .attribute 5, "rv64i2p0_zksh1p0" ; RV64ZKR: .attribute 5, "rv64i2p0_zkr1p0" -; RV64ZKN: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0" -; RV64ZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0" +; RV64ZKN: .attribute 5, "rv64i2p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0" +; RV64ZKS: .attribute 5, "rv64i2p0_zks1p0_zksed1p0_zksh1p0" ; RV64ZKT: .attribute 5, "rv64i2p0_zkt1p0" -; RV64ZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0" +; RV64ZK: .attribute 5, "rv64i2p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0" ; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10" ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zfhmin0p1_zbb1p0_zvamo0p10_zvlsseg0p10" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -66,15 +66,6 @@ .attribute arch, "rv32izbt" # CHECK: attribute 5, "rv32i2p0_zbt0p93" -.attribute arch, "rv32i_zbkb1p0" -# CHECK: attribute 5, "rv32i2p0_zbkb1p0" - -.attribute arch, "rv32i_zbkc1p0" -# CHECK: attribute 5, "rv32i2p0_zbkc1p0" - -.attribute arch, "rv32i_zbkx1p0" -# CHECK: attribute 5, "rv32i2p0_zbkx1p0" - .attribute arch, "rv32i_zknd1p0" # CHECK: attribute 5, "rv32i2p0_zknd1p0" @@ -94,16 +85,16 @@ # CHECK: attribute 5, "rv32i2p0_zkr1p0" .attribute arch, "rv32i_zkn1p0" -# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0" +# CHECK: attribute 5, "rv32i2p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0" .attribute arch, "rv32i_zks1p0" -# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0" +# CHECK: attribute 5, "rv32i2p0_zks1p0_zksed1p0_zksh1p0" .attribute arch, "rv32i_zkt1p0" # CHECK: attribute 5, "rv32i2p0_zkt1p0" .attribute arch, "rv32i_zk1p0" -# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0" +# CHECK: attribute 5, "rv32i2p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0" .attribute arch, "rv32ifzfhmin" # CHECK: attribute 5, "rv32i2p0_f2p0_zfhmin0p1" diff --git a/llvm/test/MC/RISCV/rv32zbkb-only-valid.s b/llvm/test/MC/RISCV/rv32zbkb-only-valid.s deleted file mode 100644 --- a/llvm/test/MC/RISCV/rv32zbkb-only-valid.s +++ /dev/null @@ -1,16 +0,0 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbkb -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbkb < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbkb -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: rev8 t0, t1 -# CHECK-ASM: encoding: [0x93,0x52,0x83,0x69] -rev8 t0, t1 - -# CHECK-ASM-AND-OBJ: zip t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0xf3,0x08] -zip t0, t1 -# CHECK-S-OBJ-NOALIAS: unzip t0, t1 -# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x08] -unzip t0, t1 diff --git a/llvm/test/MC/RISCV/rv32zbkb-valid.s b/llvm/test/MC/RISCV/rv32zbkb-valid.s deleted file mode 100644 --- a/llvm/test/MC/RISCV/rv32zbkb-valid.s +++ /dev/null @@ -1,45 +0,0 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbkb -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbkb -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbkb < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbkb -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbkb < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbkb -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: ror t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60] -ror t0, t1, t2 -# CHECK-ASM-AND-OBJ: rol t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x60] -rol t0, t1, t2 -# CHECK-ASM-AND-OBJ: rori t0, t1, 31 -# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61] -rori t0, t1, 31 -# CHECK-ASM-AND-OBJ: rori t0, t1, 0 -# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60] -rori t0, t1, 0 - -# CHECK-ASM-AND-OBJ: andn t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x40] -andn t0, t1, t2 -# CHECK-ASM-AND-OBJ: orn t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x40] -orn t0, t1, t2 -# CHECK-ASM-AND-OBJ: xnor t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x40] -xnor t0, t1, t2 - -# CHECK-ASM: pack t0, t1, zero -# CHECK-OBJ: zext.h t0, t1 -# CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08] -pack t0, t1, x0 -# CHECK-ASM-AND-OBJ: packh t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x08] -packh t0, t1, t2 - -# CHECK-ASM-AND-OBJ: brev8 t0, t1 -# CHECK-ASM: encoding: [0x93,0x52,0x73,0x68] -brev8 t0, t1 diff --git a/llvm/test/MC/RISCV/rv32zbkc-valid.s b/llvm/test/MC/RISCV/rv32zbkc-valid.s deleted file mode 100644 --- a/llvm/test/MC/RISCV/rv32zbkc-valid.s +++ /dev/null @@ -1,17 +0,0 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbkc -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbkc -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbkc < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbkc -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbkc < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbkc -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: clmul t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x0a] -clmul t0, t1, t2 -# CHECK-ASM-AND-OBJ: clmulh t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x0a] -clmulh t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv32zbkx-valid.s b/llvm/test/MC/RISCV/rv32zbkx-valid.s deleted file mode 100644 --- a/llvm/test/MC/RISCV/rv32zbkx-valid.s +++ /dev/null @@ -1,17 +0,0 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbkx -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbkx -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbkx < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbkx -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbkx < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbkx -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: xperm8 t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x28] -xperm8 t0, t1, t2 -# CHECK-ASM-AND-OBJ: xperm4 t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x28] -xperm4 t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64-zbkb-valid.s b/llvm/test/MC/RISCV/rv64-zbkb-valid.s deleted file mode 100644 --- a/llvm/test/MC/RISCV/rv64-zbkb-valid.s +++ /dev/null @@ -1,22 +0,0 @@ -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbkb -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbkb < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbkb -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: rorw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60] -rorw t0, t1, t2 -# CHECK-ASM-AND-OBJ: rolw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x60] -rolw t0, t1, t2 -# CHECK-ASM-AND-OBJ: roriw t0, t1, 31 -# CHECK-ASM: encoding: [0x9b,0x52,0xf3,0x61] -roriw t0, t1, 31 -# CHECK-ASM-AND-OBJ: roriw t0, t1, 0 -# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x60] -roriw t0, t1, 0 - -# CHECK-ASM-AND-OBJ: packw t0, t1, t2 -# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x08] -packw t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64zbkb-only-valid.s b/llvm/test/MC/RISCV/rv64zbkb-only-valid.s deleted file mode 100644 --- a/llvm/test/MC/RISCV/rv64zbkb-only-valid.s +++ /dev/null @@ -1,9 +0,0 @@ -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbkb -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbkb < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zbkb -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s - -# CHECK-ASM-AND-OBJ: rev8 t0, t1 -# CHECK-ASM: encoding: [0x93,0x52,0x83,0x6b] -rev8 t0, t1