diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -61,6 +61,20 @@ {"zbs", RISCVExtensionVersion{1, 0}}, {"zbt", RISCVExtensionVersion{0, 93}}, + {"zbkb", RISCVExtensionVersion{1, 0}}, + {"zbkc", RISCVExtensionVersion{1, 0}}, + {"zbkx", RISCVExtensionVersion{1, 0}}, + {"zknd", RISCVExtensionVersion{1, 0}}, + {"zkne", RISCVExtensionVersion{1, 0}}, + {"zknh", RISCVExtensionVersion{1, 0}}, + {"zksed", RISCVExtensionVersion{1, 0}}, + {"zksh", RISCVExtensionVersion{1, 0}}, + {"zkr", RISCVExtensionVersion{1, 0}}, + {"zkn", RISCVExtensionVersion{1, 0}}, + {"zks", RISCVExtensionVersion{1, 0}}, + {"zkt", RISCVExtensionVersion{1, 0}}, + {"zk", RISCVExtensionVersion{1, 0}}, + {"zvamo", RISCVExtensionVersion{0, 10}}, {"zvlsseg", RISCVExtensionVersion{0, 10}}, diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -546,6 +546,16 @@ return IsConstantImm && isUInt<7>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; } + bool isRnumArg() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && Imm >= INT64_C(0) && Imm <= INT64_C(10) && + VK == RISCVMCExpr::VK_RISCV_None; + } + bool isSImm5() const { if (!isImm()) return false; @@ -1206,6 +1216,9 @@ (1 << 4), "immediate must be in the range"); } + case Match_InvalidRnumArg: { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 6); + } } llvm_unreachable("Unknown match type detected!"); diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -427,6 +427,20 @@ return MCDisassembler::Fail; } Insn = support::endian::read32le(Bytes.data()); + + if (STI.getFeatureBits()[RISCV::FeatureStdExtZbkb] || + STI.getFeatureBits()[RISCV::FeatureStdExtZbkc] || + STI.getFeatureBits()[RISCV::FeatureStdExtZbkx]) { + LLVM_DEBUG(dbgs() << "Trying RVZbkb table (Float in Integer):\n"); + // Calling the auto-generated decoder function. + Result = + decodeInstruction(DecoderTableRVK32, MI, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n"); Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); Size = 4; diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -135,6 +135,119 @@ "'Zbb' (Base 'B' Instructions) or " "'Zbp' (Permutation 'B' Instructions)">; +def FeatureStdExtZbkb + : SubtargetFeature<"experimental-zbkb", "HasStdExtZbkb", "true", + "'Zbkb' (Bitmanip instructions for Cryptography)">; +def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">, + AssemblerPredicate<(all_of FeatureStdExtZbkb), + "'Zbkb' (Bitmanip instructions for Cryptography)">; + +def FeatureStdExtZbkc + : SubtargetFeature<"experimental-zbkc", "HasStdExtZbkc", "true", + "'Zbkc' (Carry-less multiply instructions)">; +def HasStdExtZbkc : Predicate<"Subtarget->hasStdExtZbkc()">, + AssemblerPredicate<(all_of FeatureStdExtZbkc), + "'Zbkc' (Carry-less multiply instructions)">; + +def FeatureStdExtZbkx + : SubtargetFeature<"experimental-zbkx", "HasStdExtZbkx", "true", + "'Zbkx' (Crossbar permutation instructions)">; +def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">, + AssemblerPredicate<(all_of FeatureStdExtZbkx), + "'Zbkx' (Crossbar permutation instructions)">; + +def FeatureStdExtZknd + : SubtargetFeature<"experimental-zknd", "HasStdExtZknd", "true", + "'Zknd' (NIST Suite: AES Decryption)">; +def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">, + AssemblerPredicate<(all_of FeatureStdExtZknd), + "'Zknd' (NIST Suite: AES Decryption)">; + +def FeatureStdExtZkne + : SubtargetFeature<"experimental-zkne", "HasStdExtZkne", "true", + "'Zkne' (NIST Suite: AES Encryption)">; +def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">, + AssemblerPredicate<(all_of FeatureStdExtZkne), + "'Zkne' (NIST Suite: AES Encryption)">; + +// Some instructions belong to both Zknd and Zkne subextensions. +// They should be enabled if either has been specified. +def HasStdExtZkndOrZkne + : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">, + AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne), + "'Zknd' (NIST Suite: AES Decryption) or " + "'Zkne' (NIST Suite: AES Encryption)">; + +def FeatureStdExtZknh + : SubtargetFeature<"experimental-zknh", "HasStdExtZknh", "true", + "'Zknh' (NIST Suite: Hash Function Instructions)">; +def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">, + AssemblerPredicate<(all_of FeatureStdExtZknh), + "'Zknh' (NIST Suite: Hash Function Instructions)">; + +def FeatureStdExtZksed + : SubtargetFeature<"experimental-zksed", "HasStdExtZksed", "true", + "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; +def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">, + AssemblerPredicate<(all_of FeatureStdExtZksed), + "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; + +def FeatureStdExtZksh + : SubtargetFeature<"experimental-zksh", "HasStdExtZksh", "true", + "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; +def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">, + AssemblerPredicate<(all_of FeatureStdExtZksh), + "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; + +def FeatureStdExtZkr + : SubtargetFeature<"experimental-zkr", "HasStdExtZkr", "true", + "'Zkr' (Entropy Source Extension)">; +def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">, + AssemblerPredicate<(all_of FeatureStdExtZkr), + "'Zkr' (Entropy Source Extension)">; + +def FeatureStdExtZkn + : SubtargetFeature<"experimental-zkn", "HasStdExtZkn", "true", + "'Zkn' (NIST Algorithm Suite)", + [FeatureStdExtZbkb, + FeatureStdExtZbkc, + FeatureStdExtZbkx, + FeatureStdExtZkne, + FeatureStdExtZknd, + FeatureStdExtZknh]>; +def HasStdExtZkn : Predicate<"Subtarget->hasStdExtZkn()">, + AssemblerPredicate<(all_of FeatureStdExtZkn), + "'Zkn' (NIST Algorithm Suite)">; + +def FeatureStdExtZks + : SubtargetFeature<"experimental-zks", "HasStdExtZks", "true", + "'Zks' (ShangMi Algorithm Suite)", + [FeatureStdExtZbkb, + FeatureStdExtZbkc, + FeatureStdExtZbkx, + FeatureStdExtZksed, + FeatureStdExtZksh]>; +def HasStdExtZks : Predicate<"Subtarget->hasStdExtZks()">, + AssemblerPredicate<(all_of FeatureStdExtZks), + "'Zks' (ShangMi Algorithm Suite)">; + +def FeatureStdExtZkt + : SubtargetFeature<"experimental-zkt", "HasStdExtZkt", "true", + "'Zkt' (Data Independent Execution Latency)">; +def HasStdExtZkt : Predicate<"Subtarget->hasStdExtZkt()">, + AssemblerPredicate<(all_of FeatureStdExtZkt), + "'Zkt' (Data Independent Execution Latency)">; + +def FeatureStdExtZk + : SubtargetFeature<"experimental-zk", "HasStdExtZk", "true", + "'Zk' (Standard scalar cryptography extension)", + [FeatureStdExtZkn, + FeatureStdExtZkr, + FeatureStdExtZkt]>; +def HasStdExtZk : Predicate<"Subtarget->hasStdExtZk()">, + AssemblerPredicate<(all_of FeatureStdExtZk), + "'Zk' (Standard scalar cryptography extension)">; + def FeatureNoRVCHints : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", "Disable RVC Hint Instructions.">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1461,5 +1461,6 @@ include "RISCVInstrInfoD.td" include "RISCVInstrInfoC.td" include "RISCVInstrInfoZb.td" +include "RISCVInstrInfoZk.td" include "RISCVInstrInfoV.td" include "RISCVInstrInfoZfh.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td @@ -0,0 +1,193 @@ +//===-- RISCVInstrInfoK.td - RISC-V 'K' instructions -------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the standard 'K', +// Cryptography Instructions extension, version 1.0-rc4. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Operand and SDNode transformation definitions. +//===----------------------------------------------------------------------===// + +def RnumArg : AsmOperandClass { + let Name = "RnumArg"; + let RenderMethod = "addImmOperands"; + let DiagnosticType = "InvalidRnumArg"; +} + +def rnum : Operand, ImmLeaf(Imm);}]> { + let ParserMatchClass = RnumArg; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeUImmOperand<4>"; + let OperandType = "OPERAND_UIMM4"; + let OperandNamespace = "RISCVOp"; +} + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVKShift_ri imm11_7, bits<3> funct3, RISCVOpcode opcode, + string opcodestr> + : RVInstIShift; + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVKShiftW_ri imm11_5, bits<3> funct3, RISCVOpcode opcode, + string opcodestr> + : RVInstIShiftW; + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVKUnary imm12_in, bits<3> funct3, string opcodestr> + : RVInstI, Sched<[]> { + let imm12 = imm12_in; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVKByteSelect funct5, string opcodestr> + : RVInstR<{0b00, funct5}, 0b000, OPC_OP, (outs GPR:$rd), + (ins GPR:$rs1, GPR:$rs2, uimm2:$bs), + opcodestr, "$rd, $rs1, $rs2, $bs">, Sched<[]> { + bits<2> bs; + let Inst{31-30} = bs; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVKUnary_rnum funct7, bits<3> funct3, string opcodestr> + : RVInstI, Sched<[]> { + bits<4> rnum; + let Inst{31-25} = funct7; + let Inst{24} = 1; + let Inst{23-20} = rnum; +} + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let DecoderNamespace = "RVK" in { +let Predicates = [HasStdExtZbkb] in { +def ROR_K : ALU_rr<0b0110000, 0b101, "ror">, + Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>; +def ROL_K : ALU_rr<0b0110000, 0b001, "rol">, + Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>; + +def RORI_K : RVKShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">, + Sched<[WriteRotateImm, ReadRotateImm]>; + +def ANDN_K : ALU_rr<0b0100000, 0b111, "andn">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; +def ORN_K : ALU_rr<0b0100000, 0b110, "orn">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; +def XNOR_K : ALU_rr<0b0100000, 0b100, "xnor">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + +def PACK_K : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>; +def PACKH_K : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>; + +def BREV8 : RVKUnary<0b011010000111, 0b101, "brev8">; +} // Predicates = [HasStdExtZbkb] + +let Predicates = [HasStdExtZbkb, IsRV32] in { +def REV8_RV32_K : RVKUnary<0b011010011000, 0b101, "rev8">; +def ZIP : RVKUnary<0b000010001111, 0b001, "zip">; +def UNZIP : RVKUnary<0b000010001111, 0b101, "unzip">; +} // Predicates = [HasStdExtZbkb, IsRV32] + +let Predicates = [HasStdExtZbkb, IsRV64] in { +def RORW_K : ALUW_rr<0b0110000, 0b101, "rorw">, + Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>; +def ROLW_K : ALUW_rr<0b0110000, 0b001, "rolw">, + Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>; + +def RORIW_K : RVKShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">, + Sched<[WriteRotateImm32, ReadRotateImm32]>; + +def PACKW_K : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>; + +def REV8_RV64_K : RVKUnary<0b011010111000, 0b101, "rev8">; +} // Predicates = [HasStdExtZbkb, IsRV64] + +let Predicates = [HasStdExtZbkc] in { +def CLMUL_K : ALU_rr<0b0000101, 0b001, "clmul">, Sched<[]>; +def CLMULH_K : ALU_rr<0b0000101, 0b011, "clmulh">, Sched<[]>; +} // Predicates = [HasStdExtZbkc] + +let Predicates = [HasStdExtZbkx] in { +def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>; +def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>; +} // Predicates = [HasStdExtZbkx] +} // DecoderNamespace = "RVK" + +let Predicates = [HasStdExtZknd, IsRV32] in { +def AES32DSI : RVKByteSelect<0b10101, "aes32dsi">; +def AES32DSMI : RVKByteSelect<0b10111, "aes32dsmi">; +} // Predicates = [HasStdExtZknd, IsRV32] + +let Predicates = [HasStdExtZknd, IsRV64] in { +def AES64DS : ALU_rr<0b0011101, 0b000, "aes64ds">, Sched<[]>; +def AES64DSM : ALU_rr<0b0011111, 0b000, "aes64dsm">, Sched<[]>; + +def AES64IM : RVKUnary<0b001100000000, 0b001, "aes64im">; +} // Predicates = [HasStdExtZknd, IsRV64] + +let Predicates = [HasStdExtZkndOrZkne, IsRV64] in { +def AES64KS2 : ALU_rr<0b0111111, 0b000, "aes64ks2">, Sched<[]>; + +def AES64KS1I : RVKUnary_rnum<0b0011000, 0b001, "aes64ks1i">; +} // Predicates = [HasStdExtZkndOrZkne, IsRV64] + +let Predicates = [HasStdExtZkne, IsRV32] in { +def AES32ESI : RVKByteSelect<0b10001, "aes32esi">; +def AES32ESMI : RVKByteSelect<0b10011, "aes32esmi">; +} // Predicates = [HasStdExtZkne, IsRV32] + +let Predicates = [HasStdExtZkne, IsRV64] in { +def AES64ES : ALU_rr<0b0011001, 0b000, "aes64es">; +def AES64ESM : ALU_rr<0b0011011, 0b000, "aes64esm">; +} // Predicates = [HasStdExtZkne, IsRV64] + +let Predicates = [HasStdExtZknh] in { +def SHA256SIG0 : RVKUnary<0b000100000010, 0b001, "sha256sig0">; +def SHA256SIG1 : RVKUnary<0b000100000011, 0b001, "sha256sig1">; +def SHA256SUM0 : RVKUnary<0b000100000000, 0b001, "sha256sum0">; +def SHA256SUM1 : RVKUnary<0b000100000001, 0b001, "sha256sum1">; +} // Predicates = [HasStdExtZknh] + +let Predicates = [HasStdExtZknh, IsRV32] in { +def SHA512SIG0H : ALU_rr<0b0101110, 0b000, "sha512sig0h">; +def SHA512SIG0L : ALU_rr<0b0101010, 0b000, "sha512sig0l">; +def SHA512SIG1H : ALU_rr<0b0101111, 0b000, "sha512sig1h">; +def SHA512SIG1L : ALU_rr<0b0101011, 0b000, "sha512sig1l">; +def SHA512SUM0R : ALU_rr<0b0101000, 0b000, "sha512sum0r">; +def SHA512SUM1R : ALU_rr<0b0101001, 0b000, "sha512sum1r">; +} // [HasStdExtZknh, IsRV32] + +let Predicates = [HasStdExtZknh, IsRV64] in { +def SHA512SIG0 : RVKUnary<0b000100000110, 0b001, "sha512sig0">; +def SHA512SIG1 : RVKUnary<0b000100000111, 0b001, "sha512sig1">; +def SHA512SUM0 : RVKUnary<0b000100000100, 0b001, "sha512sum0">; +def SHA512SUM1 : RVKUnary<0b000100000101, 0b001, "sha512sum1">; +} // Predicates = [HasStdExtZknh, IsRV64] + +let Predicates = [HasStdExtZksed] in { +def SM4ED : RVKByteSelect<0b11000, "sm4ed">; +def SM4KS : RVKByteSelect<0b11010, "sm4ks">; +} // Predicates = [HasStdExtZksed] + +let Predicates = [HasStdExtZksh] in { +def SM3P0 : RVKUnary<0b000100001000, 0b001, "sm3p0">; +def SM3P1 : RVKUnary<0b000100001001, 0b001, "sm3p1">; +} // Predicates = [HasStdExtZksh] diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td --- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -16,7 +16,12 @@ let IssueWidth = 1; // 1 micro-op is dispatched per cycle. let LoadLatency = 3; let MispredictPenalty = 3; - let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg]; + let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, + HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, + HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, + HasStdExtZkn, HasStdExtZks, HasStdExtZkt, + HasStdExtZk, HasStdExtV, HasStdExtZvamo, + HasStdExtZvlsseg]; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -15,7 +15,12 @@ let LoadLatency = 3; let MispredictPenalty = 3; let CompleteModel = 0; - let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg]; + let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, + HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, + HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, + HasStdExtZkn, HasStdExtZks, HasStdExtZkt, + HasStdExtZk, HasStdExtV, HasStdExtZvamo, + HasStdExtZvlsseg]; } // The SiFive7 microarchitecture has two pipelines: A and B. diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -49,6 +49,19 @@ bool HasStdExtZbr = false; bool HasStdExtZbs = false; bool HasStdExtZbt = false; + bool HasStdExtZbkb = false; + bool HasStdExtZbkc = false; + bool HasStdExtZbkx = false; + bool HasStdExtZknd = false; + bool HasStdExtZkne = false; + bool HasStdExtZknh = false; + bool HasStdExtZksed = false; + bool HasStdExtZksh = false; + bool HasStdExtZkr = false; + bool HasStdExtZkn = false; + bool HasStdExtZks = false; + bool HasStdExtZkt = false; + bool HasStdExtZk = false; bool HasStdExtV = false; bool HasStdExtZvlsseg = false; bool HasStdExtZvamo = false; @@ -115,6 +128,19 @@ bool hasStdExtZbr() const { return HasStdExtZbr; } bool hasStdExtZbs() const { return HasStdExtZbs; } bool hasStdExtZbt() const { return HasStdExtZbt; } + bool hasStdExtZbkb() const { return HasStdExtZbkb; } + bool hasStdExtZbkc() const { return HasStdExtZbkc; } + bool hasStdExtZbkx() const { return HasStdExtZbkx; } + bool hasStdExtZknd() const { return HasStdExtZknd; } + bool hasStdExtZkne() const { return HasStdExtZkne; } + bool hasStdExtZknh() const { return HasStdExtZknh; } + bool hasStdExtZksed() const { return HasStdExtZksed; } + bool hasStdExtZksh() const { return HasStdExtZksh; } + bool hasStdExtZkr() const { return HasStdExtZkr; } + bool hasStdExtZkn() const { return HasStdExtZkn; } + bool hasStdExtZks() const { return HasStdExtZks; } + bool hasStdExtZkt() const { return HasStdExtZkt; } + bool hasStdExtZk() const { return HasStdExtZk; } bool hasStdExtV() const { return HasStdExtV; } bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; } bool hasStdExtZvamo() const { return HasStdExtZvamo; } diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -388,3 +388,9 @@ def : SysReg<"vl", 0xC20>; def : SysReg<"vtype", 0xC21>; def : SysReg<"vlenb", 0xC22>; + +//===----------------------------------------------- +// Machine Scalar Cryptography CSRs +//===----------------------------------------------- +def MENTROPY : SysReg<"mentropy", 0xF15>; +def MNOISE : SysReg<"mnoise", 0x7A9>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -17,6 +17,19 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbkb %s -o - | FileCheck --check-prefix=RV32ZBKB %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbkc %s -o - | FileCheck --check-prefix=RV32ZBKC %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbkx %s -o - | FileCheck --check-prefix=RV32ZBKX %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zknd %s -o - | FileCheck --check-prefix=RV32ZKND %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zkne %s -o - | FileCheck --check-prefix=RV32ZKNE %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zknh %s -o - | FileCheck --check-prefix=RV32ZKNH %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zksed %s -o - | FileCheck --check-prefix=RV32ZKSED %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zksh %s -o - | FileCheck --check-prefix=RV32ZKSH %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zkr %s -o - | FileCheck --check-prefix=RV32ZKR %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zkn %s -o - | FileCheck --check-prefix=RV32ZKN %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zks %s -o - | FileCheck --check-prefix=RV32ZKS %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zkt %s -o - | FileCheck --check-prefix=RV32ZKT %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zk %s -o - | FileCheck --check-prefix=RV32ZK %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s @@ -35,6 +48,19 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbkb %s -o - | FileCheck --check-prefix=RV64ZBKB %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbkc %s -o - | FileCheck --check-prefix=RV64ZBKC %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbkx %s -o - | FileCheck --check-prefix=RV64ZBKX %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zknd %s -o - | FileCheck --check-prefix=RV64ZKND %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zkne %s -o - | FileCheck --check-prefix=RV64ZKNE %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zknh %s -o - | FileCheck --check-prefix=RV64ZKNH %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zksed %s -o - | FileCheck --check-prefix=RV64ZKSED %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zksh %s -o - | FileCheck --check-prefix=RV64ZKSH %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zkr %s -o - | FileCheck --check-prefix=RV64ZKR %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zkn %s -o - | FileCheck --check-prefix=RV64ZKN %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zks %s -o - | FileCheck --check-prefix=RV64ZKS %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zkt %s -o - | FileCheck --check-prefix=RV64ZKT %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zk %s -o - | FileCheck --check-prefix=RV64ZK %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s ; RV32M: .attribute 5, "rv32i2p0_m2p0" @@ -54,6 +80,19 @@ ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93" ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0" ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93" +; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0" +; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0" +; RV32ZBKX: .attribute 5, "rv32i2p0_zbkx1p0" +; RV32ZKND: .attribute 5, "rv32i2p0_zknd1p0" +; RV32ZKNE: .attribute 5, "rv32i2p0_zkne1p0" +; RV32ZKNH: .attribute 5, "rv32i2p0_zknh1p0" +; RV32ZKSED: .attribute 5, "rv32i2p0_zksed1p0" +; RV32ZKSH: .attribute 5, "rv32i2p0_zksh1p0" +; RV32ZKR: .attribute 5, "rv32i2p0_zkr1p0" +; RV32ZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0" +; RV32ZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0" +; RV32ZKT: .attribute 5, "rv32i2p0_zkt1p0" +; RV32ZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0" ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10" ; RV64M: .attribute 5, "rv64i2p0_m2p0" @@ -72,6 +111,19 @@ ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93" ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0" ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93" +; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0" +; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0" +; RV64ZBKX: .attribute 5, "rv64i2p0_zbkx1p0" +; RV64ZKND: .attribute 5, "rv64i2p0_zknd1p0" +; RV64ZKNE: .attribute 5, "rv64i2p0_zkne1p0" +; RV64ZKNH: .attribute 5, "rv64i2p0_zknh1p0" +; RV64ZKSED: .attribute 5, "rv64i2p0_zksed1p0" +; RV64ZKSH: .attribute 5, "rv64i2p0_zksh1p0" +; RV64ZKR: .attribute 5, "rv64i2p0_zkr1p0" +; RV64ZKN: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0" +; RV64ZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0" +; RV64ZKT: .attribute 5, "rv64i2p0_zkt1p0" +; RV64ZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0" ; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10" ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -66,6 +66,45 @@ .attribute arch, "rv32izbt" # CHECK: attribute 5, "rv32i2p0_zbt0p93" +.attribute arch, "rv32i_zbkb1p0" +# CHECK: attribute 5, "rv32i2p0_zbkb1p0" + +.attribute arch, "rv32i_zbkc1p0" +# CHECK: attribute 5, "rv32i2p0_zbkc1p0" + +.attribute arch, "rv32i_zbkx1p0" +# CHECK: attribute 5, "rv32i2p0_zbkx1p0" + +.attribute arch, "rv32i_zknd1p0" +# CHECK: attribute 5, "rv32i2p0_zknd1p0" + +.attribute arch, "rv32i_zkne1p0" +# CHECK: attribute 5, "rv32i2p0_zkne1p0" + +.attribute arch, "rv32i_zknh1p0" +# CHECK: attribute 5, "rv32i2p0_zknh1p0" + +.attribute arch, "rv32i_zksed1p0" +# CHECK: attribute 5, "rv32i2p0_zksed1p0" + +.attribute arch, "rv32i_zksh1p0" +# CHECK: attribute 5, "rv32i2p0_zksh1p0" + +.attribute arch, "rv32i_zkr1p0" +# CHECK: attribute 5, "rv32i2p0_zkr1p0" + +.attribute arch, "rv32i_zkn1p0" +# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0" + +.attribute arch, "rv32i_zks1p0" +# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0" + +.attribute arch, "rv32i_zkt1p0" +# CHECK: attribute 5, "rv32i2p0_zkt1p0" + +.attribute arch, "rv32i_zk1p0" +# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0" + .attribute arch, "rv32ifzfh" # CHECK: attribute 5, "rv32i2p0_f2p0_zfh0p1" diff --git a/llvm/test/MC/RISCV/rv32zbkb-only-valid.s b/llvm/test/MC/RISCV/rv32zbkb-only-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zbkb-only-valid.s @@ -0,0 +1,16 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbkb -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbkb < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zbkb -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: rev8 t0, t1 +# CHECK-ASM: encoding: [0x93,0x52,0x83,0x69] +rev8 t0, t1 + +# CHECK-ASM-AND-OBJ: zip t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0xf3,0x08] +zip t0, t1 +# CHECK-S-OBJ-NOALIAS: unzip t0, t1 +# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x08] +unzip t0, t1 diff --git a/llvm/test/MC/RISCV/rv32zbkb-valid.s b/llvm/test/MC/RISCV/rv32zbkb-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zbkb-valid.s @@ -0,0 +1,45 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbkb -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbkb -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbkb < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zbkb -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbkb < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zbkb -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: ror t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60] +ror t0, t1, t2 +# CHECK-ASM-AND-OBJ: rol t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x60] +rol t0, t1, t2 +# CHECK-ASM-AND-OBJ: rori t0, t1, 31 +# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61] +rori t0, t1, 31 +# CHECK-ASM-AND-OBJ: rori t0, t1, 0 +# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60] +rori t0, t1, 0 + +# CHECK-ASM-AND-OBJ: andn t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x40] +andn t0, t1, t2 +# CHECK-ASM-AND-OBJ: orn t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x40] +orn t0, t1, t2 +# CHECK-ASM-AND-OBJ: xnor t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x40] +xnor t0, t1, t2 + +# CHECK-ASM: pack t0, t1, zero +# CHECK-OBJ: zext.h t0, t1 +# CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08] +pack t0, t1, x0 +# CHECK-ASM-AND-OBJ: packh t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x08] +packh t0, t1, t2 + +# CHECK-ASM-AND-OBJ: brev8 t0, t1 +# CHECK-ASM: encoding: [0x93,0x52,0x73,0x68] +brev8 t0, t1 diff --git a/llvm/test/MC/RISCV/rv32zbkc-valid.s b/llvm/test/MC/RISCV/rv32zbkc-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zbkc-valid.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbkc -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbkc -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbkc < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zbkc -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbkc < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zbkc -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: clmul t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x0a] +clmul t0, t1, t2 +# CHECK-ASM-AND-OBJ: clmulh t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x0a] +clmulh t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv32zbkx-valid.s b/llvm/test/MC/RISCV/rv32zbkx-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zbkx-valid.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbkx -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbkx -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbkx < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zbkx -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbkx < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zbkx -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: xperm8 t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x28] +xperm8 t0, t1, t2 +# CHECK-ASM-AND-OBJ: xperm4 t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x28] +xperm4 t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv32zknd-only-invalid.s b/llvm/test/MC/RISCV/rv32zknd-only-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zknd-only-invalid.s @@ -0,0 +1,17 @@ +# With Zk extension: +# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-zk < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# With Zkn extension: +# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-zkn < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# With Zknd extension: +# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-zknd < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# CHECK-ERROR: immediate must be an integer in the range [0, 3] +aes32dsmi a0, a1, a2, 8 + +# CHECK-ERROR: immediate must be an integer in the range [0, 3] +aes32dsi a0, a1, a2, 8 diff --git a/llvm/test/MC/RISCV/rv32zknd-only-valid.s b/llvm/test/MC/RISCV/rv32zknd-only-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zknd-only-valid.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zknd -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zknd < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zknd -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: aes32dsi a0, a1, a2, 3 +# CHECK-ASM: [0x33,0x85,0xc5,0xea] +aes32dsi a0, a1, a2, 3 + +# CHECK-ASM-AND-OBJ: aes32dsmi a0, a1, a2, 3 +# CHECK-ASM: [0x33,0x85,0xc5,0xee] +aes32dsmi a0, a1, a2, 3 diff --git a/llvm/test/MC/RISCV/rv32zkne-only-invalid.s b/llvm/test/MC/RISCV/rv32zkne-only-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zkne-only-invalid.s @@ -0,0 +1,17 @@ +# With Zk extension: +# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-zk < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# With Zkn extension: +# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-zkn < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# With Zkne extension: +# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-zkne < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# CHECK-ERROR: immediate must be an integer in the range [0, 3] +aes32esmi a0, a1, a2, 8 + +# CHECK-ERROR: immediate must be an integer in the range [0, 3] +aes32esi a0, a1, a2, 8 diff --git a/llvm/test/MC/RISCV/rv32zkne-only-valid.s b/llvm/test/MC/RISCV/rv32zkne-only-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zkne-only-valid.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zkne -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zkne < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zkne -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: aes32esi a0, a1, a2, 3 +# CHECK-ASM: [0x33,0x85,0xc5,0xe2] +aes32esi a0, a1, a2, 3 + +# CHECK-ASM-AND-OBJ: aes32esmi a0, a1, a2, 3 +# CHECK-ASM: [0x33,0x85,0xc5,0xe6] +aes32esmi a0, a1, a2, 3 diff --git a/llvm/test/MC/RISCV/rv32zknh-only-valid.s b/llvm/test/MC/RISCV/rv32zknh-only-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zknh-only-valid.s @@ -0,0 +1,29 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zknh -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zknh < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zknh -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: sha512sig0h a0, a1, a2 +# CHECK-ASM: [0x33,0x85,0xc5,0x5c] +sha512sig0h a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sha512sig1h a0, a1, a2 +# CHECK-ASM: [0x33,0x85,0xc5,0x5e] +sha512sig1h a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sha512sig0l a0, a1, a2 +# CHECK-ASM: [0x33,0x85,0xc5,0x54] +sha512sig0l a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sha512sig1l a0, a1, a2 +# CHECK-ASM: [0x33,0x85,0xc5,0x56] +sha512sig1l a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sha512sum0r a0, a1, a2 +# CHECK-ASM: [0x33,0x85,0xc5,0x50] +sha512sum0r a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sha512sum1r a0, a1, a2 +# CHECK-ASM: [0x33,0x85,0xc5,0x52] +sha512sum1r a0, a1, a2 diff --git a/llvm/test/MC/RISCV/rv32zknh-valid.s b/llvm/test/MC/RISCV/rv32zknh-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zknh-valid.s @@ -0,0 +1,26 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zknh -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zknh -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zknh < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zknh -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zknh < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zknh -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: sha256sig0 a0, a1 +# CHECK-ASM: [0x13,0x95,0x25,0x10] +sha256sig0 a0, a1 + +# CHECK-ASM-AND-OBJ: sha256sig1 a0, a1 +# CHECK-ASM: [0x13,0x95,0x35,0x10] +sha256sig1 a0, a1 + +# CHECK-ASM-AND-OBJ: sha256sum0 a0, a1 +# CHECK-ASM: [0x13,0x95,0x05,0x10] +sha256sum0 a0, a1 + +# CHECK-ASM-AND-OBJ: sha256sum1 a0, a1 +# CHECK-ASM: [0x13,0x95,0x15,0x10] +sha256sum1 a0, a1 diff --git a/llvm/test/MC/RISCV/rv32zksed-invalid.s b/llvm/test/MC/RISCV/rv32zksed-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zksed-invalid.s @@ -0,0 +1,13 @@ +# With Zks extension: +# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-zks < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# With Zksed extension: +# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-zksed < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# CHECK-ERROR: immediate must be an integer in the range [0, 3] +sm4ed a0, a1, a2, 8 + +# CHECK-ERROR: immediate must be an integer in the range [0, 3] +sm4ks a0, a1, a2, 8 diff --git a/llvm/test/MC/RISCV/rv32zksed-valid.s b/llvm/test/MC/RISCV/rv32zksed-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zksed-valid.s @@ -0,0 +1,18 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zksed -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zksed -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zksed < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zksed -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zksed < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zksed -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: sm4ed a0, a1, a2, 3 +# CHECK-ASM: [0x33,0x85,0xc5,0xf0] +sm4ed a0, a1, a2, 3 + +# CHECK-ASM-AND-OBJ: sm4ks a0, a1, a2, 3 +# CHECK-ASM: [0x33,0x85,0xc5,0xf4] +sm4ks a0, a1, a2, 3 diff --git a/llvm/test/MC/RISCV/rv32zksh-valid.s b/llvm/test/MC/RISCV/rv32zksh-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zksh-valid.s @@ -0,0 +1,18 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zksh -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zksh -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zksh < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zksh -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zksh < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zksh -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: sm3p0 a0, a1 +# CHECK-ASM: [0x13,0x95,0x85,0x10] +sm3p0 a0, a1 + +# CHECK-ASM-AND-OBJ: sm3p1 a0, a1 +# CHECK-ASM: [0x13,0x95,0x95,0x10] +sm3p1 a0, a1 diff --git a/llvm/test/MC/RISCV/rv64-zbkb-valid.s b/llvm/test/MC/RISCV/rv64-zbkb-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64-zbkb-valid.s @@ -0,0 +1,22 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbkb -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbkb < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zbkb -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: rorw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60] +rorw t0, t1, t2 +# CHECK-ASM-AND-OBJ: rolw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x60] +rolw t0, t1, t2 +# CHECK-ASM-AND-OBJ: roriw t0, t1, 31 +# CHECK-ASM: encoding: [0x9b,0x52,0xf3,0x61] +roriw t0, t1, 31 +# CHECK-ASM-AND-OBJ: roriw t0, t1, 0 +# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x60] +roriw t0, t1, 0 + +# CHECK-ASM-AND-OBJ: packw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x08] +packw t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64zbkb-only-valid.s b/llvm/test/MC/RISCV/rv64zbkb-only-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zbkb-only-valid.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbkb -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbkb < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zbkb -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: rev8 t0, t1 +# CHECK-ASM: encoding: [0x93,0x52,0x83,0x6b] +rev8 t0, t1 diff --git a/llvm/test/MC/RISCV/rv64zknd-only-valid.s b/llvm/test/MC/RISCV/rv64zknd-only-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zknd-only-valid.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zknd -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zknd < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zknd -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: aes64ds a0, a1, a2 +# CHECK-ASM: [0x33,0x85,0xc5,0x3a] +aes64ds a0, a1, a2 + +# CHECK-ASM-AND-OBJ: aes64dsm a0, a1, a2 +# CHECK-ASM: [0x33,0x85,0xc5,0x3e] +aes64dsm a0, a1, a2 + +# CHECK-ASM-AND-OBJ: aes64im a0, a1 +# CHECK-ASM: [0x13,0x95,0x05,0x30] +aes64im a0, a1 + +# CHECK-ASM-AND-OBJ: aes64ks1i a0, a1, 5 +# CHECK-ASM: [0x13,0x95,0x55,0x31] +aes64ks1i a0, a1, 5 + +# CHECK-ASM-AND-OBJ: aes64ks2 a0, a1, a2 +# CHECK-ASM: [0x33,0x85,0xc5,0x7e] +aes64ks2 a0, a1, a2 diff --git a/llvm/test/MC/RISCV/rv64zkne-only-invalid.s b/llvm/test/MC/RISCV/rv64zkne-only-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zkne-only-invalid.s @@ -0,0 +1,17 @@ +# With Zk extension: +# RUN: not llvm-mc -triple=riscv64 -mattr=+experimental-zk < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# With Zkn extension: +# RUN: not llvm-mc -triple=riscv64 -mattr=+experimental-zkn < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# With Zkne extension: +# RUN: not llvm-mc -triple=riscv64 -mattr=+experimental-zkne < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# CHECK-ERROR: immediate must be an integer in the range [0, 10] +aes64ks1i a0, a1, 11 + +# CHECK-ERROR: immediate must be an integer in the range [0, 10] +aes64ks1i a0, a1, -1 diff --git a/llvm/test/MC/RISCV/rv64zkne-only-valid.s b/llvm/test/MC/RISCV/rv64zkne-only-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zkne-only-valid.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zkne -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zkne < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zkne -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: aes64es a0, a1, a2 +# CHECK-ASM: [0x33,0x85,0xc5,0x32] +aes64es a0, a1, a2 + +# CHECK-ASM-AND-OBJ: aes64esm a0, a1, a2 +# CHECK-ASM: [0x33,0x85,0xc5,0x36] +aes64esm a0, a1, a2 + +# CHECK-ASM-AND-OBJ: aes64ks1i a0, a1, 5 +# CHECK-ASM: [0x13,0x95,0x55,0x31] +aes64ks1i a0, a1, 5 + +# CHECK-ASM-AND-OBJ: aes64ks2 a0, a1, a2 +# CHECK-ASM: [0x33,0x85,0xc5,0x7e] +aes64ks2 a0, a1, a2 diff --git a/llvm/test/MC/RISCV/rv64zknh-only-valid.s b/llvm/test/MC/RISCV/rv64zknh-only-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zknh-only-valid.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zknh -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zknh < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zknh -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: sha512sig0 a0, a1 +# CHECK-ASM: [0x13,0x95,0x65,0x10] +sha512sig0 a0, a1 + +# CHECK-ASM-AND-OBJ: sha512sig1 a0, a1 +# CHECK-ASM: [0x13,0x95,0x75,0x10] +sha512sig1 a0, a1 + +# CHECK-ASM-AND-OBJ: sha512sum0 a0, a1 +# CHECK-ASM: [0x13,0x95,0x45,0x10] +sha512sum0 a0, a1 + +# CHECK-ASM-AND-OBJ: sha512sum1 a0, a1 +# CHECK-ASM: [0x13,0x95,0x55,0x10] +sha512sum1 a0, a1 diff --git a/llvm/test/MC/RISCV/rv64zksed-invalid.s b/llvm/test/MC/RISCV/rv64zksed-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zksed-invalid.s @@ -0,0 +1,13 @@ +# With Zks extension: +# RUN: not llvm-mc -triple=riscv64 -mattr=+experimental-zks < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# With Zksed extension: +# RUN: not llvm-mc -triple=riscv64 -mattr=+experimental-zksed < %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +sm4ed a0, a1, a2, 8 +# CHECK-ERROR: immediate must be an integer in the range [0, 3] + +sm4ks a0, a1, a2, 8 +# CHECK-ERROR: immediate must be an integer in the range [0, 3]