[RISCV] Call SelectBaseAddr on the base pointer in the custom isel for vector loads and stores.

[craig.topper]

Summary

This will allow FrameIndex as the base address instead of
emitting a separate ADDI from isel. eliminateFrameIndex will likely turn
it back into an ADDI, but this makes things consistent with the
SDPatterns and VLPatterns.

I only tested one case for simplicity. I can test more if reviewers
want.

[frasercrmck]

LGTM.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, bool IsMasked,
   SmallVector<SDValue, 7> Operands;
   if (IsMasked) {
     SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp,
                                  Node->op_begin() + CurOp + NF);
     SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL);
     Operands.push_back(MaskedOff);
     CurOp += NF;
   }
-  Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
+  SDValue Base;
+  SelectBaseAddr(Node->getOperand(CurOp++), Base);
+  Operands.push_back(Base); // Base pointer.
   if (IsStrided)
     Operands.push_back(Node->getOperand(CurOp++)); // Stride.
   if (IsMasked)
     Operands.push_back(Node->getOperand(CurOp++)); // Mask.
   SDValue VL;
   selectVLOp(Node->getOperand(CurOp++), VL);
   Operands.push_back(VL);
   Operands.push_back(SEW);
void RISCVDAGToDAGISel::selectVLSEGFF(SDNode *Node, bool IsMasked) {
   SmallVector<SDValue, 7> Operands;
   if (IsMasked) {
     SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp,
                                  Node->op_begin() + CurOp + NF);
     SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL);
     Operands.push_back(MaskedOff);
     CurOp += NF;
   }
-  Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
+  SDValue Base;
+  SelectBaseAddr(Node->getOperand(CurOp++), Base);
+  Operands.push_back(Base); // Base pointer.
   if (IsMasked)
     Operands.push_back(Node->getOperand(CurOp++)); // Mask.
   SDValue VL;
   selectVLOp(Node->getOperand(CurOp++), VL);
   Operands.push_back(VL);
   Operands.push_back(SEW);
   Operands.push_back(Node->getOperand(0)); // Chain.
   const RISCV::VLSEGPseudo *P =
void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, bool IsMasked,
   SmallVector<SDValue, 7> Operands;
   if (IsMasked) {
     SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp,
                                  Node->op_begin() + CurOp + NF);
     SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL);
     Operands.push_back(MaskedOff);
     CurOp += NF;
   }
-  Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
+  SDValue Base;
+  SelectBaseAddr(Node->getOperand(CurOp++), Base);
+  Operands.push_back(Base); // Base pointer.
   Operands.push_back(Node->getOperand(CurOp++)); // Index.
   MVT IndexVT = Operands.back()->getSimpleValueType(0);
   if (IsMasked)
     Operands.push_back(Node->getOperand(CurOp++)); // Mask.
   SDValue VL;
   selectVLOp(Node->getOperand(CurOp++), VL);
   Operands.push_back(VL);
   Operands.push_back(SEW);
void RISCVDAGToDAGISel::selectVSSEG(SDNode *Node, bool IsMasked,
   MVT XLenVT = Subtarget->getXLenVT();
   RISCVVLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
   SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
   SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF);
   SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL);
   SmallVector<SDValue, 7> Operands;
   Operands.push_back(StoreVal);
   unsigned CurOp = 2 + NF;
-  Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
+  SDValue Base;
+  SelectBaseAddr(Node->getOperand(CurOp++), Base);
+  Operands.push_back(Base); // Base pointer.
   if (IsStrided)
     Operands.push_back(Node->getOperand(CurOp++)); // Stride.
   if (IsMasked)
     Operands.push_back(Node->getOperand(CurOp++)); // Mask.
   SDValue VL;
   selectVLOp(Node->getOperand(CurOp++), VL);
   Operands.push_back(VL);
   Operands.push_back(SEW);
void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, bool IsMasked,
   MVT XLenVT = Subtarget->getXLenVT();
   RISCVVLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
   SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
   SmallVector<SDValue, 7> Operands;
   SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF);
   SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL);
   Operands.push_back(StoreVal);
   unsigned CurOp = 2 + NF;
-  Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
+  SDValue Base;
+  SelectBaseAddr(Node->getOperand(CurOp++), Base);
+  Operands.push_back(Base); // Base pointer.
   Operands.push_back(Node->getOperand(CurOp++)); // Index.
   MVT IndexVT = Operands.back()->getSimpleValueType(0);
   if (IsMasked)
     Operands.push_back(Node->getOperand(CurOp++)); // Mask.
   SDValue VL;
   selectVLOp(Node->getOperand(CurOp++), VL);
   Operands.push_back(VL);
   Operands.push_back(SEW);
case Intrinsic::riscv_vluxei_mask: {
       unsigned ScalarSize = VT.getScalarSizeInBits();
       MVT XLenVT = Subtarget->getXLenVT();
       SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
 
       unsigned CurOp = 2;
       SmallVector<SDValue, 7> Operands;
       if (IsMasked)
         Operands.push_back(Node->getOperand(CurOp++));
-      Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
+      SDValue Base;
+      SelectBaseAddr(Node->getOperand(CurOp++), Base);
+      Operands.push_back(Base); // Base pointer.
       Operands.push_back(Node->getOperand(CurOp++)); // Index.
       MVT IndexVT = Operands.back()->getSimpleValueType(0);
       if (IsMasked)
         Operands.push_back(Node->getOperand(CurOp++)); // Mask.
       SDValue VL;
       selectVLOp(Node->getOperand(CurOp++), VL);
       Operands.push_back(VL);
       Operands.push_back(SEW);
case Intrinsic::riscv_vlse_mask: {
       // VLE1 uses an SEW of 8.
       unsigned SEWImm = (IntNo == Intrinsic::riscv_vle1) ? 8 : ScalarSize;
       SDValue SEW = CurDAG->getTargetConstant(SEWImm, DL, XLenVT);
 
       unsigned CurOp = 2;
       SmallVector<SDValue, 7> Operands;
       if (IsMasked)
         Operands.push_back(Node->getOperand(CurOp++));
-      Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
+      SDValue Base;
+      SelectBaseAddr(Node->getOperand(CurOp++), Base);
+      Operands.push_back(Base); // Base pointer.
       if (IsStrided)
         Operands.push_back(Node->getOperand(CurOp++)); // Stride.
       if (IsMasked)
         Operands.push_back(Node->getOperand(CurOp++)); // Mask.
       SDValue VL;
       selectVLOp(Node->getOperand(CurOp++), VL);
       Operands.push_back(VL);
       Operands.push_back(SEW);
case Intrinsic::riscv_vleff_mask: {
       unsigned ScalarSize = VT.getScalarSizeInBits();
       MVT XLenVT = Subtarget->getXLenVT();
       SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
 
       unsigned CurOp = 2;
       SmallVector<SDValue, 7> Operands;
       if (IsMasked)
         Operands.push_back(Node->getOperand(CurOp++));
-      Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
+      SDValue Base;
+      SelectBaseAddr(Node->getOperand(CurOp++), Base);
+      Operands.push_back(Base); // Base pointer.
       if (IsMasked)
         Operands.push_back(Node->getOperand(CurOp++)); // Mask.
       SDValue VL;
       selectVLOp(Node->getOperand(CurOp++), VL);
       Operands.push_back(VL);
       Operands.push_back(SEW);
       Operands.push_back(Node->getOperand(0)); // Chain.
 
case Intrinsic::riscv_vsuxei_mask: {
       MVT VT = Node->getOperand(2)->getSimpleValueType(0);
       unsigned ScalarSize = VT.getScalarSizeInBits();
       MVT XLenVT = Subtarget->getXLenVT();
       SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
 
       unsigned CurOp = 2;
       SmallVector<SDValue, 6> Operands;
       Operands.push_back(Node->getOperand(CurOp++)); // Store value.
-      Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
+      SDValue Base;
+      SelectBaseAddr(Node->getOperand(CurOp++), Base);
+      Operands.push_back(Base); // Base pointer.
       Operands.push_back(Node->getOperand(CurOp++)); // Index.
       MVT IndexVT = Operands.back()->getSimpleValueType(0);
       if (IsMasked)
         Operands.push_back(Node->getOperand(CurOp++)); // Mask.
       SDValue VL;
       selectVLOp(Node->getOperand(CurOp++), VL);
       Operands.push_back(VL);
       Operands.push_back(SEW);
case Intrinsic::riscv_vsse_mask: {
       MVT XLenVT = Subtarget->getXLenVT();
       // VSE1 uses an SEW of 8.
       unsigned SEWImm = (IntNo == Intrinsic::riscv_vse1) ? 8 : ScalarSize;
       SDValue SEW = CurDAG->getTargetConstant(SEWImm, DL, XLenVT);
 
       unsigned CurOp = 2;
       SmallVector<SDValue, 6> Operands;
       Operands.push_back(Node->getOperand(CurOp++)); // Store value.
-      Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
+      SDValue Base;
+      SelectBaseAddr(Node->getOperand(CurOp++), Base);
+      Operands.push_back(Base); // Base pointer.
       if (IsStrided)
         Operands.push_back(Node->getOperand(CurOp++)); // Stride.
       if (IsMasked)
         Operands.push_back(Node->getOperand(CurOp++)); // Mask.
       SDValue VL;
       selectVLOp(Node->getOperand(CurOp++), VL);
       Operands.push_back(VL);
       Operands.push_back(SEW);

llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -stop-after=finalize-isel < %s | FileCheck %s
+
+; This test makes sure we match FrameIndex into the base address.
+; Done as a MIR test because eliminateFrameIndex will likely turn it
+; back into an addi.
+
+declare void @llvm.riscv.vse.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>*,
+  i64);
+
+define i64 @test(<vscale x 1 x i64> %0) nounwind {
+  ; CHECK-LABEL: name: test
+  ; CHECK: bb.0.entry:
+  ; CHECK:   liveins: $v8
+  ; CHECK:   [[COPY:%[0-9]+]]:vr = COPY $v8
+  ; CHECK:   [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
+  ; CHECK:   dead %3:gpr = PseudoVSETIVLI 1, 88, implicit-def $vl, implicit-def $vtype
+  ; CHECK:   PseudoVSE64_V_M1 [[COPY]], %stack.0.a, $noreg, -1, implicit $vl, implicit $vtype
+  ; CHECK:   [[LD:%[0-9]+]]:gpr = LD %stack.0.a, 0 :: (dereferenceable load 8 from %ir.a)
+  ; CHECK:   $x10 = COPY [[LD]]
+  ; CHECK:   PseudoRET implicit $x10
+entry:
+  %a = alloca i64
+  %b = bitcast i64* %a to <vscale x 1 x i64>*
+  call void @llvm.riscv.vse.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64>* %b,
+    i64 1)
+  %c = load i64, i64* %a
+  ret i64 %c
+}