Index: llvm/lib/Target/ARM/ARMInstrMVE.td =================================================================== --- llvm/lib/Target/ARM/ARMInstrMVE.td +++ llvm/lib/Target/ARM/ARMInstrMVE.td @@ -6231,11 +6231,7 @@ def _post : MVE_VLDRSTR_cs< dir, memsz, 0, 1, !con((outs rGPR:$wb), dir.Oops), - // We need an !if here to select the base register class, - // because it's legal to write back to SP in a load of this - // type, but not in a store. - !con(dir.Iops, (ins !if(dir.load, t2_addr_offset_none, - t2_nosp_addr_offset_none):$Rn, + !con(dir.Iops, (ins t2_nosp_addr_offset_none:$Rn, t2am_imm7_offset:$addr)), asm, suffix, IndexModePost, "$Qd, $Rn$addr", "$Rn.base = $wb"> { bits<4> Rn; Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/count_dominates_start.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/count_dominates_start.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/count_dominates_start.mir @@ -62,8 +62,8 @@ registers: - { id: 0, class: rgpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } - - { id: 2, class: gprnopc, preferred-register: '' } - - { id: 3, class: gprnopc, preferred-register: '' } + - { id: 2, class: rgpr, preferred-register: '' } + - { id: 3, class: rgpr, preferred-register: '' } - { id: 4, class: tgpreven, preferred-register: '' } - { id: 5, class: gprlr, preferred-register: '' } - { id: 6, class: rgpr, preferred-register: '' } @@ -129,8 +129,8 @@ ; CHECK: [[t2DoLoopStartTP:%[0-9]+]]:gprlr = t2DoLoopStartTP [[COPY4]], [[COPY6]] ; CHECK: bb.3.vector.body: ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) - ; CHECK: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY2]], %bb.2, %10, %bb.3 - ; CHECK: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY1]], %bb.2, %9, %bb.3 + ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.2, %10, %bb.3 + ; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.2, %9, %bb.3 ; CHECK: [[PHI2:%[0-9]+]]:tgpreven = PHI [[COPY5]], %bb.2, %8, %bb.3 ; CHECK: [[PHI3:%[0-9]+]]:gprlr = PHI [[t2DoLoopStartTP]], %bb.2, %33, %bb.3 ; CHECK: [[PHI4:%[0-9]+]]:rgpr = PHI [[COPY6]], %bb.2, %7, %bb.3 @@ -184,8 +184,8 @@ bb.2.vector.body: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - %2:gprnopc = PHI %13, %bb.1, %10, %bb.2 - %3:gprnopc = PHI %14, %bb.1, %9, %bb.2 + %2:rgpr = PHI %13, %bb.1, %10, %bb.2 + %3:rgpr = PHI %14, %bb.1, %9, %bb.2 %4:tgpreven = PHI %23, %bb.1, %8, %bb.2 %5:gprlr = PHI %1, %bb.1, %11, %bb.2 %6:rgpr = PHI %35, %bb.1, %7, %bb.2 Index: llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir +++ llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir @@ -87,7 +87,7 @@ ; CHECK-LABEL: name: MVE_VLDRWU32 ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 @@ -114,7 +114,7 @@ ; CHECK-LABEL: name: MVE_VLDRHU16 ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 @@ -141,7 +141,7 @@ ; CHECK-LABEL: name: MVE_VLDRBU8 ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 @@ -505,7 +505,7 @@ ; CHECK-LABEL: name: ld0ld4 ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8) ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] @@ -535,7 +535,7 @@ ; CHECK-LABEL: name: ld4ld0 ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] @@ -566,7 +566,7 @@ ; CHECK-LABEL: name: ld0ld4ld0 ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) @@ -599,7 +599,7 @@ ; CHECK-LABEL: name: ld4ld0ld4 ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8) @@ -631,7 +631,7 @@ ; CHECK-LABEL: name: addload ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8) ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] @@ -661,7 +661,7 @@ ; CHECK-LABEL: name: sub ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8) ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] @@ -711,7 +711,7 @@ name: postincUse tracksRegLiveness: true registers: - - { id: 0, class: gprnopc, preferred-register: '' } + - { id: 0, class: rgpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' } @@ -725,13 +725,13 @@ ; CHECK-LABEL: name: postincUse ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 4, 0, $noreg :: (load 16, align 8) ; CHECK: $r0 = COPY [[t2ADDri]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 - %0:gprnopc = COPY $r0 + %0:rgpr = COPY $r0 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) %4:rgpr, %3:mqpr = MVE_VLDRWU32_post %0, 4, 0, $noreg :: (load 16, align 8) @@ -819,7 +819,7 @@ ; CHECK-LABEL: name: addUseOK ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8) ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg @@ -886,7 +886,7 @@ ; CHECK-LABEL: name: addUseKilled ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8) ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8) @@ -905,7 +905,7 @@ name: MVE_VLDRWU32_post tracksRegLiveness: true registers: - - { id: 0, class: gprnopc, preferred-register: '' } + - { id: 0, class: rgpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' } liveins: @@ -917,12 +917,12 @@ ; CHECK-LABEL: name: MVE_VLDRWU32_post ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -16, 0, $noreg :: (load 16, align 8) ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 - %0:gprnopc = COPY $r0 + %0:rgpr = COPY $r0 %2:rgpr, %1:mqpr = MVE_VLDRWU32_post %0, 32, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRWU32 %0, 16, 0, $noreg :: (load 16, align 8) $r0 = COPY %2 @@ -933,7 +933,7 @@ name: MVE_VLDRHU16_post tracksRegLiveness: true registers: - - { id: 0, class: gprnopc, preferred-register: '' } + - { id: 0, class: rgpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' } liveins: @@ -945,12 +945,12 @@ ; CHECK-LABEL: name: MVE_VLDRHU16_post ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[MVE_VLDRHU16_post]], -16, 0, $noreg :: (load 16, align 8) ; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 - %0:gprnopc = COPY $r0 + %0:rgpr = COPY $r0 %2:rgpr, %1:mqpr = MVE_VLDRHU16_post %0, 32, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRHU16 %0, 16, 0, $noreg :: (load 16, align 8) $r0 = COPY %2 @@ -961,7 +961,7 @@ name: MVE_VLDRBU8_post tracksRegLiveness: true registers: - - { id: 0, class: gprnopc, preferred-register: '' } + - { id: 0, class: rgpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' } liveins: @@ -973,12 +973,12 @@ ; CHECK-LABEL: name: MVE_VLDRBU8_post ; CHECK: liveins: $r0, $q0 - ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[MVE_VLDRBU8_post]], -16, 0, $noreg :: (load 16, align 8) ; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 - %0:gprnopc = COPY $r0 + %0:rgpr = COPY $r0 %2:rgpr, %1:mqpr = MVE_VLDRBU8_post %0, 32, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRBU8 %0, 16, 0, $noreg :: (load 16, align 8) $r0 = COPY %2