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Differential D96341

GlobalISel: Merge some AMDGPU ABI lowering code to generic code
ClosedPublic

Authored by arsenm on Feb 9 2021, 7:29 AM.

Details

Reviewers
paquette
aemerson
cdevadas
dsanders
bogner
aditya_nandakumar
foad
Petar.Avramovic
mbrkusanin
Summary

AMDGPU currently has a lot of pre-processing code to pre-split
argument types into 32-bit pieces before passing it to the generic
code in handleAssignments. This is a bit sloppy and also requires some
overly fancy iterator work when building the calls. It's better if all
argument marshalling code is handled directly in
handleAssignments. This handles more situations like decomposing large
element vectors into sub-element sized pieces.




This should mostly be NFC, but does change the generated code by

shifting where the initial argument packing instructions are placed. I

think this is nicer looking, since it now emits the packing code

directly after the relevant copies, rather than after the copies for

the remaining arguments.






This doubles down on gfx6/gfx7 using the gfx8+ ABI for 16-bit

types. This is ultimately the better option, but incompatible with the

DAG. Fixing this requires more work, especially for f16.
Diff Detail
Event Timeline
arsenm created this revision.Feb 9 2021, 7:29 AM
Herald added subscribers: wenlei, kerbowa, hiraditya and 8 others.  ·  View Herald TranscriptFeb 9 2021, 7:29 AM
arsenm requested review of this revision.Feb 9 2021, 7:29 AM
Herald added a project: Restricted Project.  ·  View Herald TranscriptFeb 9 2021, 7:29 AM
Herald added a subscriber: wdng.  ·  View Herald Transcript
bogner accepted this revision.Feb 17 2021, 2:56 PM
This revision is now accepted and ready to land.Feb 17 2021, 2:56 PM
arsenm closed this revision.Feb 18 2021, 2:27 PM
62d946e133f748d4500903c2b80fc456ff409505
Revision Contents
PathSize
llvm/
lib/
CodeGen/
GlobalISel/
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GlobalISel/
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Diff 322386
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Show First 20 Lines • Show All 222 Lines • ▼ Show 20 Linesvoid CallLowering::unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg,

  SmallVector<uint64_t, 8> Offsets;
  SmallVector<uint64_t, 8> Offsets;

  computeValueLLTs(DL, *PackedTy, LLTs, &Offsets);
  computeValueLLTs(DL, *PackedTy, LLTs, &Offsets);

  assert(LLTs.size() == DstRegs.size() && "Regs / types mismatch");
  assert(LLTs.size() == DstRegs.size() && "Regs / types mismatch");




  for (unsigned i = 0; i < DstRegs.size(); ++i)
  for (unsigned i = 0; i < DstRegs.size(); ++i)

    MIRBuilder.buildExtract(DstRegs[i], SrcReg, Offsets[i]);
    MIRBuilder.buildExtract(DstRegs[i], SrcReg, Offsets[i]);

}
}




/// Pack values \p SrcRegs to cover the vector type result \p DstRegs.

static MachineInstrBuilder

mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,

                            ArrayRef<Register> SrcRegs) {

  MachineRegisterInfo &MRI = *B.getMRI();

  LLT LLTy = MRI.getType(DstRegs[0]);

  LLT PartLLT = MRI.getType(SrcRegs[0]);



  // Deal with v3s16 split into v2s16

  LLT LCMTy = getLCMType(LLTy, PartLLT);

  if (LCMTy == LLTy) {

    // Common case where no padding is needed.

    assert(DstRegs.size() == 1);

    return B.buildConcatVectors(DstRegs[0], SrcRegs);

  }



  const int NumWide = LCMTy.getSizeInBits() / PartLLT.getSizeInBits();

  Register Undef = B.buildUndef(PartLLT).getReg(0);



  // Build vector of undefs.

  SmallVector<Register, 8> WidenedSrcs(NumWide, Undef);



  // Replace the first sources with the real registers.

  std::copy(SrcRegs.begin(), SrcRegs.end(), WidenedSrcs.begin());



  auto Widened = B.buildConcatVectors(LCMTy, WidenedSrcs);

  int NumDst = LCMTy.getSizeInBits() / LLTy.getSizeInBits();



  SmallVector<Register, 8> PadDstRegs(NumDst);

  std::copy(DstRegs.begin(), DstRegs.end(), PadDstRegs.begin());



  // Create the excess dead defs for the unmerge.

  for (int I = DstRegs.size(); I != NumDst; ++I)

    PadDstRegs[I] = MRI.createGenericVirtualRegister(LLTy);



  return B.buildUnmerge(PadDstRegs, Widened);

}



/// Create a sequence of instructions to combine pieces split into register

/// typed values to the original IR value. \p OrigRegs contains the destination

/// value registers of type \p LLTy, and \p Regs contains the legalized pieces

/// with type \p PartLLT.

static void buildCopyToParts(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,

                             ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT) {

  MachineRegisterInfo &MRI = *B.getMRI();



  if (!LLTy.isVector() && !PartLLT.isVector()) {

    assert(OrigRegs.size() == 1);

    LLT OrigTy = MRI.getType(OrigRegs[0]);



    unsigned SrcSize = PartLLT.getSizeInBits() * Regs.size();

    if (SrcSize == OrigTy.getSizeInBits())

      B.buildMerge(OrigRegs[0], Regs);

    else {

      auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs);

      B.buildTrunc(OrigRegs[0], Widened);

    }



    return;

  }



  if (LLTy.isVector() && PartLLT.isVector()) {

    assert(OrigRegs.size() == 1);

    assert(LLTy.getElementType() == PartLLT.getElementType());

    mergeVectorRegsToResultRegs(B, OrigRegs, Regs);

    return;

  }



  assert(LLTy.isVector() && !PartLLT.isVector());



  LLT DstEltTy = LLTy.getElementType();



  // Pointer information was discarded. We'll need to coerce some register types

  // to avoid violating type constraints.

  LLT RealDstEltTy = MRI.getType(OrigRegs[0]).getElementType();



  assert(DstEltTy.getSizeInBits() == RealDstEltTy.getSizeInBits());



  if (DstEltTy == PartLLT) {

    // Vector was trivially scalarized.



    if (RealDstEltTy.isPointer()) {

      for (Register Reg : Regs)

        MRI.setType(Reg, RealDstEltTy);

    }



    B.buildBuildVector(OrigRegs[0], Regs);

  } else if (DstEltTy.getSizeInBits() > PartLLT.getSizeInBits()) {

    // Deal with vector with 64-bit elements decomposed to 32-bit

    // registers. Need to create intermediate 64-bit elements.

    SmallVector<Register, 8> EltMerges;

    int PartsPerElt = DstEltTy.getSizeInBits() / PartLLT.getSizeInBits();



    assert(DstEltTy.getSizeInBits() % PartLLT.getSizeInBits() == 0);



    for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {

      auto Merge = B.buildMerge(RealDstEltTy, Regs.take_front(PartsPerElt));

      // Fix the type in case this is really a vector of pointers.

      MRI.setType(Merge.getReg(0), RealDstEltTy);

      EltMerges.push_back(Merge.getReg(0));

      Regs = Regs.drop_front(PartsPerElt);

    }



    B.buildBuildVector(OrigRegs[0], EltMerges);

  } else {

    // Vector was split, and elements promoted to a wider type.

    // FIXME: Should handle floating point promotions.

    LLT BVType = LLT::vector(LLTy.getNumElements(), PartLLT);

    auto BV = B.buildBuildVector(BVType, Regs);

    B.buildTrunc(OrigRegs[0], BV);

  }

}



bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,

                                     SmallVectorImpl<ArgInfo> &Args,
                                     SmallVectorImpl<ArgInfo> &Args,

                                     ValueHandler &Handler,
                                     ValueHandler &Handler,

                                     CallingConv::ID CallConv, bool IsVarArg,
                                     CallingConv::ID CallConv, bool IsVarArg,

                                     Register ThisReturnReg) const {
                                     Register ThisReturnReg) const {

  MachineFunction &MF = MIRBuilder.getMF();
  MachineFunction &MF = MIRBuilder.getMF();

  const Function &F = MF.getFunction();
  const Function &F = MF.getFunction();

  SmallVector<CCValAssign, 16> ArgLocs;
  SmallVector<CCValAssign, 16> ArgLocs;

Show All 34 Lines    if (NumParts == 1) {

      // Try to use the register type if we couldn't assign the VT.
      // Try to use the register type if we couldn't assign the VT.

      if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, Args[i],
      if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, Args[i],

                            Args[i].Flags[0], CCInfo))
                            Args[i].Flags[0], CCInfo))

        return false;
        return false;

      continue;
      continue;

    }
    }




    assert(NumParts > 1);
    assert(NumParts > 1);

    // For now only handle exact splits.

    if (NewVT.getSizeInBits() * NumParts != CurVT.getSizeInBits())

      return false;




    // For incoming arguments (physregs to vregs), we could have values in
    // For incoming arguments (physregs to vregs), we could have values in

    // physregs (or memlocs) which we want to extract and copy to vregs.
    // physregs (or memlocs) which we want to extract and copy to vregs.

    // During this, we might have to deal with the LLT being split across
    // During this, we might have to deal with the LLT being split across

    // multiple regs, so we have to record this information for later.
    // multiple regs, so we have to record this information for later.

    //
    //

    // If we have outgoing args, then we have the opposite case. We have a
    // If we have outgoing args, then we have the opposite case. We have a

    // vreg with an LLT which we want to assign to a physical location, and
    // vreg with an LLT which we want to assign to a physical location, and

▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines  for (unsigned i = 0, e = Args.size(), j = 0; i != e; ++i, ++j) {

    }
    }




    // FIXME: Pack registers if we have more than one.
    // FIXME: Pack registers if we have more than one.

    Register ArgReg = Args[i].Regs[0];
    Register ArgReg = Args[i].Regs[0];




    EVT OrigVT = EVT::getEVT(Args[i].Ty);
    EVT OrigVT = EVT::getEVT(Args[i].Ty);

    EVT VAVT = VA.getValVT();
    EVT VAVT = VA.getValVT();

    const LLT OrigTy = getLLTForType(*Args[i].Ty, DL);
    const LLT OrigTy = getLLTForType(*Args[i].Ty, DL);

    const LLT VATy(VAVT.getSimpleVT());




    // Expected to be multiple regs for a single incoming arg.
    // Expected to be multiple regs for a single incoming arg.

    // There should be Regs.size() ArgLocs per argument.
    // There should be Regs.size() ArgLocs per argument.

    unsigned NumArgRegs = Args[i].Regs.size();
    unsigned NumArgRegs = Args[i].Regs.size();




    assert((j + (NumArgRegs - 1)) < ArgLocs.size() &&
    assert((j + (NumArgRegs - 1)) < ArgLocs.size() &&

           "Too many regs for number of args");
           "Too many regs for number of args");

    for (unsigned Part = 0; Part < NumArgRegs; ++Part) {
    for (unsigned Part = 0; Part < NumArgRegs; ++Part) {

Show All 32 Lines    for (unsigned Part = 0; Part < NumArgRegs; ++Part) {




        // Insert the argument copies. If VAVT < OrigVT, we'll insert the merge
        // Insert the argument copies. If VAVT < OrigVT, we'll insert the merge

        // to the original register after handling all of the parts.
        // to the original register after handling all of the parts.

        Handler.assignValueToReg(Args[i].Regs[Part], VA.getLocReg(), VA);
        Handler.assignValueToReg(Args[i].Regs[Part], VA.getLocReg(), VA);

        continue;
        continue;

      }
      }




      // This ArgLoc covers multiple pieces, so we need to split it.
      // This ArgLoc covers multiple pieces, so we need to split it.

      const LLT VATy(VAVT.getSimpleVT());

      Register NewReg =
      Register NewReg =

        MIRBuilder.getMRI()->createGenericVirtualRegister(VATy);
        MIRBuilder.getMRI()->createGenericVirtualRegister(VATy);

      Handler.assignValueToReg(NewReg, VA.getLocReg(), VA);
      Handler.assignValueToReg(NewReg, VA.getLocReg(), VA);

      // If it's a vector type, we either need to truncate the elements
      // If it's a vector type, we either need to truncate the elements

      // or do an unmerge to get the lower block of elements.
      // or do an unmerge to get the lower block of elements.

      if (VATy.isVector() &&
      if (VATy.isVector() &&

          VATy.getNumElements() > OrigVT.getVectorNumElements()) {
          VATy.getNumElements() > OrigVT.getVectorNumElements()) {

        // Just handle the case where the VA type is 2 * original type.
        // Just handle the case where the VA type is 2 * original type.

        if (VATy.getNumElements() != OrigVT.getVectorNumElements() * 2) {
        if (VATy.getNumElements() != OrigVT.getVectorNumElements() * 2) {

          LLVM_DEBUG(dbgs()
          LLVM_DEBUG(dbgs()

                     << "Incoming promoted vector arg has too many elts");
                     << "Incoming promoted vector arg has too many elts");

          return false;
          return false;

        }
        }

        auto Unmerge = MIRBuilder.buildUnmerge({OrigTy, OrigTy}, {NewReg});
        auto Unmerge = MIRBuilder.buildUnmerge({OrigTy, OrigTy}, {NewReg});

        MIRBuilder.buildCopy(ArgReg, Unmerge.getReg(0));
        MIRBuilder.buildCopy(ArgReg, Unmerge.getReg(0));

      } else {
      } else {

        MIRBuilder.buildTrunc(ArgReg, {NewReg}).getReg(0);
        MIRBuilder.buildTrunc(ArgReg, {NewReg}).getReg(0);

      }
      }

    }
    }




    // Now that all pieces have been handled, re-pack any arguments into any
    // Now that all pieces have been handled, re-pack any arguments into any

    // wider, original registers.
    // wider, original registers.

    if (Handler.isIncomingArgumentHandler()) {
    if (Handler.isIncomingArgumentHandler()) {

      if (VAVT.getFixedSizeInBits() < OrigVT.getFixedSizeInBits()) {
      // Merge the split registers into the expected larger result vregs of

        assert(NumArgRegs >= 2);
      // the original call.




        // Merge the split registers into the expected larger result vreg
      if (OrigTy != VATy && !Args[i].OrigRegs.empty()) {

        // of the original call.
        buildCopyToParts(MIRBuilder, Args[i].OrigRegs, Args[i].Regs, OrigTy,

        MIRBuilder.buildMerge(Args[i].OrigRegs[0], Args[i].Regs);
                         VATy);

      }
      }

    }
    }




    j += NumArgRegs - 1;
    j += NumArgRegs - 1;

  }
  }




  return true;
  return true;

}
}

▲ Show 20 Lines • Show All 316 Lines • Show Last 20 Lines
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
Show First 20 Lines • Show All 729 Lines • ▼ Show 20 Lines  for (auto &Arg : F.args()) {

    ++i;
    ++i;

  }
  }




  TLI.allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
  TLI.allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);

  TLI.allocateSystemSGPRs(CCInfo, MF, *Info, F.getCallingConv(), false);
  TLI.allocateSystemSGPRs(CCInfo, MF, *Info, F.getCallingConv(), false);

  return true;
  return true;

}
}




/// Pack values \p SrcRegs to cover the vector type result \p DstRegs.

static MachineInstrBuilder mergeVectorRegsToResultRegs(

  MachineIRBuilder &B, ArrayRef<Register> DstRegs, ArrayRef<Register> SrcRegs) {

  MachineRegisterInfo &MRI = *B.getMRI();

  LLT LLTy = MRI.getType(DstRegs[0]);

  LLT PartLLT = MRI.getType(SrcRegs[0]);



  // Deal with v3s16 split into v2s16

  LLT LCMTy = getLCMType(LLTy, PartLLT);

  if (LCMTy == LLTy) {

    // Common case where no padding is needed.

    assert(DstRegs.size() == 1);

    return B.buildConcatVectors(DstRegs[0], SrcRegs);

  }



  const int NumWide =  LCMTy.getSizeInBits() / PartLLT.getSizeInBits();

  Register Undef = B.buildUndef(PartLLT).getReg(0);



  // Build vector of undefs.

  SmallVector<Register, 8> WidenedSrcs(NumWide, Undef);



  // Replace the first sources with the real registers.

  std::copy(SrcRegs.begin(), SrcRegs.end(), WidenedSrcs.begin());



  auto Widened = B.buildConcatVectors(LCMTy, WidenedSrcs);

  int NumDst = LCMTy.getSizeInBits() / LLTy.getSizeInBits();



  SmallVector<Register, 8> PadDstRegs(NumDst);

  std::copy(DstRegs.begin(), DstRegs.end(), PadDstRegs.begin());



  // Create the excess dead defs for the unmerge.

  for (int I = DstRegs.size(); I != NumDst; ++I)

    PadDstRegs[I] = MRI.createGenericVirtualRegister(LLTy);



  return B.buildUnmerge(PadDstRegs, Widened);

}



// TODO: Move this to generic code

static void packSplitRegsToOrigType(MachineIRBuilder &B,

                                    ArrayRef<Register> OrigRegs,

                                    ArrayRef<Register> Regs,

                                    LLT LLTy,

                                    LLT PartLLT) {

  MachineRegisterInfo &MRI = *B.getMRI();



  if (!LLTy.isVector() && !PartLLT.isVector()) {

    assert(OrigRegs.size() == 1);

    LLT OrigTy = MRI.getType(OrigRegs[0]);



    unsigned SrcSize = PartLLT.getSizeInBits() * Regs.size();

    if (SrcSize == OrigTy.getSizeInBits())

      B.buildMerge(OrigRegs[0], Regs);

    else {

      auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs);

      B.buildTrunc(OrigRegs[0], Widened);

    }



    return;

  }



  if (LLTy.isVector() && PartLLT.isVector()) {

    assert(OrigRegs.size() == 1);

    assert(LLTy.getElementType() == PartLLT.getElementType());

    mergeVectorRegsToResultRegs(B, OrigRegs, Regs);

    return;

  }



  assert(LLTy.isVector() && !PartLLT.isVector());



  LLT DstEltTy = LLTy.getElementType();



  // Pointer information was discarded. We'll need to coerce some register types

  // to avoid violating type constraints.

  LLT RealDstEltTy = MRI.getType(OrigRegs[0]).getElementType();



  assert(DstEltTy.getSizeInBits() == RealDstEltTy.getSizeInBits());



  if (DstEltTy == PartLLT) {

    // Vector was trivially scalarized.



    if (RealDstEltTy.isPointer()) {

      for (Register Reg : Regs)

        MRI.setType(Reg, RealDstEltTy);

    }



    B.buildBuildVector(OrigRegs[0], Regs);

  } else if (DstEltTy.getSizeInBits() > PartLLT.getSizeInBits()) {

    // Deal with vector with 64-bit elements decomposed to 32-bit

    // registers. Need to create intermediate 64-bit elements.

    SmallVector<Register, 8> EltMerges;

    int PartsPerElt = DstEltTy.getSizeInBits() / PartLLT.getSizeInBits();



    assert(DstEltTy.getSizeInBits() % PartLLT.getSizeInBits() == 0);



    for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I)  {

      auto Merge = B.buildMerge(RealDstEltTy, Regs.take_front(PartsPerElt));

      // Fix the type in case this is really a vector of pointers.

      MRI.setType(Merge.getReg(0), RealDstEltTy);

      EltMerges.push_back(Merge.getReg(0));

      Regs = Regs.drop_front(PartsPerElt);

    }



    B.buildBuildVector(OrigRegs[0], EltMerges);

  } else {

    // Vector was split, and elements promoted to a wider type.

    LLT BVType = LLT::vector(LLTy.getNumElements(), PartLLT);

    auto BV = B.buildBuildVector(BVType, Regs);

    B.buildTrunc(OrigRegs[0], BV);

  }

}



bool AMDGPUCallLowering::lowerFormalArguments(
bool AMDGPUCallLowering::lowerFormalArguments(

    MachineIRBuilder &B, const Function &F, ArrayRef<ArrayRef<Register>> VRegs,
    MachineIRBuilder &B, const Function &F, ArrayRef<ArrayRef<Register>> VRegs,

    FunctionLoweringInfo &FLI) const {
    FunctionLoweringInfo &FLI) const {

  CallingConv::ID CC = F.getCallingConv();
  CallingConv::ID CC = F.getCallingConv();




  // The infrastructure for normal calling convention lowering is essentially
  // The infrastructure for normal calling convention lowering is essentially

  // useless for kernels. We want to avoid any kind of legalization or argument
  // useless for kernels. We want to avoid any kind of legalization or argument

  // splitting.
  // splitting.

Show All 24 Linesbool AMDGPUCallLowering::lowerFormalArguments(

  }
  }




  if (Info->hasImplicitBufferPtr()) {
  if (Info->hasImplicitBufferPtr()) {

    Register ImplicitBufferPtrReg = Info->addImplicitBufferPtr(*TRI);
    Register ImplicitBufferPtrReg = Info->addImplicitBufferPtr(*TRI);

    MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
    MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);

    CCInfo.AllocateReg(ImplicitBufferPtrReg);
    CCInfo.AllocateReg(ImplicitBufferPtrReg);

  }
  }




  SmallVector<ArgInfo, 8> SplitArg;

  SmallVector<ArgInfo, 32> SplitArgs;
  SmallVector<ArgInfo, 32> SplitArgs;

  unsigned Idx = 0;
  unsigned Idx = 0;

  unsigned PSInputNum = 0;
  unsigned PSInputNum = 0;




  // Insert the hidden sret parameter if the return value won't fit in the
  // Insert the hidden sret parameter if the return value won't fit in the

  // return registers.
  // return registers.

  if (!FLI.CanLowerReturn)
  if (!FLI.CanLowerReturn)

    insertSRetIncomingArgument(F, SplitArgs, FLI.DemoteRegister, MRI, DL);
    insertSRetIncomingArgument(F, SplitArgs, FLI.DemoteRegister, MRI, DL);

Show All 33 Lines    if (CC == CallingConv::AMDGPU_PS && !InReg && PSInputNum <= 15) {

        continue;
        continue;

      }
      }

    }
    }




    ArgInfo OrigArg(VRegs[Idx], Arg.getType());
    ArgInfo OrigArg(VRegs[Idx], Arg.getType());

    const unsigned OrigArgIdx = Idx + AttributeList::FirstArgIndex;
    const unsigned OrigArgIdx = Idx + AttributeList::FirstArgIndex;

    setArgFlags(OrigArg, OrigArgIdx, DL, F);
    setArgFlags(OrigArg, OrigArgIdx, DL, F);




    SplitArg.clear();
    splitToValueTypes(B, OrigArg, SplitArgs, DL, CC);

    splitToValueTypes(B, OrigArg, SplitArg, DL, CC);



    processSplitArgs(B, OrigArg, SplitArg, SplitArgs, DL, CC, false,

                     // FIXME: We should probably be passing multiple registers

                     // to handleAssignments to do this

                     [&](ArrayRef<Register> Regs, Register DstReg, LLT LLTy,

                         LLT PartLLT, int VTSplitIdx) {

                       assert(DstReg == VRegs[Idx][VTSplitIdx]);

                       packSplitRegsToOrigType(B, VRegs[Idx][VTSplitIdx], Regs,

                                               LLTy, PartLLT);

                     });



    ++Idx;
    ++Idx;

  }
  }




  // At least one interpolation mode must be enabled or else the GPU will
  // At least one interpolation mode must be enabled or else the GPU will

  // hang.
  // hang.

  //
  //

  // Check PSInputAddr instead of PSInputEnable. The idea is that if the user
  // Check PSInputAddr instead of PSInputEnable. The idea is that if the user

  // set PSInputAddr, the user wants to enable some bits after the compilation
  // set PSInputAddr, the user wants to enable some bits after the compilation

▲ Show 20 Lines • Show All 391 Lines • ▼ Show 20 Linesbool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,

  MachineInstrBuilder CallSeqEnd =
  MachineInstrBuilder CallSeqEnd =

    MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN);
    MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN);




  SmallVector<ArgInfo, 8> InArgs;
  SmallVector<ArgInfo, 8> InArgs;

  if (!Info.CanLowerReturn) {
  if (!Info.CanLowerReturn) {

    insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,
    insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,

                    Info.DemoteRegister, Info.DemoteStackIndex);
                    Info.DemoteRegister, Info.DemoteStackIndex);

  } else if (!Info.OrigRet.Ty->isVoidTy()) {
  } else if (!Info.OrigRet.Ty->isVoidTy()) {

    SmallVector<ArgInfo, 8> PreSplitRetInfos;
    splitToValueTypes(MIRBuilder, Info.OrigRet, InArgs, DL, Info.CallConv);



    splitToValueTypes(

      MIRBuilder, Info.OrigRet, PreSplitRetInfos/*InArgs*/, DL, Info.CallConv);



    processSplitArgs(MIRBuilder, Info.OrigRet,

                     PreSplitRetInfos, InArgs/*SplitRetInfos*/, DL, Info.CallConv, false,

                     [&](ArrayRef<Register> Regs, Register DstReg,

                         LLT LLTy, LLT PartLLT, int VTSplitIdx) {

                       assert(DstReg == Info.OrigRet.Regs[VTSplitIdx]);

                       packSplitRegsToOrigType(MIRBuilder, Info.OrigRet.Regs[VTSplitIdx],

                                               Regs, LLTy, PartLLT);

                     });

  }
  }




  // Make sure the raw argument copies are inserted before the marshalling to
  // Make sure the raw argument copies are inserted before the marshalling to

  // the original types.
  // the original types.

  MIRBuilder.setInsertPt(MIRBuilder.getMBB(), CallSeqEnd);
  MIRBuilder.setInsertPt(MIRBuilder.getMBB(), CallSeqEnd);




  // Finally we can copy the returned value back into its virtual-register. In
  // Finally we can copy the returned value back into its virtual-register. In

  // symmetry with the arguments, the physical register must be an
  // symmetry with the arguments, the physical register must be an

Show All 18 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
Show First 20 Lines • Show All 279 Lines • ▼ Show 20 Lines; GCN-NEXT:    ; return to shader part epilog

  %zext = zext i16 %and to i32
  %zext = zext i16 %and to i32

  %cast.zext = bitcast i32 %zext to float
  %cast.zext = bitcast i32 %zext to float

  ret float %cast.zext
  ret float %cast.zext

}
}




define amdgpu_ps i32 @s_andn2_v2i16(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {
define amdgpu_ps i32 @s_andn2_v2i16(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {

; GFX6-LABEL: s_andn2_v2i16:
; GFX6-LABEL: s_andn2_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_mov_b32 s1, 0xffff
; GFX6-NEXT:    s_xor_b32 s0, s3, -1

; GFX6-NEXT:    s_and_b32 s2, s2, s1
; GFX6-NEXT:    s_and_b32 s0, s2, s0

; GFX6-NEXT:    s_lshl_b32 s0, s3, 16

; GFX6-NEXT:    s_or_b32 s0, s0, s2

; GFX6-NEXT:    s_lshl_b32 s2, s5, 16

; GFX6-NEXT:    s_and_b32 s1, s4, s1

; GFX6-NEXT:    s_or_b32 s1, s2, s1

; GFX6-NEXT:    s_xor_b32 s1, s1, -1

; GFX6-NEXT:    s_and_b32 s0, s0, s1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX9-LABEL: s_andn2_v2i16:
; GFX9-LABEL: s_andn2_v2i16:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_andn2_b32 s0, s2, s3
; GFX9-NEXT:    s_andn2_b32 s0, s2, s3

; GFX9-NEXT:    ; return to shader part epilog
; GFX9-NEXT:    ; return to shader part epilog

  %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
  %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>

  %and = and <2 x i16> %src0, %not.src1
  %and = and <2 x i16> %src0, %not.src1

  %cast = bitcast <2 x i16> %and to i32
  %cast = bitcast <2 x i16> %and to i32

  ret i32 %cast
  ret i32 %cast

}
}




define amdgpu_ps i32 @s_andn2_v2i16_commute(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {
define amdgpu_ps i32 @s_andn2_v2i16_commute(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {

; GFX6-LABEL: s_andn2_v2i16_commute:
; GFX6-LABEL: s_andn2_v2i16_commute:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_mov_b32 s1, 0xffff
; GFX6-NEXT:    s_xor_b32 s0, s3, -1

; GFX6-NEXT:    s_and_b32 s2, s2, s1
; GFX6-NEXT:    s_and_b32 s0, s0, s2

; GFX6-NEXT:    s_lshl_b32 s0, s3, 16

; GFX6-NEXT:    s_or_b32 s0, s0, s2

; GFX6-NEXT:    s_lshl_b32 s2, s5, 16

; GFX6-NEXT:    s_and_b32 s1, s4, s1

; GFX6-NEXT:    s_or_b32 s1, s2, s1

; GFX6-NEXT:    s_xor_b32 s1, s1, -1

; GFX6-NEXT:    s_and_b32 s0, s1, s0

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX9-LABEL: s_andn2_v2i16_commute:
; GFX9-LABEL: s_andn2_v2i16_commute:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_andn2_b32 s0, s2, s3
; GFX9-NEXT:    s_andn2_b32 s0, s2, s3

; GFX9-NEXT:    ; return to shader part epilog
; GFX9-NEXT:    ; return to shader part epilog

  %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
  %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>

  %and = and <2 x i16> %not.src1, %src0
  %and = and <2 x i16> %not.src1, %src0

  %cast = bitcast <2 x i16> %and to i32
  %cast = bitcast <2 x i16> %and to i32

  ret i32 %cast
  ret i32 %cast

}
}




define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {
define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {

; GFX6-LABEL: s_andn2_v2i16_multi_use:
; GFX6-LABEL: s_andn2_v2i16_multi_use:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_mov_b32 s1, 0xffff
; GFX6-NEXT:    s_xor_b32 s1, s3, -1

; GFX6-NEXT:    s_and_b32 s2, s2, s1
; GFX6-NEXT:    s_and_b32 s0, s2, s1

; GFX6-NEXT:    s_lshl_b32 s0, s3, 16

; GFX6-NEXT:    s_or_b32 s0, s0, s2

; GFX6-NEXT:    s_lshl_b32 s2, s5, 16

; GFX6-NEXT:    s_and_b32 s1, s4, s1

; GFX6-NEXT:    s_or_b32 s1, s2, s1

; GFX6-NEXT:    s_xor_b32 s1, s1, -1

; GFX6-NEXT:    s_and_b32 s0, s0, s1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX9-LABEL: s_andn2_v2i16_multi_use:
; GFX9-LABEL: s_andn2_v2i16_multi_use:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_xor_b32 s1, s3, -1
; GFX9-NEXT:    s_xor_b32 s1, s3, -1

; GFX9-NEXT:    s_andn2_b32 s0, s2, s3
; GFX9-NEXT:    s_andn2_b32 s0, s2, s3

; GFX9-NEXT:    ; return to shader part epilog
; GFX9-NEXT:    ; return to shader part epilog

  %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
  %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>

  %and = and <2 x i16> %src0, %not.src1
  %and = and <2 x i16> %src0, %not.src1




  %cast.0 = bitcast <2 x i16> %and to i32
  %cast.0 = bitcast <2 x i16> %and to i32

  %cast.1 = bitcast <2 x i16> %not.src1 to i32
  %cast.1 = bitcast <2 x i16> %not.src1 to i32

  %insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
  %insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0

  %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
  %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1

  ret { i32, i32 } %insert.1
  ret { i32, i32 } %insert.1

}
}




define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_foldable_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1, <2 x i16> inreg %src2) {
define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_foldable_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1, <2 x i16> inreg %src2) {

; GFX6-LABEL: s_andn2_v2i16_multi_foldable_use:
; GFX6-LABEL: s_andn2_v2i16_multi_foldable_use:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_mov_b32 s1, 0xffff
; GFX6-NEXT:    s_xor_b32 s1, s4, -1

; GFX6-NEXT:    s_lshl_b32 s0, s3, 16
; GFX6-NEXT:    s_and_b32 s0, s2, s1

; GFX6-NEXT:    s_and_b32 s2, s2, s1
; GFX6-NEXT:    s_and_b32 s1, s3, s1

; GFX6-NEXT:    s_or_b32 s0, s0, s2

; GFX6-NEXT:    s_and_b32 s3, s4, s1

; GFX6-NEXT:    s_lshl_b32 s2, s5, 16

; GFX6-NEXT:    s_or_b32 s2, s2, s3

; GFX6-NEXT:    s_lshl_b32 s3, s7, 16

; GFX6-NEXT:    s_and_b32 s1, s6, s1

; GFX6-NEXT:    s_or_b32 s1, s3, s1

; GFX6-NEXT:    s_xor_b32 s1, s1, -1

; GFX6-NEXT:    s_and_b32 s0, s0, s1

; GFX6-NEXT:    s_and_b32 s1, s2, s1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX9-LABEL: s_andn2_v2i16_multi_foldable_use:
; GFX9-LABEL: s_andn2_v2i16_multi_foldable_use:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_andn2_b32 s0, s2, s4
; GFX9-NEXT:    s_andn2_b32 s0, s2, s4

; GFX9-NEXT:    s_andn2_b32 s1, s3, s4
; GFX9-NEXT:    s_andn2_b32 s1, s3, s4

; GFX9-NEXT:    ; return to shader part epilog
; GFX9-NEXT:    ; return to shader part epilog

  %not.src2 = xor <2 x i16> %src2, <i16 -1, i16 -1>
  %not.src2 = xor <2 x i16> %src2, <i16 -1, i16 -1>

  %and0 = and <2 x i16> %src0, %not.src2
  %and0 = and <2 x i16> %src0, %not.src2

  %and1 = and <2 x i16> %src1, %not.src2
  %and1 = and <2 x i16> %src1, %not.src2




  %cast.0 = bitcast <2 x i16> %and0 to i32
  %cast.0 = bitcast <2 x i16> %and0 to i32

  %cast.1 = bitcast <2 x i16> %and1 to i32
  %cast.1 = bitcast <2 x i16> %and1 to i32

  %insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
  %insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0

  %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
  %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1

  ret { i32, i32 } %insert.1
  ret { i32, i32 } %insert.1

}
}




define <2 x i16> @v_andn2_v2i16(<2 x i16> %src0, <2 x i16> %src1) {
define <2 x i16> @v_andn2_v2i16(<2 x i16> %src0, <2 x i16> %src1) {

; GFX6-LABEL: v_andn2_v2i16:
; GFX6-LABEL: v_andn2_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_mov_b32_e32 v4, 0xffff

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_and_b32_e32 v0, v0, v4

; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v3

; GFX6-NEXT:    v_and_b32_e32 v2, v2, v4

; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2

; GFX6-NEXT:    v_xor_b32_e32 v1, -1, v1
; GFX6-NEXT:    v_xor_b32_e32 v1, -1, v1

; GFX6-NEXT:    v_and_b32_e32 v0, v0, v1
; GFX6-NEXT:    v_and_b32_e32 v0, v0, v1

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX9-LABEL: v_andn2_v2i16:
; GFX9-LABEL: v_andn2_v2i16:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

▲ Show 20 Lines • Show All 236 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
Show First 20 Lines • Show All 467 Lines • ▼ Show 20 Lines; GFX9-NEXT:    ; return to shader part epilog

  %cast = bitcast i16 %result to half
  %cast = bitcast i16 %result to half

  ret half %cast
  ret half %cast

}
}




define <2 x i16> @v_ashr_v2i16(<2 x i16> %value, <2 x i16> %amount) {
define <2 x i16> @v_ashr_v2i16(<2 x i16> %value, <2 x i16> %amount) {

; GFX6-LABEL: v_ashr_v2i16:
; GFX6-LABEL: v_ashr_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    s_mov_b32 s4, 0xffff
; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_and_b32_e32 v2, s4, v2
; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1

; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1

; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16

; GFX6-NEXT:    v_ashrrev_i32_e32 v0, v2, v0
; GFX6-NEXT:    v_ashrrev_i32_e32 v0, v1, v0

; GFX6-NEXT:    v_and_b32_e32 v2, s4, v3
; GFX6-NEXT:    v_bfe_i32 v1, v2, 0, 16

; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT:    v_ashrrev_i32_e32 v1, v3, v1

; GFX6-NEXT:    v_ashrrev_i32_e32 v1, v2, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_ashr_v2i16:
; GFX8-LABEL: v_ashr_v2i16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_ashrrev_i16_e32 v2, v1, v0
; GFX8-NEXT:    v_ashrrev_i16_e32 v2, v1, v0

; GFX8-NEXT:    v_ashrrev_i16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT:    v_ashrrev_i16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1

; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0

; GFX8-NEXT:    s_setpc_b64 s[30:31]
; GFX8-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX9-LABEL: v_ashr_v2i16:
; GFX9-LABEL: v_ashr_v2i16:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX9-NEXT:    v_pk_ashrrev_i16 v0, v1, v0
; GFX9-NEXT:    v_pk_ashrrev_i16 v0, v1, v0

; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %result = ashr <2 x i16> %value, %amount
  %result = ashr <2 x i16> %value, %amount

  ret <2 x i16> %result
  ret <2 x i16> %result

}
}




define <2 x i16> @v_ashr_v2i16_15(<2 x i16> %value) {
define <2 x i16> @v_ashr_v2i16_15(<2 x i16> %value) {

; GFX6-LABEL: v_ashr_v2i16_15:
; GFX6-LABEL: v_ashr_v2i16_15:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16

; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16

; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 15, v0
; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 15, v0

; GFX6-NEXT:    v_ashrrev_i32_e32 v1, 15, v1
; GFX6-NEXT:    v_ashrrev_i32_e32 v1, 15, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_ashr_v2i16_15:
; GFX8-LABEL: v_ashr_v2i16_15:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

Show All 12 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %result = ashr <2 x i16> %value, <i16 15, i16 15>
  %result = ashr <2 x i16> %value, <i16 15, i16 15>

  ret <2 x i16> %result
  ret <2 x i16> %result

}
}




define amdgpu_ps i32 @s_ashr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {
define amdgpu_ps i32 @s_ashr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {

; GFX6-LABEL: s_ashr_v2i16:
; GFX6-LABEL: s_ashr_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_mov_b32 s4, 0xffff
; GFX6-NEXT:    s_mov_b32 s4, 0xffff

; GFX6-NEXT:    s_and_b32 s2, s2, s4
; GFX6-NEXT:    s_lshr_b32 s2, s0, 16

; GFX6-NEXT:    s_lshr_b32 s3, s1, 16

; GFX6-NEXT:    s_and_b32 s1, s1, s4

; GFX6-NEXT:    s_sext_i32_i16 s0, s0
; GFX6-NEXT:    s_sext_i32_i16 s0, s0

; GFX6-NEXT:    s_ashr_i32 s0, s0, s2
; GFX6-NEXT:    s_ashr_i32 s0, s0, s1

; GFX6-NEXT:    s_and_b32 s2, s3, s4
; GFX6-NEXT:    s_sext_i32_i16 s1, s2

; GFX6-NEXT:    s_sext_i32_i16 s1, s1
; GFX6-NEXT:    s_ashr_i32 s1, s1, s3

; GFX6-NEXT:    s_ashr_i32 s1, s1, s2

; GFX6-NEXT:    s_and_b32 s1, s1, s4
; GFX6-NEXT:    s_and_b32 s1, s1, s4

; GFX6-NEXT:    s_and_b32 s0, s0, s4
; GFX6-NEXT:    s_and_b32 s0, s0, s4

; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
; GFX6-NEXT:    s_lshl_b32 s1, s1, 16

; GFX6-NEXT:    s_or_b32 s0, s0, s1
; GFX6-NEXT:    s_or_b32 s0, s0, s1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: s_ashr_v2i16:
; GFX8-LABEL: s_ashr_v2i16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

Show All 24 Lines; GFX9-NEXT:    ; return to shader part epilog

  %cast = bitcast <2 x i16> %result to i32
  %cast = bitcast <2 x i16> %result to i32

  ret i32 %cast
  ret i32 %cast

}
}




define amdgpu_ps float @ashr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {
define amdgpu_ps float @ashr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {

; GFX6-LABEL: ashr_v2i16_sv:
; GFX6-LABEL: ashr_v2i16_sv:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_mov_b32 s2, 0xffff
; GFX6-NEXT:    s_mov_b32 s2, 0xffff

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0
; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0

; GFX6-NEXT:    s_sext_i32_i16 s0, s0
; GFX6-NEXT:    s_sext_i32_i16 s0, s0

; GFX6-NEXT:    v_ashr_i32_e32 v0, s0, v0
; GFX6-NEXT:    v_ashr_i32_e32 v0, s0, v0

; GFX6-NEXT:    v_and_b32_e32 v1, s2, v1

; GFX6-NEXT:    s_sext_i32_i16 s0, s1
; GFX6-NEXT:    s_sext_i32_i16 s0, s1

; GFX6-NEXT:    v_ashr_i32_e32 v1, s0, v1
; GFX6-NEXT:    v_ashr_i32_e32 v1, s0, v1

; GFX6-NEXT:    v_and_b32_e32 v1, s2, v1
; GFX6-NEXT:    v_and_b32_e32 v1, s2, v1

; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0
; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

Show All 13 Lines; GFX9-NEXT:    ; return to shader part epilog

  %result = ashr <2 x i16> %value, %amount
  %result = ashr <2 x i16> %value, %amount

  %cast = bitcast <2 x i16> %result to float
  %cast = bitcast <2 x i16> %result to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @ashr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {
define amdgpu_ps float @ashr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {

; GFX6-LABEL: ashr_v2i16_vs:
; GFX6-LABEL: ashr_v2i16_vs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16

; GFX6-NEXT:    s_mov_b32 s2, 0xffff
; GFX6-NEXT:    s_mov_b32 s2, 0xffff

; GFX6-NEXT:    v_ashrrev_i32_e32 v1, s1, v1

; GFX6-NEXT:    s_and_b32 s0, s0, s2
; GFX6-NEXT:    s_and_b32 s0, s0, s2

; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16

; GFX6-NEXT:    v_ashrrev_i32_e32 v0, s0, v0
; GFX6-NEXT:    v_ashrrev_i32_e32 v0, s0, v0

; GFX6-NEXT:    s_and_b32 s0, s1, s2

; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16

; GFX6-NEXT:    v_ashrrev_i32_e32 v1, s0, v1

; GFX6-NEXT:    v_and_b32_e32 v1, s2, v1
; GFX6-NEXT:    v_and_b32_e32 v1, s2, v1

; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0
; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: ashr_v2i16_vs:
; GFX8-LABEL: ashr_v2i16_vs:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

▲ Show 20 Lines • Show All 609 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
Show First 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %bswap = call i16 @llvm.bswap.i16(i16 %src)
  %bswap = call i16 @llvm.bswap.i16(i16 %src)

  ret i16 %bswap
  ret i16 %bswap

}
}




define amdgpu_ps i32 @s_bswap_v2i16(<2 x i16> inreg %src) {
define amdgpu_ps i32 @s_bswap_v2i16(<2 x i16> inreg %src) {

; GFX7-LABEL: s_bswap_v2i16:
; GFX7-LABEL: s_bswap_v2i16:

; GFX7:       ; %bb.0:
; GFX7:       ; %bb.0:

; GFX7-NEXT:    s_mov_b32 s3, 0xffff
; GFX7-NEXT:    s_lshr_b32 s1, s0, 16

; GFX7-NEXT:    s_and_b32 s3, s0, 0xffff

; GFX7-NEXT:    s_lshl_b32 s2, s0, 8
; GFX7-NEXT:    s_lshl_b32 s2, s0, 8

; GFX7-NEXT:    s_and_b32 s0, s0, s3
; GFX7-NEXT:    s_lshl_b32 s1, s1, 8

; GFX7-NEXT:    s_lshr_b32 s0, s0, 8
; GFX7-NEXT:    s_lshr_b32 s0, s0, 24

; GFX7-NEXT:    s_or_b32 s0, s0, s2

; GFX7-NEXT:    s_lshl_b32 s2, s1, 8

; GFX7-NEXT:    s_and_b32 s1, s1, s3

; GFX7-NEXT:    s_lshr_b32 s1, s1, 8

; GFX7-NEXT:    s_or_b32 s1, s1, s2

; GFX7-NEXT:    s_bfe_u32 s1, s1, 0x100000

; GFX7-NEXT:    s_bfe_u32 s0, s0, 0x100000

; GFX7-NEXT:    s_lshl_b32 s1, s1, 16

; GFX7-NEXT:    s_or_b32 s0, s0, s1
; GFX7-NEXT:    s_or_b32 s0, s0, s1

; GFX7-NEXT:    s_lshr_b32 s3, s3, 8

; GFX7-NEXT:    s_bfe_u32 s0, s0, 0x100000

; GFX7-NEXT:    s_or_b32 s2, s3, s2

; GFX7-NEXT:    s_bfe_u32 s1, s2, 0x100000

; GFX7-NEXT:    s_lshl_b32 s0, s0, 16

; GFX7-NEXT:    s_or_b32 s0, s1, s0

; GFX7-NEXT:    ; return to shader part epilog
; GFX7-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: s_bswap_v2i16:
; GFX8-LABEL: s_bswap_v2i16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    v_mov_b32_e32 v0, s0
; GFX8-NEXT:    v_mov_b32_e32 v0, s0

; GFX8-NEXT:    s_mov_b32 s0, 0x2030001
; GFX8-NEXT:    s_mov_b32 s0, 0x2030001

; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s0
; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s0

; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
; GFX8-NEXT:    v_readfirstlane_b32 s0, v0

▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %zext = sext i16 %bswap to i32
  %zext = sext i16 %bswap to i32

  ret i32 %zext
  ret i32 %zext

}
}




define <2 x i16> @v_bswap_v2i16(<2 x i16> %src) {
define <2 x i16> @v_bswap_v2i16(<2 x i16> %src) {

; GFX7-LABEL: v_bswap_v2i16:
; GFX7-LABEL: v_bswap_v2i16:

; GFX7:       ; %bb.0:
; GFX7:       ; %bb.0:

; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX7-NEXT:    s_mov_b32 s4, 0xffff
; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff, v0

; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 8, v0
; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 8, v0

; GFX7-NEXT:    v_and_b32_e32 v0, s4, v0
; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 8, v3

; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
; GFX7-NEXT:    v_or_b32_e32 v2, v3, v2

; GFX7-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 8, v1

; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 8, v1
; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 24, v0

; GFX7-NEXT:    v_and_b32_e32 v1, s4, v1
; GFX7-NEXT:    v_or_b32_e32 v1, v0, v1

; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
; GFX7-NEXT:    v_mov_b32_e32 v0, v2

; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2

; GFX7-NEXT:    s_setpc_b64 s[30:31]
; GFX7-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_bswap_v2i16:
; GFX8-LABEL: v_bswap_v2i16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    s_mov_b32 s4, 0x2030001
; GFX8-NEXT:    s_mov_b32 s4, 0x2030001

; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s4
; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s4

; GFX8-NEXT:    s_setpc_b64 s[30:31]
; GFX8-NEXT:    s_setpc_b64 s[30:31]

▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Linesdefine i16 @halfinsts_add_i16(i16 %arg0) #1 {

  ; CHECK:   S_SETPC_B64_return [[COPY4]], implicit $vgpr0
  ; CHECK:   S_SETPC_B64_return [[COPY4]], implicit $vgpr0

  %add = add i16 %arg0, %arg0
  %add = add i16 %arg0, %arg0

  ret i16 %add
  ret i16 %add

}
}




define <2 x i16> @halfinsts_add_v2i16(<2 x i16> %arg0) #1 {
define <2 x i16> @halfinsts_add_v2i16(<2 x i16> %arg0) #1 {

  ; CHECK-LABEL: name: halfinsts_add_v2i16
  ; CHECK-LABEL: name: halfinsts_add_v2i16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
  ; CHECK:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY4]]
  ; CHECK:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
  ; CHECK:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)

  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)

  ; CHECK:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY5]], [[COPY6]]
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)

  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
  ; CHECK:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]

  ; CHECK:   [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; CHECK:   $vgpr0 = COPY [[COPY7]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

  ; CHECK:   $vgpr1 = COPY [[COPY8]](s32)
  ; CHECK:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)

  ; CHECK:   S_SETPC_B64_return [[COPY9]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)

  ; CHECK:   $vgpr0 = COPY [[COPY6]](s32)

  ; CHECK:   $vgpr1 = COPY [[COPY7]](s32)

  ; CHECK:   [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]

  ; CHECK:   S_SETPC_B64_return [[COPY8]], implicit $vgpr0, implicit $vgpr1

  %add = add <2 x i16> %arg0, %arg0
  %add = add <2 x i16> %arg0, %arg0

  ret <2 x i16> %add
  ret <2 x i16> %add

}
}




attributes #0 = { "target-features"="+vop3p" }
attributes #0 = { "target-features"="+vop3p" }

attributes #0 = { "target-features"="+16-bit-insts" }
attributes #0 = { "target-features"="+16-bit-insts" }

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
Show First 20 Lines • Show All 400 Lines • ▼ Show 20 Lines; GFX89-NEXT:    s_setpc_b64 s[30:31]

  %fdiv = fdiv arcp half %a, %b, !fpmath !0
  %fdiv = fdiv arcp half %a, %b, !fpmath !0

  ret half %fdiv
  ret half %fdiv

}
}




define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) {
define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) {

; GFX6-IEEE-LABEL: v_fdiv_v2f16:
; GFX6-IEEE-LABEL: v_fdiv_v2f16:

; GFX6-IEEE:       ; %bb.0:
; GFX6-IEEE:       ; %bb.0:

; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v3, v1

; GFX6-IEEE-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; GFX6-IEEE-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v3, v3, v2

; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0

; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4

; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v2, v3, v2

; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0

; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5

; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5

; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7

; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v6, v0

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
; GFX6-IEEE-NEXT:    v_div_fmas_f32 v0, v4, v5, v7

; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v3, v3, v1
; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v0, v3, v2

; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v2

; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v3, v1

; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2

; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v6, v1, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v2, v6, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0

; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3

; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v6, v5
; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v2, v5, v4

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v3, v5

; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, v6

; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX6-FLUSH-LABEL: v_fdiv_v2f16:
; GFX6-FLUSH-LABEL: v_fdiv_v2f16:

; GFX6-FLUSH:       ; %bb.0:
; GFX6-FLUSH:       ; %bb.0:

; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v3, v1

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
; GFX6-FLUSH-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-FLUSH-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v3, v3, v2

; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4
; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v6, vcc, v2, v3, v2

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0

; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v7, v5, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v7, v5, v5

; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5
; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5

; GFX6-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, v8, v5, v7
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, v8, v5, v7

; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v3, v3

; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v5, v0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v3, v2

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0

; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v3, v3, v1
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v5

; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v2
; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v1, v3, v1
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, v5, v1, v5

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.0

; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v3

; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v4, v3

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v4

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v6

; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v4

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0

; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v6

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, v5

; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_fdiv_v2f16:
; GFX8-LABEL: v_fdiv_v2f16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v1

; GFX8-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX8-NEXT:    v_cvt_f32_f16_e32 v2, v1

Show All 38 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fdiv = fdiv <2 x half> %a, %b
  %fdiv = fdiv <2 x half> %a, %b

  ret <2 x half> %fdiv
  ret <2 x half> %fdiv

}
}




define <2 x half> @v_fdiv_v2f16_afn(<2 x half> %a, <2 x half> %b) {
define <2 x half> @v_fdiv_v2f16_afn(<2 x half> %a, <2 x half> %b) {

; GFX6-LABEL: v_fdiv_v2f16_afn:
; GFX6-LABEL: v_fdiv_v2f16_afn:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_rcp_f32_e32 v2, v2
; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_rcp_f32_e32 v3, v3
; GFX6-NEXT:    v_rcp_f32_e32 v3, v3

; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v2
; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_mul_f32_e32 v1, v1, v3
; GFX6-NEXT:    v_rcp_f32_e32 v1, v1

; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v3

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_fdiv_v2f16_afn:
; GFX8-LABEL: v_fdiv_v2f16_afn:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_rcp_f16_e32 v2, v1
; GFX8-NEXT:    v_rcp_f16_e32 v2, v1

; GFX8-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1

Show All 17 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fdiv = fdiv afn <2 x half> %a, %b
  %fdiv = fdiv afn <2 x half> %a, %b

  ret <2 x half> %fdiv
  ret <2 x half> %fdiv

}
}




define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {
define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {

; GFX6-IEEE-LABEL: v_fdiv_v2f16_ulp25:
; GFX6-IEEE-LABEL: v_fdiv_v2f16_ulp25:

; GFX6-IEEE:       ; %bb.0:
; GFX6-IEEE:       ; %bb.0:

; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v3, v1

; GFX6-IEEE-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; GFX6-IEEE-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v3, v3, v2

; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0

; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4

; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v2, v3, v2

; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0

; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5

; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5

; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7

; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v6, v0

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
; GFX6-IEEE-NEXT:    v_div_fmas_f32 v0, v4, v5, v7

; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v3, v3, v1
; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v0, v3, v2

; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v2

; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v3, v1

; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2

; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v6, v1, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v2, v6, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0

; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3

; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v6, v5
; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v2, v5, v4

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v3, v5

; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, v6

; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX6-FLUSH-LABEL: v_fdiv_v2f16_ulp25:
; GFX6-FLUSH-LABEL: v_fdiv_v2f16_ulp25:

; GFX6-FLUSH:       ; %bb.0:
; GFX6-FLUSH:       ; %bb.0:

; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v3, v1

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
; GFX6-FLUSH-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-FLUSH-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v3, v3, v2

; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4
; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v6, vcc, v2, v3, v2

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0

; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v7, v5, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v7, v5, v5

; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5
; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5

; GFX6-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, v8, v5, v7
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, v8, v5, v7

; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v3, v3

; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v5, v0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v3, v2

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0

; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v3, v3, v1
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v5

; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v2
; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v1, v3, v1
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, v5, v1, v5

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.0

; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v3

; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v4, v3

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v4

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v6

; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v4

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0

; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v6

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, v5

; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_fdiv_v2f16_ulp25:
; GFX8-LABEL: v_fdiv_v2f16_ulp25:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v1

; GFX8-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX8-NEXT:    v_cvt_f32_f16_e32 v2, v1

Show All 38 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fdiv = fdiv <2 x half> %a, %b, !fpmath !0
  %fdiv = fdiv <2 x half> %a, %b, !fpmath !0

  ret <2 x half> %fdiv
  ret <2 x half> %fdiv

}
}




define <2 x half> @v_rcp_v2f16(<2 x half> %x) {
define <2 x half> @v_rcp_v2f16(<2 x half> %x) {

; GFX6-IEEE-LABEL: v_rcp_v2f16:
; GFX6-IEEE-LABEL: v_rcp_v2f16:

; GFX6-IEEE:       ; %bb.0:
; GFX6-IEEE:       ; %bb.0:

; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, 1.0
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, 1.0

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-IEEE-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v2
; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v2, v2, v1

; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3

; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v2, v0, v2
; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v2, v1

; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0

; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4

; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4

; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5

; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v5, v0

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v2
; GFX6-IEEE-NEXT:    v_div_fmas_f32 v0, v3, v4, v6

; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v2
; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v0, v2, v1

; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3

; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v2, v1, v2

; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v5, v5, v1

; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2

; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v1, v5, v1

; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v3, 1.0

; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v3, v6, v3, v3

; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v4, v3

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v2, v6, v4

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, v2
; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v3, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v6, v4

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v6

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v5, v1

; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX6-FLUSH-LABEL: v_rcp_v2f16:
; GFX6-FLUSH-LABEL: v_rcp_v2f16:

; GFX6-FLUSH:       ; %bb.0:
; GFX6-FLUSH:       ; %bb.0:

; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-FLUSH-NEXT:    s_movk_i32 s6, 0x3c00
; GFX6-FLUSH-NEXT:    s_movk_i32 s6, 0x3c00

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, s6
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, s6

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v2
; GFX6-FLUSH-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v2, v2, v1

; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3
; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v2, v0, v2
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v1, v2, v1

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v4, 1.0

; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v4

; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v4

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v3, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v3, v6, v5

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6

; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v5

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0

; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v5, v0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, s6
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, s6

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v3, v2, v1

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v3, v0, v2

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0

; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v4
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v1, s[4:5], v5, v5, v4

; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v4, v1, v4
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, v4, v5, v4

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.0
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v1, v2, 1.0

; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v3
; GFX6-FLUSH-NEXT:    v_fma_f32 v2, v6, v2, v2

; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v3
; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v3, v2

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v1, v6, v3

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v2, v6

; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v1, -v1, v6, v3

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0

; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v6
; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v6

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, v4
; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v1, v5, v4

; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_rcp_v2f16:
; GFX8-LABEL: v_rcp_v2f16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX8-NEXT:    v_cvt_f32_f16_e32 v1, v0
; GFX8-NEXT:    v_cvt_f32_f16_e32 v1, v0

Show All 34 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x
  %fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x

  ret <2 x half> %fdiv
  ret <2 x half> %fdiv

}
}




define <2 x half> @v_rcp_v2f16_arcp(<2 x half> %x) {
define <2 x half> @v_rcp_v2f16_arcp(<2 x half> %x) {

; GFX6-IEEE-LABEL: v_rcp_v2f16_arcp:
; GFX6-IEEE-LABEL: v_rcp_v2f16_arcp:

; GFX6-IEEE:       ; %bb.0:
; GFX6-IEEE:       ; %bb.0:

; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, 1.0
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, 1.0

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-IEEE-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v2
; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v2, v2, v1

; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3

; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v2, v0, v2
; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v2, v1

; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0

; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4

; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4

; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5

; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v5, v0

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v2
; GFX6-IEEE-NEXT:    v_div_fmas_f32 v0, v3, v4, v6

; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v2
; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v0, v2, v1

; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3

; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v2, v1, v2

; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v5, v5, v1

; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2

; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v1, v5, v1

; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v3, 1.0

; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v3, v6, v3, v3

; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v4, v3

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v2, v6, v4

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, v2
; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v3, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v6, v4

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v6

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v5, v1

; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX6-FLUSH-LABEL: v_rcp_v2f16_arcp:
; GFX6-FLUSH-LABEL: v_rcp_v2f16_arcp:

; GFX6-FLUSH:       ; %bb.0:
; GFX6-FLUSH:       ; %bb.0:

; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-FLUSH-NEXT:    s_movk_i32 s6, 0x3c00
; GFX6-FLUSH-NEXT:    s_movk_i32 s6, 0x3c00

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, s6
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, s6

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v2
; GFX6-FLUSH-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v2, v2, v1

; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3
; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v2, v0, v2
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v1, v2, v1

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v4, 1.0

; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v4

; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v4

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v3, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v3, v6, v5

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6

; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v5

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0

; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v5, v0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, s6
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, s6

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v3, v2, v1

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v3, v0, v2

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0

; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v4
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v1, s[4:5], v5, v5, v4

; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v4, v1, v4
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, v4, v5, v4

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.0
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v1, v2, 1.0

; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v3
; GFX6-FLUSH-NEXT:    v_fma_f32 v2, v6, v2, v2

; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v3
; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v3, v2

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v1, v6, v3

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v2, v6

; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v1, -v1, v6, v3

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0

; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v6
; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v6

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, v4
; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v1, v5, v4

; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_rcp_v2f16_arcp:
; GFX8-LABEL: v_rcp_v2f16_arcp:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX8-NEXT:    v_cvt_f32_f16_e32 v1, v0
; GFX8-NEXT:    v_cvt_f32_f16_e32 v1, v0

Show All 34 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fdiv = fdiv arcp <2 x half> <half 1.0, half 1.0>, %x
  %fdiv = fdiv arcp <2 x half> <half 1.0, half 1.0>, %x

  ret <2 x half> %fdiv
  ret <2 x half> %fdiv

}
}




define <2 x half> @v_rcp_v2f16_arcp_afn(<2 x half> %x) {
define <2 x half> @v_rcp_v2f16_arcp_afn(<2 x half> %x) {

; GFX6-LABEL: v_rcp_v2f16_arcp_afn:
; GFX6-LABEL: v_rcp_v2f16_arcp_afn:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, 1.0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, 1.0

; GFX6-NEXT:    v_rcp_f32_e32 v0, v0

; GFX6-NEXT:    v_rcp_f32_e32 v1, v1
; GFX6-NEXT:    v_rcp_f32_e32 v1, v1

; GFX6-NEXT:    v_mul_f32_e32 v0, v2, v0
; GFX6-NEXT:    v_rcp_f32_e32 v3, v0

; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
; GFX6-NEXT:    v_mul_f32_e32 v0, v2, v1

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v3

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_rcp_v2f16_arcp_afn:
; GFX8-LABEL: v_rcp_v2f16_arcp_afn:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT:    v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1

; GFX8-NEXT:    v_rcp_f16_e32 v0, v0
; GFX8-NEXT:    v_rcp_f16_e32 v0, v0

Show All 13 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fdiv = fdiv arcp afn <2 x half> <half 1.0, half 1.0>, %x
  %fdiv = fdiv arcp afn <2 x half> <half 1.0, half 1.0>, %x

  ret <2 x half> %fdiv
  ret <2 x half> %fdiv

}
}




define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {
define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {

; GFX6-IEEE-LABEL: v_rcp_v2f16_ulp25:
; GFX6-IEEE-LABEL: v_rcp_v2f16_ulp25:

; GFX6-IEEE:       ; %bb.0:
; GFX6-IEEE:       ; %bb.0:

; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, 1.0
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, 1.0

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-IEEE-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v2
; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v2, v2, v1

; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3

; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v2, v0, v2
; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v2, v1

; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0

; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4

; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4

; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5

; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v5, v0

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v2
; GFX6-IEEE-NEXT:    v_div_fmas_f32 v0, v3, v4, v6

; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v2
; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v0, v2, v1

; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3

; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v2, v1, v2

; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v5, v5, v1

; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2

; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v1, v5, v1

; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v3, 1.0

; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v3, v6, v3, v3

; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v4, v3

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v2, v6, v4

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, v2
; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v3, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v6, v4

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v6

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v5, v1

; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX6-FLUSH-LABEL: v_rcp_v2f16_ulp25:
; GFX6-FLUSH-LABEL: v_rcp_v2f16_ulp25:

; GFX6-FLUSH:       ; %bb.0:
; GFX6-FLUSH:       ; %bb.0:

; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-FLUSH-NEXT:    s_movk_i32 s6, 0x3c00
; GFX6-FLUSH-NEXT:    s_movk_i32 s6, 0x3c00

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, s6
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, s6

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v2
; GFX6-FLUSH-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v2, v2, v1

; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3
; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v2, v0, v2
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v1, v2, v1

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v4, 1.0

; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v4

; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v4

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v3, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v3, v6, v5

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6

; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v5

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0

; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v5, v0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, s6
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, s6

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v3, v2, v1

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v3, v0, v2

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0

; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v4
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v1, s[4:5], v5, v5, v4

; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v4, v1, v4
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, v4, v5, v4

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.0
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v1, v2, 1.0

; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v3
; GFX6-FLUSH-NEXT:    v_fma_f32 v2, v6, v2, v2

; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v3
; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v3, v2

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v1, v6, v3

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v2, v6

; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v1, -v1, v6, v3

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0

; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v6
; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v6

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, v4
; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v1, v5, v4

; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_rcp_v2f16_ulp25:
; GFX8-LABEL: v_rcp_v2f16_ulp25:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT:    v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1

; GFX8-NEXT:    v_rcp_f16_e32 v0, v0
; GFX8-NEXT:    v_rcp_f16_e32 v0, v0

Show All 13 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x, !fpmath !0
  %fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x, !fpmath !0

  ret <2 x half> %fdiv
  ret <2 x half> %fdiv

}
}




define <2 x half> @v_fdiv_v2f16_afn_ulp25(<2 x half> %a, <2 x half> %b) {
define <2 x half> @v_fdiv_v2f16_afn_ulp25(<2 x half> %a, <2 x half> %b) {

; GFX6-LABEL: v_fdiv_v2f16_afn_ulp25:
; GFX6-LABEL: v_fdiv_v2f16_afn_ulp25:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_rcp_f32_e32 v2, v2
; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_rcp_f32_e32 v3, v3
; GFX6-NEXT:    v_rcp_f32_e32 v3, v3

; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v2
; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_mul_f32_e32 v1, v1, v3
; GFX6-NEXT:    v_rcp_f32_e32 v1, v1

; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v3

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_fdiv_v2f16_afn_ulp25:
; GFX8-LABEL: v_fdiv_v2f16_afn_ulp25:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_rcp_f16_e32 v2, v1
; GFX8-NEXT:    v_rcp_f16_e32 v2, v1

; GFX8-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1

Show All 17 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fdiv = fdiv afn <2 x half> %a, %b, !fpmath !0
  %fdiv = fdiv afn <2 x half> %a, %b, !fpmath !0

  ret <2 x half> %fdiv
  ret <2 x half> %fdiv

}
}




define <2 x half> @v_fdiv_v2f16_arcp_ulp25(<2 x half> %a, <2 x half> %b) {
define <2 x half> @v_fdiv_v2f16_arcp_ulp25(<2 x half> %a, <2 x half> %b) {

; GFX6-IEEE-LABEL: v_fdiv_v2f16_arcp_ulp25:
; GFX6-IEEE-LABEL: v_fdiv_v2f16_arcp_ulp25:

; GFX6-IEEE:       ; %bb.0:
; GFX6-IEEE:       ; %bb.0:

; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v3, v1

; GFX6-IEEE-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; GFX6-IEEE-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v3, v3, v2

; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0

; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4

; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v2, v3, v2

; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0

; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5

; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5

; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7

; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v6, v0

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
; GFX6-IEEE-NEXT:    v_div_fmas_f32 v0, v4, v5, v7

; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v3, v3, v1
; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v0, v3, v2

; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v2

; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v3, v1

; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2

; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v6, v1, v6

; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v2, v6, v5
; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0

; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3

; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v6, v5
; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v2, v5, v4

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v3, v5

; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4

; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5

; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, v6

; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX6-FLUSH-LABEL: v_fdiv_v2f16_arcp_ulp25:
; GFX6-FLUSH-LABEL: v_fdiv_v2f16_arcp_ulp25:

; GFX6-FLUSH:       ; %bb.0:
; GFX6-FLUSH:       ; %bb.0:

; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v3, v1

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
; GFX6-FLUSH-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-FLUSH-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v3, v3, v2

; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4
; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v6, vcc, v2, v3, v2

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0

; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v7, v5, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v7, v5, v5

; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5
; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5

; GFX6-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, v8, v5, v7
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, v8, v5, v7

; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v3, v3

; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v5, v0

; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v3, v2

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0

; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v3, v3, v1
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v5

; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v2
; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2

; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v1, v3, v1
; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, v5, v1, v5

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.0

; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v4
; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v3

; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v4
; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v4, v3

; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v4

; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v6

; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v5
; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v4

; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0

; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v6

; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, v5

; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_fdiv_v2f16_arcp_ulp25:
; GFX8-LABEL: v_fdiv_v2f16_arcp_ulp25:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v1

; GFX8-NEXT:    v_cvt_f32_f16_e32 v2, v1
; GFX8-NEXT:    v_cvt_f32_f16_e32 v2, v1

Show All 38 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fdiv = fdiv arcp <2 x half> %a, %b, !fpmath !0
  %fdiv = fdiv arcp <2 x half> %a, %b, !fpmath !0

  ret <2 x half> %fdiv
  ret <2 x half> %fdiv

}
}




define <2 x half> @v_fdiv_v2f16_arcp_afn_ulp25(<2 x half> %a, <2 x half> %b) {
define <2 x half> @v_fdiv_v2f16_arcp_afn_ulp25(<2 x half> %a, <2 x half> %b) {

; GFX6-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
; GFX6-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_rcp_f32_e32 v2, v2
; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_rcp_f32_e32 v3, v3
; GFX6-NEXT:    v_rcp_f32_e32 v3, v3

; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v2
; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_mul_f32_e32 v1, v1, v3
; GFX6-NEXT:    v_rcp_f32_e32 v1, v1

; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v3

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
; GFX8-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_rcp_f16_e32 v2, v1
; GFX8-NEXT:    v_rcp_f16_e32 v2, v1

; GFX8-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1

Show All 22 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fma = call half @llvm.fma.f16(half %x, half %y, half %z)
  %fma = call half @llvm.fma.f16(half %x, half %y, half %z)

  ret half %fma
  ret half %fma

}
}




define <2 x half> @v_fma_v2f16(<2 x half> %x, <2 x half> %y, <2 x half> %z) {
define <2 x half> @v_fma_v2f16(<2 x half> %x, <2 x half> %y, <2 x half> %z) {

; GFX6-LABEL: v_fma_v2f16:
; GFX6-LABEL: v_fma_v2f16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 16, v1

; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 16, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v4, v4

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3

; GFX6-NEXT:    v_cvt_f32_f16_e32 v4, v4

; GFX6-NEXT:    v_cvt_f32_f16_e32 v5, v5
; GFX6-NEXT:    v_cvt_f32_f16_e32 v5, v5

; GFX6-NEXT:    v_fma_f32 v0, v0, v2, v4
; GFX6-NEXT:    v_fma_f32 v0, v0, v1, v2

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_fma_f32 v1, v1, v3, v5
; GFX6-NEXT:    v_fma_f32 v1, v3, v4, v5

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_fma_v2f16:
; GFX8-LABEL: v_fma_v2f16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 16, v0

; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v1

Show All 13 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fma = call <2 x half> @llvm.fma.v2f16(<2 x half> %x, <2 x half> %y, <2 x half> %z)
  %fma = call <2 x half> @llvm.fma.v2f16(<2 x half> %x, <2 x half> %y, <2 x half> %z)

  ret <2 x half> %fma
  ret <2 x half> %fma

}
}




define <2 x half> @v_fma_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y, <2 x half> %z) {
define <2 x half> @v_fma_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y, <2 x half> %z) {

; GFX6-LABEL: v_fma_v2f16_fneg_lhs:
; GFX6-LABEL: v_fma_v2f16_fneg_lhs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0

; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0

; GFX6-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
; GFX6-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 16, v1

; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 16, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v4, v4

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3

; GFX6-NEXT:    v_cvt_f32_f16_e32 v4, v4

; GFX6-NEXT:    v_cvt_f32_f16_e32 v5, v5
; GFX6-NEXT:    v_cvt_f32_f16_e32 v5, v5

; GFX6-NEXT:    v_fma_f32 v0, v0, v2, v4
; GFX6-NEXT:    v_fma_f32 v0, v0, v1, v2

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_fma_f32 v1, v1, v3, v5
; GFX6-NEXT:    v_fma_f32 v1, v3, v4, v5

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_fma_v2f16_fneg_lhs:
; GFX8-LABEL: v_fma_v2f16_fneg_lhs:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
; GFX8-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0

; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 16, v0

Show All 15 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fma = call <2 x half> @llvm.fma.v2f16(<2 x half> %x.fneg, <2 x half> %y, <2 x half> %z)
  %fma = call <2 x half> @llvm.fma.v2f16(<2 x half> %x.fneg, <2 x half> %y, <2 x half> %z)

  ret <2 x half> %fma
  ret <2 x half> %fma

}
}




define <2 x half> @v_fma_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y, <2 x half> %z) {
define <2 x half> @v_fma_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y, <2 x half> %z) {

; GFX6-LABEL: v_fma_v2f16_fneg_rhs:
; GFX6-LABEL: v_fma_v2f16_fneg_rhs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT:    v_xor_b32_e32 v1, 0x80008000, v1

; GFX6-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v0

; GFX6-NEXT:    v_or_b32_e32 v2, v3, v2
; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 16, v1

; GFX6-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 16, v2

; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v4, v4

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3

; GFX6-NEXT:    v_cvt_f32_f16_e32 v4, v4

; GFX6-NEXT:    v_cvt_f32_f16_e32 v5, v5
; GFX6-NEXT:    v_cvt_f32_f16_e32 v5, v5

; GFX6-NEXT:    v_fma_f32 v0, v0, v2, v4
; GFX6-NEXT:    v_fma_f32 v0, v0, v1, v2

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_fma_f32 v1, v1, v3, v5
; GFX6-NEXT:    v_fma_f32 v1, v3, v4, v5

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_fma_v2f16_fneg_rhs:
; GFX8-LABEL: v_fma_v2f16_fneg_rhs:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_xor_b32_e32 v1, 0x80008000, v1
; GFX8-NEXT:    v_xor_b32_e32 v1, 0x80008000, v1

; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 16, v0

Show All 15 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %fma = call <2 x half> @llvm.fma.v2f16(<2 x half> %x, <2 x half> %y.fneg, <2 x half> %z)
  %fma = call <2 x half> @llvm.fma.v2f16(<2 x half> %x, <2 x half> %y.fneg, <2 x half> %z)

  ret <2 x half> %fma
  ret <2 x half> %fma

}
}




define <2 x half> @v_fma_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y, <2 x half> %z) {
define <2 x half> @v_fma_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y, <2 x half> %z) {

; GFX6-LABEL: v_fma_v2f16_fneg_lhs_rhs:
; GFX6-LABEL: v_fma_v2f16_fneg_lhs_rhs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_mov_b32_e32 v6, 0xffff

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_and_b32_e32 v0, v0, v6

; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v3

; GFX6-NEXT:    v_and_b32_e32 v2, v2, v6

; GFX6-NEXT:    s_mov_b32 s4, 0x80008000
; GFX6-NEXT:    s_mov_b32 s4, 0x80008000

; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2

; GFX6-NEXT:    v_xor_b32_e32 v0, s4, v0
; GFX6-NEXT:    v_xor_b32_e32 v0, s4, v0

; GFX6-NEXT:    v_xor_b32_e32 v1, s4, v1
; GFX6-NEXT:    v_xor_b32_e32 v1, s4, v1

; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 16, v1

; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 16, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v4, v4

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3

; GFX6-NEXT:    v_cvt_f32_f16_e32 v4, v4

; GFX6-NEXT:    v_cvt_f32_f16_e32 v5, v5
; GFX6-NEXT:    v_cvt_f32_f16_e32 v5, v5

; GFX6-NEXT:    v_fma_f32 v0, v0, v1, v4
; GFX6-NEXT:    v_fma_f32 v0, v0, v1, v2

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_fma_f32 v1, v2, v3, v5
; GFX6-NEXT:    v_fma_f32 v1, v3, v4, v5

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_fma_v2f16_fneg_lhs_rhs:
; GFX8-LABEL: v_fma_v2f16_fneg_lhs_rhs:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    s_mov_b32 s4, 0x80008000
; GFX8-NEXT:    s_mov_b32 s4, 0x80008000

; GFX8-NEXT:    v_xor_b32_e32 v0, s4, v0
; GFX8-NEXT:    v_xor_b32_e32 v0, s4, v0

▲ Show 20 Lines • Show All 373 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %pow = call half @llvm.pow.f16(half %x, half %y)
  %pow = call half @llvm.pow.f16(half %x, half %y)

  ret half %pow
  ret half %pow

}
}




define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {

; GFX6-LABEL: v_pow_v2f16:
; GFX6-LABEL: v_pow_v2f16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_log_f32_e32 v0, v0
; GFX6-NEXT:    v_log_f32_e32 v0, v0

; GFX6-NEXT:    v_log_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3

; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v2
; GFX6-NEXT:    v_log_f32_e32 v2, v2

; GFX6-NEXT:    v_mul_legacy_f32_e32 v1, v1, v3
; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1

; GFX6-NEXT:    v_exp_f32_e32 v0, v0
; GFX6-NEXT:    v_exp_f32_e32 v0, v0

; GFX6-NEXT:    v_mul_legacy_f32_e32 v1, v2, v3

; GFX6-NEXT:    v_exp_f32_e32 v1, v1
; GFX6-NEXT:    v_exp_f32_e32 v1, v1

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_pow_v2f16:
; GFX8-LABEL: v_pow_v2f16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

Show All 35 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y)
  %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y)

  ret <2 x half> %pow
  ret <2 x half> %pow

}
}




define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {

; GFX6-LABEL: v_pow_v2f16_fneg_lhs:
; GFX6-LABEL: v_pow_v2f16_fneg_lhs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0

; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0

; GFX6-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
; GFX6-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v0
; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_log_f32_e32 v1, v1
; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_log_f32_e32 v0, v0
; GFX6-NEXT:    v_log_f32_e32 v0, v0

; GFX6-NEXT:    v_mul_legacy_f32_e32 v1, v1, v2
; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3

; GFX6-NEXT:    v_log_f32_e32 v2, v2

; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1

; GFX6-NEXT:    v_exp_f32_e32 v0, v0

; GFX6-NEXT:    v_mul_legacy_f32_e32 v1, v2, v3

; GFX6-NEXT:    v_exp_f32_e32 v1, v1
; GFX6-NEXT:    v_exp_f32_e32 v1, v1

; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v3
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_exp_f32_e32 v2, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v1

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v2

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_pow_v2f16_fneg_lhs:
; GFX8-LABEL: v_pow_v2f16_fneg_lhs:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
; GFX8-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0

; GFX8-NEXT:    v_log_f16_e32 v2, v0
; GFX8-NEXT:    v_log_f16_e32 v2, v0

; GFX8-NEXT:    v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT:    v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1

Show All 35 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y)
  %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y)

  ret <2 x half> %pow
  ret <2 x half> %pow

}
}




define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {

; GFX6-LABEL: v_pow_v2f16_fneg_rhs:
; GFX6-LABEL: v_pow_v2f16_fneg_rhs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v3

; GFX6-NEXT:    v_and_b32_e32 v2, 0xffff, v2

; GFX6-NEXT:    v_or_b32_e32 v2, v3, v2

; GFX6-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2

; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v2

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_xor_b32_e32 v1, 0x80008000, v1

; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_log_f32_e32 v0, v0
; GFX6-NEXT:    v_log_f32_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3

; GFX6-NEXT:    v_log_f32_e32 v1, v1
; GFX6-NEXT:    v_log_f32_e32 v2, v2

; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v2
; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1

; GFX6-NEXT:    v_exp_f32_e32 v0, v0
; GFX6-NEXT:    v_exp_f32_e32 v0, v0

; GFX6-NEXT:    v_mul_legacy_f32_e32 v1, v1, v3
; GFX6-NEXT:    v_mul_legacy_f32_e32 v1, v2, v3

; GFX6-NEXT:    v_exp_f32_e32 v1, v1
; GFX6-NEXT:    v_exp_f32_e32 v1, v1

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_pow_v2f16_fneg_rhs:
; GFX8-LABEL: v_pow_v2f16_fneg_rhs:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

Show All 38 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y.fneg)
  %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y.fneg)

  ret <2 x half> %pow
  ret <2 x half> %pow

}
}




define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {

; GFX6-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX6-LABEL: v_pow_v2f16_fneg_lhs_rhs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_mov_b32_e32 v4, 0xffff

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_and_b32_e32 v0, v0, v4

; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0

; GFX6-NEXT:    s_mov_b32 s4, 0x80008000
; GFX6-NEXT:    s_mov_b32 s4, 0x80008000

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v3

; GFX6-NEXT:    v_and_b32_e32 v2, v2, v4

; GFX6-NEXT:    v_xor_b32_e32 v0, s4, v0
; GFX6-NEXT:    v_xor_b32_e32 v0, s4, v0

; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2

; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2

; GFX6-NEXT:    v_xor_b32_e32 v1, s4, v1
; GFX6-NEXT:    v_xor_b32_e32 v1, s4, v1

; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1

; GFX6-NEXT:    v_log_f32_e32 v0, v0
; GFX6-NEXT:    v_log_f32_e32 v0, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3

▲ Show 20 Lines • Show All 295 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
Show First 20 Lines • Show All 1,188 Lines • ▼ Show 20 Lines



define <33 x i32> @v33i32_func_v33i32_i32(<33 x i32> addrspace(1)* %p, i32 %idx) #0 {
define <33 x i32> @v33i32_func_v33i32_i32(<33 x i32> addrspace(1)* %p, i32 %idx) #0 {

  ; CHECK-LABEL: name: v33i32_func_v33i32_i32
  ; CHECK-LABEL: name: v33i32_func_v33i32_i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY3]](s32)
  ; CHECK:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY3]](s32)

  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256
  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256

  ; CHECK:   [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
  ; CHECK:   [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]

  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[MUL]](s64)
  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[MUL]](s64)

  ; CHECK:   [[COPY5:%[0-9]+]]:_(p1) = COPY [[PTR_ADD]](p1)
  ; CHECK:   [[COPY5:%[0-9]+]]:_(p1) = COPY [[PTR_ADD]](p1)

  ; CHECK:   [[LOAD:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[COPY5]](p1) :: (load 132 from %ir.gep, align 256, addrspace 1)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[COPY5]](p1) :: (load 132 from %ir.gep, align 256, addrspace 1)

  ; CHECK:   G_STORE [[LOAD]](<33 x s32>), [[COPY]](p5) :: (store 132, align 256, addrspace 5)
  ; CHECK:   G_STORE [[LOAD]](<33 x s32>), [[COPY]](p5) :: (store 132, align 256, addrspace 5)

  ; CHECK:   [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

▲ Show 20 Lines • Show All 303 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.a16.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s




define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, i16 %s) {
define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, i16 %s) {

  ; GFX9-LABEL: name: load_mip_1d
  ; GFX9-LABEL: name: load_mip_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[DEF]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: load_mip_1d
  ; GFX10-LABEL: name: load_mip_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, i16 %s, i16 %t) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: load_mip_2d
  ; GFX10-LABEL: name: load_mip_2d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %u) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 9 Linesdefine amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %u) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, i16 %s, i16 %t) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: load_mip_1darray
  ; GFX10-LABEL: name: load_mip_1darray

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %u) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 9 Linesdefine amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %u) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %u) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 9 Linesdefine amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %u) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i16 %s) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10-LABEL: name: store_mip_1d
  ; GFX10-LABEL: name: store_mip_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)

  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX10:   S_ENDPGM 0
  ; GFX10:   S_ENDPGM 0

main_body:
main_body:

  call void @llvm.amdgcn.image.store.mip.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 0, <8 x i32> %rsrc, i32 0, i32 0)
  call void @llvm.amdgcn.image.store.mip.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 0, <8 x i32> %rsrc, i32 0, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i16 %s, i16 %t) {
define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i16 %s, i16 %t) {

  ; GFX9-LABEL: name: store_mip_2d
  ; GFX9-LABEL: name: store_mip_2d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10-LABEL: name: store_mip_2d
  ; GFX10-LABEL: name: store_mip_2d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX10:   S_ENDPGM 0
  ; GFX10:   S_ENDPGM 0

main_body:
main_body:

  call void @llvm.amdgcn.image.store.mip.2d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 0, <8 x i32> %rsrc, i32 0, i32 0)
  call void @llvm.amdgcn.image.store.mip.2d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 0, <8 x i32> %rsrc, i32 0, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i16 %s, i16 %t, i16 %u) {
define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i16 %s, i16 %t, i16 %u) {

  ; GFX9-LABEL: name: store_mip_3d
  ; GFX9-LABEL: name: store_mip_3d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10-LABEL: name: store_mip_3d
  ; GFX10-LABEL: name: store_mip_3d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

Show All 10 Linesdefine amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i16 %s, i16 %t) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10-LABEL: name: store_mip_1darray
  ; GFX10-LABEL: name: store_mip_1darray

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX10:   S_ENDPGM 0
  ; GFX10:   S_ENDPGM 0

main_body:
main_body:

  call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 0, <8 x i32> %rsrc, i32 0, i32 0)
  call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 0, <8 x i32> %rsrc, i32 0, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i16 %s, i16 %t, i16 %u) {
define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i16 %s, i16 %t, i16 %u) {

  ; GFX9-LABEL: name: store_mip_2darray
  ; GFX9-LABEL: name: store_mip_2darray

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10-LABEL: name: store_mip_2darray
  ; GFX10-LABEL: name: store_mip_2darray

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

Show All 10 Linesdefine amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, i16 %s, i16 %t, i16 %u) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10-LABEL: name: store_mip_cube
  ; GFX10-LABEL: name: store_mip_cube

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

Show All 21 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
Show First 20 Lines • Show All 2,878 Lines • ▼ Show 20 Lines
; GPRIDX-NEXT:    s_mov_b32 s23, s25
; GPRIDX-NEXT:    s_mov_b32 s23, s25

; GPRIDX-NEXT:    s_mov_b32 s24, s26
; GPRIDX-NEXT:    s_mov_b32 s24, s26

; GPRIDX-NEXT:    s_mov_b32 s25, s27
; GPRIDX-NEXT:    s_mov_b32 s25, s27

; GPRIDX-NEXT:    s_mov_b32 s26, s28
; GPRIDX-NEXT:    s_mov_b32 s26, s28

; GPRIDX-NEXT:    s_mov_b32 s27, s29
; GPRIDX-NEXT:    s_mov_b32 s27, s29

; GPRIDX-NEXT:    s_mov_b32 s28, s30
; GPRIDX-NEXT:    s_mov_b32 s28, s30

; GPRIDX-NEXT:    s_mov_b32 s29, s31
; GPRIDX-NEXT:    s_mov_b32 s29, s31

; GPRIDX-NEXT:    s_mov_b32 s31, s33
; GPRIDX-NEXT:    s_mov_b32 s31, s33

; GPRIDX-NEXT:    v_mov_b32_e32 v32, v0

; GPRIDX-NEXT:    s_mov_b32 s30, s32
; GPRIDX-NEXT:    s_mov_b32 s30, s32

; GPRIDX-NEXT:    v_mov_b32_e32 v32, v0

; GPRIDX-NEXT:    v_mov_b32_e32 v0, s0
; GPRIDX-NEXT:    v_mov_b32_e32 v0, s0

; GPRIDX-NEXT:    v_mov_b32_e32 v1, s1
; GPRIDX-NEXT:    v_mov_b32_e32 v1, s1

; GPRIDX-NEXT:    v_mov_b32_e32 v2, s2
; GPRIDX-NEXT:    v_mov_b32_e32 v2, s2

; GPRIDX-NEXT:    v_mov_b32_e32 v3, s3
; GPRIDX-NEXT:    v_mov_b32_e32 v3, s3

; GPRIDX-NEXT:    v_mov_b32_e32 v4, s4
; GPRIDX-NEXT:    v_mov_b32_e32 v4, s4

; GPRIDX-NEXT:    v_mov_b32_e32 v5, s5
; GPRIDX-NEXT:    v_mov_b32_e32 v5, s5

; GPRIDX-NEXT:    v_mov_b32_e32 v6, s6
; GPRIDX-NEXT:    v_mov_b32_e32 v6, s6

; GPRIDX-NEXT:    v_mov_b32_e32 v7, s7
; GPRIDX-NEXT:    v_mov_b32_e32 v7, s7

▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; MOVREL-NEXT:    s_mov_b32 s23, s25
; MOVREL-NEXT:    s_mov_b32 s23, s25

; MOVREL-NEXT:    s_mov_b32 s24, s26
; MOVREL-NEXT:    s_mov_b32 s24, s26

; MOVREL-NEXT:    s_mov_b32 s25, s27
; MOVREL-NEXT:    s_mov_b32 s25, s27

; MOVREL-NEXT:    s_mov_b32 s26, s28
; MOVREL-NEXT:    s_mov_b32 s26, s28

; MOVREL-NEXT:    s_mov_b32 s27, s29
; MOVREL-NEXT:    s_mov_b32 s27, s29

; MOVREL-NEXT:    s_mov_b32 s28, s30
; MOVREL-NEXT:    s_mov_b32 s28, s30

; MOVREL-NEXT:    s_mov_b32 s29, s31
; MOVREL-NEXT:    s_mov_b32 s29, s31

; MOVREL-NEXT:    s_mov_b32 s31, s33
; MOVREL-NEXT:    s_mov_b32 s31, s33

; MOVREL-NEXT:    v_mov_b32_e32 v32, v0

; MOVREL-NEXT:    s_mov_b32 s30, s32
; MOVREL-NEXT:    s_mov_b32 s30, s32

; MOVREL-NEXT:    v_mov_b32_e32 v32, v0

; MOVREL-NEXT:    v_mov_b32_e32 v0, s0
; MOVREL-NEXT:    v_mov_b32_e32 v0, s0

; MOVREL-NEXT:    s_mov_b32 m0, s34
; MOVREL-NEXT:    s_mov_b32 m0, s34

; MOVREL-NEXT:    v_mov_b32_e32 v1, s1
; MOVREL-NEXT:    v_mov_b32_e32 v1, s1

; MOVREL-NEXT:    v_mov_b32_e32 v2, s2
; MOVREL-NEXT:    v_mov_b32_e32 v2, s2

; MOVREL-NEXT:    v_mov_b32_e32 v3, s3
; MOVREL-NEXT:    v_mov_b32_e32 v3, s3

; MOVREL-NEXT:    v_mov_b32_e32 v4, s4
; MOVREL-NEXT:    v_mov_b32_e32 v4, s4

; MOVREL-NEXT:    v_mov_b32_e32 v5, s5
; MOVREL-NEXT:    v_mov_b32_e32 v5, s5

; MOVREL-NEXT:    v_mov_b32_e32 v6, s6
; MOVREL-NEXT:    v_mov_b32_e32 v6, s6

▲ Show 20 Lines • Show All 1,596 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
Show First 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
}
}




define amdgpu_gfx void @test_gfx_call_external_i32_func_i32_imm(i32 addrspace(1)* %out) #0 {
define amdgpu_gfx void @test_gfx_call_external_i32_func_i32_imm(i32 addrspace(1)* %out) #0 {

  ; GCN-LABEL: name: test_gfx_call_external_i32_func_i32_imm
  ; GCN-LABEL: name: test_gfx_call_external_i32_func_i32_imm

  ; GCN: bb.1 (%ir-block.0):
  ; GCN: bb.1 (%ir-block.0):

  ; GCN:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; GCN:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; GCN:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; GCN:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; GCN:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; GCN:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
  ; GCN:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42

  ; GCN:   ADJCALLSTACKUP 0, 0, implicit-def $scc
  ; GCN:   ADJCALLSTACKUP 0, 0, implicit-def $scc

  ; GCN:   [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_gfx_i32_func_i32
  ; GCN:   [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_gfx_i32_func_i32

  ; GCN:   $vgpr0 = COPY [[C]](s32)
  ; GCN:   $vgpr0 = COPY [[C]](s32)

  ; GCN:   [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
  ; GCN:   [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

  ; GCN:   $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY3]](<4 x s32>)
  ; GCN:   $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY3]](<4 x s32>)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_gfx_i32_func_i32, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_gfx_i32_func_i32, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr0

▲ Show 20 Lines • Show All 689 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_i48_func_void() #0 {

  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)
  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i48_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i48_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)

  ; GCN:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
  ; GCN:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[TRUNC]](s48), [[DEF]](p1) :: (volatile store 6 into `i48 addrspace(1)* undef`, align 8, addrspace 1)
  ; GCN:   G_STORE [[TRUNC]](s48), [[DEF]](p1) :: (volatile store 6 into `i48 addrspace(1)* undef`, align 8, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call i48 @external_i48_func_void()
  %val = call i48 @external_i48_func_void()

  store volatile i48 %val, i48 addrspace(1)* undef
  store volatile i48 %val, i48 addrspace(1)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_i48_zeroext_func_void() #0 {
define amdgpu_kernel void @test_call_external_i48_zeroext_func_void() #0 {

Show All 39 Linesdefine amdgpu_kernel void @test_call_external_i48_zeroext_func_void() #0 {

  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)
  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i48_zeroext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i48_zeroext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)

  ; GCN:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
  ; GCN:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s48)
  ; GCN:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s48)

  ; GCN:   G_STORE [[ZEXT]](s64), [[DEF]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[ZEXT]](s64), [[DEF]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call i48 @external_i48_zeroext_func_void()
  %val = call i48 @external_i48_zeroext_func_void()

  %ext = zext i48 %val to i64
  %ext = zext i48 %val to i64

  store volatile i64 %ext, i64 addrspace(1)* undef
  store volatile i64 %ext, i64 addrspace(1)* undef

  ret void
  ret void

}
}

▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_i48_signext_func_void() #0 {

  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)
  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i48_signext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i48_signext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)

  ; GCN:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
  ; GCN:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s48)
  ; GCN:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s48)

  ; GCN:   G_STORE [[SEXT]](s64), [[DEF]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[SEXT]](s64), [[DEF]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call i48 @external_i48_signext_func_void()
  %val = call i48 @external_i48_signext_func_void()

  %ext = sext i48 %val to i64
  %ext = sext i48 %val to i64

  store volatile i64 %ext, i64 addrspace(1)* undef
  store volatile i64 %ext, i64 addrspace(1)* undef

  ret void
  ret void

}
}

▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_i64_func_void() #0 {

  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)
  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[MV]](s64), [[DEF]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[MV]](s64), [[DEF]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call i64 @external_i64_func_void()
  %val = call i64 @external_i64_func_void()

  store volatile i64 %val, i64 addrspace(1)* undef
  store volatile i64 %val, i64 addrspace(1)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_p1_func_void() #0 {
define amdgpu_kernel void @test_call_external_p1_func_void() #0 {

Show All 39 Linesdefine amdgpu_kernel void @test_call_external_p1_func_void() #0 {

  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)
  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_p1_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_p1_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
  ; GCN:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[MV]](p1), [[DEF]](p1) :: (volatile store 8 into `i8 addrspace(1)* addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[MV]](p1), [[DEF]](p1) :: (volatile store 8 into `i8 addrspace(1)* addrspace(1)* undef`, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call i8 addrspace(1)* @external_p1_func_void()
  %val = call i8 addrspace(1)* @external_p1_func_void()

  store volatile i8 addrspace(1)* %val, i8 addrspace(1)* addrspace(1)* undef
  store volatile i8 addrspace(1)* %val, i8 addrspace(1)* addrspace(1)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v2p1_func_void() #0 {
define amdgpu_kernel void @test_call_external_v2p1_func_void() #0 {

▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_v2p1_func_void() #0 {

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2p1_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2p1_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
  ; GCN:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)

  ; GCN:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY23]](s32), [[COPY24]](s32)
  ; GCN:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY23]](s32), [[COPY24]](s32)

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)
  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[BUILD_VECTOR]](<2 x p1>), [[DEF]](p1) :: (volatile store 16 into `<2 x i8 addrspace(1)*> addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[BUILD_VECTOR]](<2 x p1>), [[DEF]](p1) :: (volatile store 16 into `<2 x i8 addrspace(1)*> addrspace(1)* undef`, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <2 x i8 addrspace(1)*> @external_v2p1_func_void()
  %val = call <2 x i8 addrspace(1)*> @external_v2p1_func_void()

  store volatile <2 x i8 addrspace(1)*> %val, <2 x i8 addrspace(1)*> addrspace(1)* undef
  store volatile <2 x i8 addrspace(1)*> %val, <2 x i8 addrspace(1)*> addrspace(1)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_p3_func_void() #0 {
define amdgpu_kernel void @test_call_external_p3_func_void() #0 {

▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_v2p3_func_void() #0 {

  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)
  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2p3_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2p3_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1

  ; GCN:   [[COPY21:%[0-9]+]]:_(p3) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(p3) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(p3) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(p3) = COPY $vgpr1

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY21]](p3), [[COPY22]](p3)
  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY21]](p3), [[COPY22]](p3)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[BUILD_VECTOR]](<2 x p3>), [[DEF]](p3) :: (volatile store 8 into `<2 x i8 addrspace(3)*> addrspace(3)* undef`, addrspace 3)
  ; GCN:   G_STORE [[BUILD_VECTOR]](<2 x p3>), [[DEF]](p3) :: (volatile store 8 into `<2 x i8 addrspace(3)*> addrspace(3)* undef`, addrspace 3)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <2 x i8 addrspace(3)*> @external_v2p3_func_void()
  %val = call <2 x i8 addrspace(3)*> @external_v2p3_func_void()

  store volatile <2 x i8 addrspace(3)*> %val, <2 x i8 addrspace(3)*> addrspace(3)* undef
  store volatile <2 x i8 addrspace(3)*> %val, <2 x i8 addrspace(3)*> addrspace(3)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_f16_func_void() #0 {
define amdgpu_kernel void @test_call_external_f16_func_void() #0 {

▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_f64_func_void() #0 {

  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)
  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_f64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_f64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[MV]](s64), [[DEF]](p1) :: (volatile store 8 into `double addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[MV]](s64), [[DEF]](p1) :: (volatile store 8 into `double addrspace(1)* undef`, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call double @external_f64_func_void()
  %val = call double @external_f64_func_void()

  store volatile double %val, double addrspace(1)* undef
  store volatile double %val, double addrspace(1)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v2f64_func_void() #0 {
define amdgpu_kernel void @test_call_external_v2f64_func_void() #0 {

▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_v2f64_func_void() #0 {

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2f64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2f64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)

  ; GCN:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY23]](s32), [[COPY24]](s32)
  ; GCN:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY23]](s32), [[COPY24]](s32)

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[BUILD_VECTOR]](<2 x s64>), [[DEF]](p1) :: (volatile store 16 into `<2 x double> addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[BUILD_VECTOR]](<2 x s64>), [[DEF]](p1) :: (volatile store 16 into `<2 x double> addrspace(1)* undef`, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <2 x double> @external_v2f64_func_void()
  %val = call <2 x double> @external_v2f64_func_void()

  store volatile <2 x double> %val, <2 x double> addrspace(1)* undef
  store volatile <2 x double> %val, <2 x double> addrspace(1)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v2i32_func_void() #0 {
define amdgpu_kernel void @test_call_external_v2i32_func_void() #0 {

Show All 39 Linesdefine amdgpu_kernel void @test_call_external_v2i32_func_void() #0 {

  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)
  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32)
  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[BUILD_VECTOR]](<2 x s32>), [[DEF]](p1) :: (volatile store 8 into `<2 x i32> addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[BUILD_VECTOR]](<2 x s32>), [[DEF]](p1) :: (volatile store 8 into `<2 x i32> addrspace(1)* undef`, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <2 x i32> @external_v2i32_func_void()
  %val = call <2 x i32> @external_v2i32_func_void()

  store volatile <2 x i32> %val, <2 x i32> addrspace(1)* undef
  store volatile <2 x i32> %val, <2 x i32> addrspace(1)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v3i32_func_void() #0 {
define amdgpu_kernel void @test_call_external_v3i32_func_void() #0 {

Show All 40 Linesdefine amdgpu_kernel void @test_call_external_v3i32_func_void() #0 {

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32)
  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[BUILD_VECTOR]](<3 x s32>), [[DEF]](p1) :: (volatile store 12 into `<3 x i32> addrspace(1)* undef`, align 8, addrspace 1)
  ; GCN:   G_STORE [[BUILD_VECTOR]](<3 x s32>), [[DEF]](p1) :: (volatile store 12 into `<3 x i32> addrspace(1)* undef`, align 8, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <3 x i32> @external_v3i32_func_void()
  %val = call <3 x i32> @external_v3i32_func_void()

  store volatile <3 x i32> %val, <3 x i32> addrspace(1)* undef, align 8
  store volatile <3 x i32> %val, <3 x i32> addrspace(1)* undef, align 8

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v4i32_func_void() #0 {
define amdgpu_kernel void @test_call_external_v4i32_func_void() #0 {

▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_v4i32_func_void() #0 {

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v4i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v4i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32)
  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[BUILD_VECTOR]](<4 x s32>), [[DEF]](p1) :: (volatile store 16 into `<4 x i32> addrspace(1)* undef`, align 8, addrspace 1)
  ; GCN:   G_STORE [[BUILD_VECTOR]](<4 x s32>), [[DEF]](p1) :: (volatile store 16 into `<4 x i32> addrspace(1)* undef`, align 8, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <4 x i32> @external_v4i32_func_void()
  %val = call <4 x i32> @external_v4i32_func_void()

  store volatile <4 x i32> %val, <4 x i32> addrspace(1)* undef, align 8
  store volatile <4 x i32> %val, <4 x i32> addrspace(1)* undef, align 8

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v5i32_func_void() #0 {
define amdgpu_kernel void @test_call_external_v5i32_func_void() #0 {

▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_v5i32_func_void() #0 {

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v5i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v5i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GCN:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GCN:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32)
  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[BUILD_VECTOR]](<5 x s32>), [[DEF]](p1) :: (volatile store 20 into `<5 x i32> addrspace(1)* undef`, align 8, addrspace 1)
  ; GCN:   G_STORE [[BUILD_VECTOR]](<5 x s32>), [[DEF]](p1) :: (volatile store 20 into `<5 x i32> addrspace(1)* undef`, align 8, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <5 x i32> @external_v5i32_func_void()
  %val = call <5 x i32> @external_v5i32_func_void()

  store volatile <5 x i32> %val, <5 x i32> addrspace(1)* undef, align 8
  store volatile <5 x i32> %val, <5 x i32> addrspace(1)* undef, align 8

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v8i32_func_void() #0 {
define amdgpu_kernel void @test_call_external_v8i32_func_void() #0 {

▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_v8i32_func_void() #0 {

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GCN:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GCN:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GCN:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GCN:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GCN:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GCN:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GCN:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GCN:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32)
  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[BUILD_VECTOR]](<8 x s32>), [[DEF]](p1) :: (volatile store 32 into `<8 x i32> addrspace(1)* undef`, align 8, addrspace 1)
  ; GCN:   G_STORE [[BUILD_VECTOR]](<8 x s32>), [[DEF]](p1) :: (volatile store 32 into `<8 x i32> addrspace(1)* undef`, align 8, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <8 x i32> @external_v8i32_func_void()
  %val = call <8 x i32> @external_v8i32_func_void()

  store volatile <8 x i32> %val, <8 x i32> addrspace(1)* undef, align 8
  store volatile <8 x i32> %val, <8 x i32> addrspace(1)* undef, align 8

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v16i32_func_void() #0 {
define amdgpu_kernel void @test_call_external_v16i32_func_void() #0 {

▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_v16i32_func_void() #0 {

  ; GCN:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; GCN:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; GCN:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr9
  ; GCN:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr9

  ; GCN:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr10
  ; GCN:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr10

  ; GCN:   [[COPY32:%[0-9]+]]:_(s32) = COPY $vgpr11
  ; GCN:   [[COPY32:%[0-9]+]]:_(s32) = COPY $vgpr11

  ; GCN:   [[COPY33:%[0-9]+]]:_(s32) = COPY $vgpr12
  ; GCN:   [[COPY33:%[0-9]+]]:_(s32) = COPY $vgpr12

  ; GCN:   [[COPY34:%[0-9]+]]:_(s32) = COPY $vgpr13
  ; GCN:   [[COPY34:%[0-9]+]]:_(s32) = COPY $vgpr13

  ; GCN:   [[COPY35:%[0-9]+]]:_(s32) = COPY $vgpr14
  ; GCN:   [[COPY35:%[0-9]+]]:_(s32) = COPY $vgpr14

  ; GCN:   [[COPY36:%[0-9]+]]:_(s32) = COPY $vgpr15
  ; GCN:   [[COPY36:%[0-9]+]]:_(s32) = COPY $vgpr15

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32), [[COPY33]](s32), [[COPY34]](s32), [[COPY35]](s32), [[COPY36]](s32)
  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32), [[COPY33]](s32), [[COPY34]](s32), [[COPY35]](s32), [[COPY36]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[BUILD_VECTOR]](<16 x s32>), [[DEF]](p1) :: (volatile store 64 into `<16 x i32> addrspace(1)* undef`, align 8, addrspace 1)
  ; GCN:   G_STORE [[BUILD_VECTOR]](<16 x s32>), [[DEF]](p1) :: (volatile store 64 into `<16 x i32> addrspace(1)* undef`, align 8, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <16 x i32> @external_v16i32_func_void()
  %val = call <16 x i32> @external_v16i32_func_void()

  store volatile <16 x i32> %val, <16 x i32> addrspace(1)* undef, align 8
  store volatile <16 x i32> %val, <16 x i32> addrspace(1)* undef, align 8

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v32i32_func_void() #0 {
define amdgpu_kernel void @test_call_external_v32i32_func_void() #0 {

▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_v32i32_func_void() #0 {

  ; GCN:   [[COPY45:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; GCN:   [[COPY45:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; GCN:   [[COPY46:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; GCN:   [[COPY46:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; GCN:   [[COPY47:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; GCN:   [[COPY47:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; GCN:   [[COPY48:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; GCN:   [[COPY48:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; GCN:   [[COPY49:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; GCN:   [[COPY49:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; GCN:   [[COPY50:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; GCN:   [[COPY50:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; GCN:   [[COPY51:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; GCN:   [[COPY51:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; GCN:   [[COPY52:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; GCN:   [[COPY52:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32), [[COPY33]](s32), [[COPY34]](s32), [[COPY35]](s32), [[COPY36]](s32), [[COPY37]](s32), [[COPY38]](s32), [[COPY39]](s32), [[COPY40]](s32), [[COPY41]](s32), [[COPY42]](s32), [[COPY43]](s32), [[COPY44]](s32), [[COPY45]](s32), [[COPY46]](s32), [[COPY47]](s32), [[COPY48]](s32), [[COPY49]](s32), [[COPY50]](s32), [[COPY51]](s32), [[COPY52]](s32)
  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32), [[COPY33]](s32), [[COPY34]](s32), [[COPY35]](s32), [[COPY36]](s32), [[COPY37]](s32), [[COPY38]](s32), [[COPY39]](s32), [[COPY40]](s32), [[COPY41]](s32), [[COPY42]](s32), [[COPY43]](s32), [[COPY44]](s32), [[COPY45]](s32), [[COPY46]](s32), [[COPY47]](s32), [[COPY48]](s32), [[COPY49]](s32), [[COPY50]](s32), [[COPY51]](s32), [[COPY52]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, align 8, addrspace 1)
  ; GCN:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, align 8, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <32 x i32> @external_v32i32_func_void()
  %val = call <32 x i32> @external_v32i32_func_void()

  store volatile <32 x i32> %val, <32 x i32> addrspace(1)* undef, align 8
  store volatile <32 x i32> %val, <32 x i32> addrspace(1)* undef, align 8

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v2i16_func_void() #0 {
define amdgpu_kernel void @test_call_external_v2i16_func_void() #0 {

▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_v3i16_func_void() #0 {

  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)
  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3i16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3i16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1

  ; GCN:   [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; GCN:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; GCN:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>), [[DEF1]](<2 x s16>)
  ; GCN:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>), [[DEF1]](<2 x s16>)

  ; GCN:   [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
  ; GCN:   [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[UV]](<3 x s16>), [[DEF]](p1) :: (volatile store 6 into `<3 x i16> addrspace(1)* undef`, align 8, addrspace 1)
  ; GCN:   G_STORE [[UV]](<3 x s16>), [[DEF]](p1) :: (volatile store 6 into `<3 x i16> addrspace(1)* undef`, align 8, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <3 x i16> @external_v3i16_func_void()
  %val = call <3 x i16> @external_v3i16_func_void()

  store volatile <3 x i16> %val, <3 x i16> addrspace(1)* undef
  store volatile <3 x i16> %val, <3 x i16> addrspace(1)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v4i16_func_void() #0 {
define amdgpu_kernel void @test_call_external_v4i16_func_void() #0 {

Show All 39 Linesdefine amdgpu_kernel void @test_call_external_v4i16_func_void() #0 {

  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)
  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v4i16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v4i16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1

  ; GCN:   [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>)
  ; GCN:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[CONCAT_VECTORS]](<4 x s16>), [[DEF]](p1) :: (volatile store 8 into `<4 x i16> addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[CONCAT_VECTORS]](<4 x s16>), [[DEF]](p1) :: (volatile store 8 into `<4 x i16> addrspace(1)* undef`, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <4 x i16> @external_v4i16_func_void()
  %val = call <4 x i16> @external_v4i16_func_void()

  store volatile <4 x i16> %val, <4 x i16> addrspace(1)* undef
  store volatile <4 x i16> %val, <4 x i16> addrspace(1)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v2f16_func_void() #0 {
define amdgpu_kernel void @test_call_external_v2f16_func_void() #0 {

▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_v3f16_func_void() #0 {

  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)
  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3f16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3f16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1

  ; GCN:   [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; GCN:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; GCN:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>), [[DEF1]](<2 x s16>)
  ; GCN:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>), [[DEF1]](<2 x s16>)

  ; GCN:   [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
  ; GCN:   [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[UV]](<3 x s16>), [[DEF]](p1) :: (volatile store 6 into `<3 x half> addrspace(1)* undef`, align 8, addrspace 1)
  ; GCN:   G_STORE [[UV]](<3 x s16>), [[DEF]](p1) :: (volatile store 6 into `<3 x half> addrspace(1)* undef`, align 8, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <3 x half> @external_v3f16_func_void()
  %val = call <3 x half> @external_v3f16_func_void()

  store volatile <3 x half> %val, <3 x half> addrspace(1)* undef
  store volatile <3 x half> %val, <3 x half> addrspace(1)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v4f16_func_void() #0 {
define amdgpu_kernel void @test_call_external_v4f16_func_void() #0 {

Show All 39 Linesdefine amdgpu_kernel void @test_call_external_v4f16_func_void() #0 {

  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)
  ; GCN:   $sgpr10_sgpr11 = COPY [[COPY13]](s64)

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v4f16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v4f16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1

  ; GCN:   [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>)
  ; GCN:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[CONCAT_VECTORS]](<4 x s16>), [[DEF]](p1) :: (volatile store 8 into `<4 x half> addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[CONCAT_VECTORS]](<4 x s16>), [[DEF]](p1) :: (volatile store 8 into `<4 x half> addrspace(1)* undef`, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <4 x half> @external_v4f16_func_void()
  %val = call <4 x half> @external_v4f16_func_void()

  store volatile <4 x half> %val, <4 x half> addrspace(1)* undef
  store volatile <4 x half> %val, <4 x half> addrspace(1)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v3f32_func_void() #0 {
define amdgpu_kernel void @test_call_external_v3f32_func_void() #0 {

Show All 40 Linesdefine amdgpu_kernel void @test_call_external_v3f32_func_void() #0 {

  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY14]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3f32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3f32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32)
  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[BUILD_VECTOR]](<3 x s32>), [[DEF]](p1) :: (volatile store 12 into `<3 x float> addrspace(1)* undef`, align 16, addrspace 1)
  ; GCN:   G_STORE [[BUILD_VECTOR]](<3 x s32>), [[DEF]](p1) :: (volatile store 12 into `<3 x float> addrspace(1)* undef`, align 16, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <3 x float> @external_v3f32_func_void()
  %val = call <3 x float> @external_v3f32_func_void()

  store volatile <3 x float> %val, <3 x float> addrspace(1)* undef
  store volatile <3 x float> %val, <3 x float> addrspace(1)* undef

  ret void
  ret void

}
}




define amdgpu_kernel void @test_call_external_v5f32_func_void() #0 {
define amdgpu_kernel void @test_call_external_v5f32_func_void() #0 {

▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_v5f32_func_void() #0 {

  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY16]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v5f32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v5f32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4

  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GCN:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GCN:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32)
  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[BUILD_VECTOR]](<5 x s32>), [[DEF]](p1) :: (volatile store 20 into `<5 x float> addrspace(1)* undef`, align 32, addrspace 1)
  ; GCN:   G_STORE [[BUILD_VECTOR]](<5 x s32>), [[DEF]](p1) :: (volatile store 20 into `<5 x float> addrspace(1)* undef`, align 32, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call <5 x float> @external_v5f32_func_void()
  %val = call <5 x float> @external_v5f32_func_void()

  store volatile <5 x float> %val, <5 x float> addrspace(1)* undef
  store volatile <5 x float> %val, <5 x float> addrspace(1)* undef

  ret void
  ret void

}
}







▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_i32_i64_func_void() #0 {

  ; GCN:   $sgpr12 = COPY [[COPY15]](s32)
  ; GCN:   $sgpr12 = COPY [[COPY15]](s32)

  ; GCN:   $sgpr13 = COPY [[COPY16]](s32)
  ; GCN:   $sgpr13 = COPY [[COPY16]](s32)

  ; GCN:   $sgpr14 = COPY [[COPY17]](s32)
  ; GCN:   $sgpr14 = COPY [[COPY17]](s32)

  ; GCN:   $vgpr31 = COPY [[OR1]](s32)
  ; GCN:   $vgpr31 = COPY [[OR1]](s32)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i32_i64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i32_i64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2

  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GCN:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY23]](s32), [[COPY24]](s32)
  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY23]](s32), [[COPY24]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[COPY22]](s32), [[DEF]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[COPY22]](s32), [[DEF]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   G_STORE [[MV]](s64), [[COPY10]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[MV]](s64), [[COPY10]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  %val = call { i32, i64 } @external_i32_i64_func_void()
  %val = call { i32, i64 } @external_i32_i64_func_void()

  %val.0 = extractvalue { i32, i64 } %val, 0
  %val.0 = extractvalue { i32, i64 } %val, 0

  %val.1 = extractvalue { i32, i64 } %val, 1
  %val.1 = extractvalue { i32, i64 } %val, 1

  store volatile i32 %val.0, i32 addrspace(1)* undef
  store volatile i32 %val.0, i32 addrspace(1)* undef

  store volatile i64 %val.1, i64 addrspace(1)* undef
  store volatile i64 %val.1, i64 addrspace(1)* undef

Show All 10 Linesdefine amdgpu_gfx void @test_gfx_call_external_i32_i64_func_void() #0 {

  ; GCN:   ADJCALLSTACKUP 0, 0, implicit-def $scc
  ; GCN:   ADJCALLSTACKUP 0, 0, implicit-def $scc

  ; GCN:   [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_gfx_i32_i64_func_void
  ; GCN:   [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_gfx_i32_i64_func_void

  ; GCN:   [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
  ; GCN:   [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

  ; GCN:   $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY2]](<4 x s32>)
  ; GCN:   $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY2]](<4 x s32>)

  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_gfx_i32_i64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2
  ; GCN:   $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_gfx_i32_i64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; GCN:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; GCN:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; GCN:   G_STORE [[COPY3]](s32), [[DEF]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[COPY3]](s32), [[DEF]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   G_STORE [[MV]](s64), [[COPY1]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[MV]](s64), [[COPY1]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)

  ; GCN:   [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
  ; GCN:   [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]

  ; GCN:   S_SETPC_B64_return [[COPY6]]
  ; GCN:   S_SETPC_B64_return [[COPY6]]

  %val = call amdgpu_gfx { i32, i64 } @external_gfx_i32_i64_func_void()
  %val = call amdgpu_gfx { i32, i64 } @external_gfx_i32_i64_func_void()

  %val.0 = extractvalue { i32, i64 } %val, 0
  %val.0 = extractvalue { i32, i64 } %val, 0

  %val.1 = extractvalue { i32, i64 } %val, 1
  %val.1 = extractvalue { i32, i64 } %val, 1

  store volatile i32 %val.0, i32 addrspace(1)* undef
  store volatile i32 %val.0, i32 addrspace(1)* undef

▲ Show 20 Lines • Show All 402 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
}
}




define <2 x float> @v_constained_fadd_v2f32_fpexcept_strict(<2 x float> %x, <2 x float> %y) #0 {
define <2 x float> @v_constained_fadd_v2f32_fpexcept_strict(<2 x float> %x, <2 x float> %y) #0 {

  ; CHECK-LABEL: name: v_constained_fadd_v2f32_fpexcept_strict
  ; CHECK-LABEL: name: v_constained_fadd_v2f32_fpexcept_strict

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[STRICT_FADD:%[0-9]+]]:_(<2 x s32>) = G_STRICT_FADD [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
  ; CHECK:   [[STRICT_FADD:%[0-9]+]]:_(<2 x s32>) = G_STRICT_FADD [[BUILD_VECTOR]], [[BUILD_VECTOR1]]

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[STRICT_FADD]](<2 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[STRICT_FADD]](<2 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %val = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float> %x, <2 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
  %val = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float> %x, <2 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")

  ret <2 x float> %val
  ret <2 x float> %val

}
}




define <2 x float> @v_constained_fadd_v2f32_fpexcept_ignore(<2 x float> %x, <2 x float> %y) #0 {
define <2 x float> @v_constained_fadd_v2f32_fpexcept_ignore(<2 x float> %x, <2 x float> %y) #0 {

  ; CHECK-LABEL: name: v_constained_fadd_v2f32_fpexcept_ignore
  ; CHECK-LABEL: name: v_constained_fadd_v2f32_fpexcept_ignore

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   %7:_(<2 x s32>) = nofpexcept G_STRICT_FADD [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
  ; CHECK:   %7:_(<2 x s32>) = nofpexcept G_STRICT_FADD [[BUILD_VECTOR]], [[BUILD_VECTOR1]]

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %7(<2 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %7(<2 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %val = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float> %x, <2 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
  %val = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float> %x, <2 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")

  ret <2 x float> %val
  ret <2 x float> %val

}
}




define <2 x float> @v_constained_fadd_v2f32_fpexcept_maytrap(<2 x float> %x, <2 x float> %y) #0 {
define <2 x float> @v_constained_fadd_v2f32_fpexcept_maytrap(<2 x float> %x, <2 x float> %y) #0 {

  ; CHECK-LABEL: name: v_constained_fadd_v2f32_fpexcept_maytrap
  ; CHECK-LABEL: name: v_constained_fadd_v2f32_fpexcept_maytrap

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[STRICT_FADD:%[0-9]+]]:_(<2 x s32>) = G_STRICT_FADD [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
  ; CHECK:   [[STRICT_FADD:%[0-9]+]]:_(<2 x s32>) = G_STRICT_FADD [[BUILD_VECTOR]], [[BUILD_VECTOR1]]

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[STRICT_FADD]](<2 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[STRICT_FADD]](<2 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %val = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float> %x, <2 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
  %val = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float> %x, <2 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap")

  ret <2 x float> %val
  ret <2 x float> %val

▲ Show 20 Lines • Show All 104 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
Show First 20 Lines • Show All 302 Lines • ▼ Show 20 Lines
}
}




define void @void_func_i48(i48 %arg0) #0 {
define void @void_func_i48(i48 %arg0) #0 {

  ; CHECK-LABEL: name: void_func_i48
  ; CHECK-LABEL: name: void_func_i48

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[TRUNC]](s48), [[DEF]](p1) :: (store 6 into `i48 addrspace(1)* undef`, align 8, addrspace 1)
  ; CHECK:   G_STORE [[TRUNC]](s48), [[DEF]](p1) :: (store 6 into `i48 addrspace(1)* undef`, align 8, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store i48 %arg0, i48 addrspace(1)* undef
  store i48 %arg0, i48 addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_i48_zeroext(i48 zeroext %arg0) #0 {
define void @void_func_i48_zeroext(i48 zeroext %arg0) #0 {

  ; CHECK-LABEL: name: void_func_i48_zeroext
  ; CHECK-LABEL: name: void_func_i48_zeroext

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s48)
  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s48)

  ; CHECK:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ZEXT]], [[C]]
  ; CHECK:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ZEXT]], [[C]]

  ; CHECK:   G_STORE [[ADD]](s64), [[DEF]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[ADD]](s64), [[DEF]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  %ext = zext i48 %arg0 to i64
  %ext = zext i48 %arg0 to i64

  %add = add i64 %ext, 12
  %add = add i64 %ext, 12

  store i64 %add, i64 addrspace(1)* undef
  store i64 %add, i64 addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_i48_signext(i48 signext %arg0) #0 {
define void @void_func_i48_signext(i48 signext %arg0) #0 {

  ; CHECK-LABEL: name: void_func_i48_signext
  ; CHECK-LABEL: name: void_func_i48_signext

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s48)
  ; CHECK:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s48)

  ; CHECK:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SEXT]], [[C]]
  ; CHECK:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SEXT]], [[C]]

  ; CHECK:   G_STORE [[ADD]](s64), [[DEF]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[ADD]](s64), [[DEF]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  %ext = sext i48 %arg0 to i64
  %ext = sext i48 %arg0 to i64

  %add = add i64 %ext, 12
  %add = add i64 %ext, 12

  store i64 %add, i64 addrspace(1)* undef
  store i64 %add, i64 addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_i64(i64 %arg0) #0 {
define void @void_func_i64(i64 %arg0) #0 {

  ; CHECK-LABEL: name: void_func_i64
  ; CHECK-LABEL: name: void_func_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[MV]](s64), [[DEF]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[MV]](s64), [[DEF]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store i64 %arg0, i64 addrspace(1)* undef
  store i64 %arg0, i64 addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_i95(i95 %arg0) #0 {
define void @void_func_i95(i95 %arg0) #0 {

  ; CHECK-LABEL: name: void_func_i95
  ; CHECK-LABEL: name: void_func_i95

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s95) = G_TRUNC [[MV]](s96)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s95) = G_TRUNC [[MV]](s96)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[TRUNC]](s95), [[DEF]](p1) :: (store 12 into `i95 addrspace(1)* undef`, align 8, addrspace 1)
  ; CHECK:   G_STORE [[TRUNC]](s95), [[DEF]](p1) :: (store 12 into `i95 addrspace(1)* undef`, align 8, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  store i95 %arg0, i95 addrspace(1)* undef
  store i95 %arg0, i95 addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_i95_zeroext(i95 zeroext %arg0) #0 {
define void @void_func_i95_zeroext(i95 zeroext %arg0) #0 {

  ; CHECK-LABEL: name: void_func_i95_zeroext
  ; CHECK-LABEL: name: void_func_i95_zeroext

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s95) = G_TRUNC [[MV]](s96)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s95) = G_TRUNC [[MV]](s96)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[C:%[0-9]+]]:_(s96) = G_CONSTANT i96 12
  ; CHECK:   [[C:%[0-9]+]]:_(s96) = G_CONSTANT i96 12

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s96) = G_ZEXT [[TRUNC]](s95)
  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s96) = G_ZEXT [[TRUNC]](s95)

  ; CHECK:   [[ADD:%[0-9]+]]:_(s96) = G_ADD [[ZEXT]], [[C]]
  ; CHECK:   [[ADD:%[0-9]+]]:_(s96) = G_ADD [[ZEXT]], [[C]]

  ; CHECK:   G_STORE [[ADD]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)
  ; CHECK:   G_STORE [[ADD]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  %ext = zext i95 %arg0 to i96
  %ext = zext i95 %arg0 to i96

  %add = add i96 %ext, 12
  %add = add i96 %ext, 12

  store i96 %add, i96 addrspace(1)* undef
  store i96 %add, i96 addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_i95_signext(i95 signext %arg0) #0 {
define void @void_func_i95_signext(i95 signext %arg0) #0 {

  ; CHECK-LABEL: name: void_func_i95_signext
  ; CHECK-LABEL: name: void_func_i95_signext

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s95) = G_TRUNC [[MV]](s96)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s95) = G_TRUNC [[MV]](s96)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[C:%[0-9]+]]:_(s96) = G_CONSTANT i96 12
  ; CHECK:   [[C:%[0-9]+]]:_(s96) = G_CONSTANT i96 12

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[SEXT:%[0-9]+]]:_(s96) = G_SEXT [[TRUNC]](s95)
  ; CHECK:   [[SEXT:%[0-9]+]]:_(s96) = G_SEXT [[TRUNC]](s95)

  ; CHECK:   [[ADD:%[0-9]+]]:_(s96) = G_ADD [[SEXT]], [[C]]
  ; CHECK:   [[ADD:%[0-9]+]]:_(s96) = G_ADD [[SEXT]], [[C]]

  ; CHECK:   G_STORE [[ADD]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)
  ; CHECK:   G_STORE [[ADD]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  %ext = sext i95 %arg0 to i96
  %ext = sext i95 %arg0 to i96

  %add = add i96 %ext, 12
  %add = add i96 %ext, 12

  store i96 %add, i96 addrspace(1)* undef
  store i96 %add, i96 addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_i96(i96 %arg0) #0 {
define void @void_func_i96(i96 %arg0) #0 {

  ; CHECK-LABEL: name: void_func_i96
  ; CHECK-LABEL: name: void_func_i96

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[MV]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)
  ; CHECK:   G_STORE [[MV]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  store i96 %arg0, i96 addrspace(1)* undef
  store i96 %arg0, i96 addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_p0i8(i8* %arg0) #0 {
define void @void_func_p0i8(i8* %arg0) #0 {

  ; CHECK-LABEL: name: void_func_p0i8
  ; CHECK-LABEL: name: void_func_p0i8

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[MV]](p0), [[DEF]](p1) :: (store 8 into `i8* addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[MV]](p0), [[DEF]](p1) :: (store 8 into `i8* addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store i8* %arg0, i8* addrspace(1)* undef
  store i8* %arg0, i8* addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_p1i8(i8 addrspace(1)* %arg0) #0 {
define void @void_func_p1i8(i8 addrspace(1)* %arg0) #0 {

  ; CHECK-LABEL: name: void_func_p1i8
  ; CHECK-LABEL: name: void_func_p1i8

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[MV]](p1), [[DEF]](p1) :: (store 8 into `i8 addrspace(1)* addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[MV]](p1), [[DEF]](p1) :: (store 8 into `i8 addrspace(1)* addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store i8 addrspace(1)* %arg0, i8 addrspace(1)* addrspace(1)* undef
  store i8 addrspace(1)* %arg0, i8 addrspace(1)* addrspace(1)* undef

  ret void
  ret void

}
}




Show All 27 Lines
}
}




define void @void_func_f64(double %arg0) #0 {
define void @void_func_f64(double %arg0) #0 {

  ; CHECK-LABEL: name: void_func_f64
  ; CHECK-LABEL: name: void_func_f64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[MV]](s64), [[DEF]](p1) :: (store 8 into `double addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[MV]](s64), [[DEF]](p1) :: (store 8 into `double addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store double %arg0, double addrspace(1)* undef
  store double %arg0, double addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v2i32(<2 x i32> %arg0) #0 {
define void @void_func_v2i32(<2 x i32> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v2i32
  ; CHECK-LABEL: name: void_func_v2i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x s32>), [[DEF]](p1) :: (store 8 into `<2 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x s32>), [[DEF]](p1) :: (store 8 into `<2 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store <2 x i32> %arg0, <2 x i32> addrspace(1)* undef
  store <2 x i32> %arg0, <2 x i32> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v2i24(<2 x i24> %arg0) #0 {
define void @void_func_v2i24(<2 x i24> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v2i24
  ; CHECK-LABEL: name: void_func_v2i24

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(<2 x s24>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(<2 x s24>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[TRUNC]](<2 x s24>), [[DEF]](p1) :: (store 6 into `<2 x i24> addrspace(1)* undef`, align 8, addrspace 1)
  ; CHECK:   G_STORE [[TRUNC]](<2 x s24>), [[DEF]](p1) :: (store 6 into `<2 x i24> addrspace(1)* undef`, align 8, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store <2 x i24> %arg0, <2 x i24> addrspace(1)* undef
  store <2 x i24> %arg0, <2 x i24> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v3i24(<3 x i24> %arg0) #0 {
define void @void_func_v3i24(<3 x i24> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v3i24
  ; CHECK-LABEL: name: void_func_v3i24

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(<3 x s24>) = G_TRUNC [[BUILD_VECTOR]](<3 x s32>)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(<3 x s24>) = G_TRUNC [[BUILD_VECTOR]](<3 x s32>)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[TRUNC]](<3 x s24>), [[DEF]](p1) :: (store 9 into `<3 x i24> addrspace(1)* undef`, align 16, addrspace 1)
  ; CHECK:   G_STORE [[TRUNC]](<3 x s24>), [[DEF]](p1) :: (store 9 into `<3 x i24> addrspace(1)* undef`, align 16, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  store <3 x i24> %arg0, <3 x i24> addrspace(1)* undef
  store <3 x i24> %arg0, <3 x i24> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v2i8(<2 x i8> %arg0) #0 {
define void @void_func_v2i8(<2 x i8> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v2i8
  ; CHECK-LABEL: name: void_func_v2i8

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)

  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(<2 x s8>) = G_TRUNC [[BUILD_VECTOR]](<2 x s16>)
  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(<2 x s8>) = G_TRUNC [[BUILD_VECTOR]](<2 x s16>)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[TRUNC2]](<2 x s8>), [[DEF]](p1) :: (store 2 into `<2 x i8> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[TRUNC2]](<2 x s8>), [[DEF]](p1) :: (store 2 into `<2 x i8> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store <2 x i8> %arg0, <2 x i8> addrspace(1)* undef
  store <2 x i8> %arg0, <2 x i8> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v3i8(<3 x i8> %arg0) #0 {
define void @void_func_v3i8(<3 x i8> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v3i8
  ; CHECK-LABEL: name: void_func_v3i8

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16)

  ; CHECK:   [[TRUNC3:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[BUILD_VECTOR]](<3 x s16>)
  ; CHECK:   [[TRUNC3:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[BUILD_VECTOR]](<3 x s16>)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[TRUNC3]](<3 x s8>), [[DEF]](p1) :: (store 3 into `<3 x i8> addrspace(1)* undef`, align 4, addrspace 1)
  ; CHECK:   G_STORE [[TRUNC3]](<3 x s8>), [[DEF]](p1) :: (store 3 into `<3 x i8> addrspace(1)* undef`, align 4, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  store <3 x i8> %arg0, <3 x i8> addrspace(1)* undef
  store <3 x i8> %arg0, <3 x i8> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v4i8(<4 x i8> %arg0) #0 {
define void @void_func_v4i8(<4 x i8> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v4i8
  ; CHECK-LABEL: name: void_func_v4i8

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
  ; CHECK:   [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16)

  ; CHECK:   [[TRUNC4:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s16>)
  ; CHECK:   [[TRUNC4:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s16>)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[TRUNC4]](<4 x s8>), [[DEF]](p1) :: (store 4 into `<4 x i8> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[TRUNC4]](<4 x s8>), [[DEF]](p1) :: (store 4 into `<4 x i8> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]]
  ; CHECK:   S_SETPC_B64_return [[COPY5]]

  store <4 x i8> %arg0, <4 x i8> addrspace(1)* undef
  store <4 x i8> %arg0, <4 x i8> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v2p3i8(<2 x i8 addrspace(3)*> %arg0) #0 {
define void @void_func_v2p3i8(<2 x i8 addrspace(3)*> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v2p3i8
  ; CHECK-LABEL: name: void_func_v2p3i8

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY]](p3), [[COPY1]](p3)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY]](p3), [[COPY1]](p3)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x p3>), [[DEF]](p1) :: (store 8 into `<2 x i8 addrspace(3)*> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x p3>), [[DEF]](p1) :: (store 8 into `<2 x i8 addrspace(3)*> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store <2 x i8 addrspace(3)*> %arg0, <2 x i8 addrspace(3)*> addrspace(1)* undef
  store <2 x i8 addrspace(3)*> %arg0, <2 x i8 addrspace(3)*> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v3i32(<3 x i32> %arg0) #0 {
define void @void_func_v3i32(<3 x i32> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v3i32
  ; CHECK-LABEL: name: void_func_v3i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<3 x s32>), [[DEF]](p1) :: (store 12 into `<3 x i32> addrspace(1)* undef`, align 16, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<3 x s32>), [[DEF]](p1) :: (store 12 into `<3 x i32> addrspace(1)* undef`, align 16, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  store <3 x i32> %arg0, <3 x i32> addrspace(1)* undef
  store <3 x i32> %arg0, <3 x i32> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v4i32(<4 x i32> %arg0) #0 {
define void @void_func_v4i32(<4 x i32> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v4i32
  ; CHECK-LABEL: name: void_func_v4i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]]
  ; CHECK:   S_SETPC_B64_return [[COPY5]]

  store <4 x i32> %arg0, <4 x i32> addrspace(1)* undef
  store <4 x i32> %arg0, <4 x i32> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v5i32(<5 x i32> %arg0) #0 {
define void @void_func_v5i32(<5 x i32> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v5i32
  ; CHECK-LABEL: name: void_func_v5i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<5 x s32>), [[DEF]](p1) :: (store 20 into `<5 x i32> addrspace(1)* undef`, align 32, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<5 x s32>), [[DEF]](p1) :: (store 20 into `<5 x i32> addrspace(1)* undef`, align 32, addrspace 1)

  ; CHECK:   [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY5]]
  ; CHECK:   [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY5]]

  ; CHECK:   S_SETPC_B64_return [[COPY6]]
  ; CHECK:   S_SETPC_B64_return [[COPY6]]

  store <5 x i32> %arg0, <5 x i32> addrspace(1)* undef
  store <5 x i32> %arg0, <5 x i32> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v8i32(<8 x i32> %arg0) #0 {
define void @void_func_v8i32(<8 x i32> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v8i32
  ; CHECK-LABEL: name: void_func_v8i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<8 x s32>), [[DEF]](p1) :: (store 32 into `<8 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<8 x s32>), [[DEF]](p1) :: (store 32 into `<8 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]
  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]

  ; CHECK:   S_SETPC_B64_return [[COPY9]]
  ; CHECK:   S_SETPC_B64_return [[COPY9]]

  store <8 x i32> %arg0, <8 x i32> addrspace(1)* undef
  store <8 x i32> %arg0, <8 x i32> addrspace(1)* undef

  ret void
  ret void

}
}




Show All 12 Linesdefine void @void_func_v16i32(<16 x i32> %arg0) #0 {

  ; CHECK:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; CHECK:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; CHECK:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9
  ; CHECK:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9

  ; CHECK:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr10
  ; CHECK:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr10

  ; CHECK:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11
  ; CHECK:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11

  ; CHECK:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12
  ; CHECK:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12

  ; CHECK:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
  ; CHECK:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13

  ; CHECK:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
  ; CHECK:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14

  ; CHECK:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
  ; CHECK:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15

  ; CHECK:   [[COPY16:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)

  ; CHECK:   [[COPY16:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<16 x s32>), [[DEF]](p1) :: (store 64 into `<16 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<16 x s32>), [[DEF]](p1) :: (store 64 into `<16 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY17:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY16]]
  ; CHECK:   [[COPY17:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY16]]

  ; CHECK:   S_SETPC_B64_return [[COPY17]]
  ; CHECK:   S_SETPC_B64_return [[COPY17]]

  store <16 x i32> %arg0, <16 x i32> addrspace(1)* undef
  store <16 x i32> %arg0, <16 x i32> addrspace(1)* undef

  ret void
  ret void

}
}




Show All 28 Linesdefine void @void_func_v32i32(<32 x i32> %arg0) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY33]]
  ; CHECK:   S_SETPC_B64_return [[COPY33]]

  store <32 x i32> %arg0, <32 x i32> addrspace(1)* undef
  store <32 x i32> %arg0, <32 x i32> addrspace(1)* undef

  ret void
  ret void

}
}




Show All 31 Linesdefine void @void_func_v33i32(<33 x i32> %arg0) #0 {

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0

  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.0, align 16, addrspace 5)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.0, align 16, addrspace 5)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<33 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[LOAD]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<33 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[LOAD]](s32)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<33 x s32>), [[DEF]](p1) :: (store 132 into `<33 x i32> addrspace(1)* undef`, align 256, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<33 x s32>), [[DEF]](p1) :: (store 132 into `<33 x i32> addrspace(1)* undef`, align 256, addrspace 1)

  ; CHECK:   [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY33]]
  ; CHECK:   S_SETPC_B64_return [[COPY33]]

  store <33 x i32> %arg0, <33 x i32> addrspace(1)* undef
  store <33 x i32> %arg0, <33 x i32> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v2i64(<2 x i64> %arg0) #0 {
define void @void_func_v2i64(<2 x i64> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v2i64
  ; CHECK-LABEL: name: void_func_v2i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x s64>), [[DEF]](p1) :: (store 16 into `<2 x i64> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x s64>), [[DEF]](p1) :: (store 16 into `<2 x i64> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]]
  ; CHECK:   S_SETPC_B64_return [[COPY5]]

  store <2 x i64> %arg0, <2 x i64> addrspace(1)* undef
  store <2 x i64> %arg0, <2 x i64> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v2p0i8(<2 x i8*> %arg0) #0 {
define void @void_func_v2p0i8(<2 x i8*> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v2p0i8
  ; CHECK-LABEL: name: void_func_v2p0i8

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[MV]](p0), [[MV1]](p0)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[MV]](p0), [[MV1]](p0)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x p0>), [[DEF]](p1) :: (store 16 into `<2 x i8*> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x p0>), [[DEF]](p1) :: (store 16 into `<2 x i8*> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]]
  ; CHECK:   S_SETPC_B64_return [[COPY5]]

  store <2 x i8*> %arg0, <2 x i8*> addrspace(1)* undef
  store <2 x i8*> %arg0, <2 x i8*> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v2p1i8(<2 x i8 addrspace(1)*> %arg0) #0 {
define void @void_func_v2p1i8(<2 x i8 addrspace(1)*> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v2p1i8
  ; CHECK-LABEL: name: void_func_v2p1i8

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x p1>), [[DEF]](p1) :: (store 16 into `<2 x i8 addrspace(1)*> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x p1>), [[DEF]](p1) :: (store 16 into `<2 x i8 addrspace(1)*> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]]
  ; CHECK:   S_SETPC_B64_return [[COPY5]]

  store <2 x i8 addrspace(1)*> %arg0, <2 x i8 addrspace(1)*> addrspace(1)* undef
  store <2 x i8 addrspace(1)*> %arg0, <2 x i8 addrspace(1)*> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v3i64(<3 x i64> %arg0) #0 {
define void @void_func_v3i64(<3 x i64> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v3i64
  ; CHECK-LABEL: name: void_func_v3i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64)

  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<3 x s64>), [[DEF]](p1) :: (store 24 into `<3 x i64> addrspace(1)* undef`, align 32, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<3 x s64>), [[DEF]](p1) :: (store 24 into `<3 x i64> addrspace(1)* undef`, align 32, addrspace 1)

  ; CHECK:   [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY6]]
  ; CHECK:   [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY6]]

  ; CHECK:   S_SETPC_B64_return [[COPY7]]
  ; CHECK:   S_SETPC_B64_return [[COPY7]]

  store <3 x i64> %arg0, <3 x i64> addrspace(1)* undef
  store <3 x i64> %arg0, <3 x i64> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v4i64(<4 x i64> %arg0) #0 {
define void @void_func_v4i64(<4 x i64> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v4i64
  ; CHECK-LABEL: name: void_func_v4i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<4 x s64>), [[DEF]](p1) :: (store 32 into `<4 x i64> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<4 x s64>), [[DEF]](p1) :: (store 32 into `<4 x i64> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]
  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]

  ; CHECK:   S_SETPC_B64_return [[COPY9]]
  ; CHECK:   S_SETPC_B64_return [[COPY9]]

  store <4 x i64> %arg0, <4 x i64> addrspace(1)* undef
  store <4 x i64> %arg0, <4 x i64> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v5i64(<5 x i64> %arg0) #0 {
define void @void_func_v5i64(<5 x i64> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v5i64
  ; CHECK-LABEL: name: void_func_v5i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; CHECK:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; CHECK:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; CHECK:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9
  ; CHECK:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9

  ; CHECK:   [[COPY10:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)

  ; CHECK:   [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)
  ; CHECK:   [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64)

  ; CHECK:   [[COPY10:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<5 x s64>), [[DEF]](p1) :: (store 40 into `<5 x i64> addrspace(1)* undef`, align 64, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<5 x s64>), [[DEF]](p1) :: (store 40 into `<5 x i64> addrspace(1)* undef`, align 64, addrspace 1)

  ; CHECK:   [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY10]]
  ; CHECK:   [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY10]]

  ; CHECK:   S_SETPC_B64_return [[COPY11]]
  ; CHECK:   S_SETPC_B64_return [[COPY11]]

  store <5 x i64> %arg0, <5 x i64> addrspace(1)* undef
  store <5 x i64> %arg0, <5 x i64> addrspace(1)* undef

  ret void
  ret void

}
}




Show All 12 Linesdefine void @void_func_v8i64(<8 x i64> %arg0) #0 {

  ; CHECK:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; CHECK:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; CHECK:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9
  ; CHECK:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9

  ; CHECK:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr10
  ; CHECK:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr10

  ; CHECK:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11
  ; CHECK:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11

  ; CHECK:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12
  ; CHECK:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12

  ; CHECK:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
  ; CHECK:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13

  ; CHECK:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
  ; CHECK:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14

  ; CHECK:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
  ; CHECK:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15

  ; CHECK:   [[COPY16:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)

  ; CHECK:   [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)
  ; CHECK:   [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)

  ; CHECK:   [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY10]](s32), [[COPY11]](s32)
  ; CHECK:   [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY10]](s32), [[COPY11]](s32)

  ; CHECK:   [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY12]](s32), [[COPY13]](s32)
  ; CHECK:   [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY12]](s32), [[COPY13]](s32)

  ; CHECK:   [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY14]](s32), [[COPY15]](s32)
  ; CHECK:   [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY14]](s32), [[COPY15]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64)

  ; CHECK:   [[COPY16:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<8 x s64>), [[DEF]](p1) :: (store 64 into `<8 x i64> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<8 x s64>), [[DEF]](p1) :: (store 64 into `<8 x i64> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY17:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY16]]
  ; CHECK:   [[COPY17:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY16]]

  ; CHECK:   S_SETPC_B64_return [[COPY17]]
  ; CHECK:   S_SETPC_B64_return [[COPY17]]

  store <8 x i64> %arg0, <8 x i64> addrspace(1)* undef
  store <8 x i64> %arg0, <8 x i64> addrspace(1)* undef

  ret void
  ret void

}
}




Show All 28 Linesdefine void @void_func_v16i64(<16 x i64> %arg0) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)

  ; CHECK:   [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)
  ; CHECK:   [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)

  ; CHECK:   [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY10]](s32), [[COPY11]](s32)
  ; CHECK:   [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY10]](s32), [[COPY11]](s32)

  ; CHECK:   [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY12]](s32), [[COPY13]](s32)
  ; CHECK:   [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY12]](s32), [[COPY13]](s32)

  ; CHECK:   [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY14]](s32), [[COPY15]](s32)
  ; CHECK:   [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY14]](s32), [[COPY15]](s32)

  ; CHECK:   [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY16]](s32), [[COPY17]](s32)
  ; CHECK:   [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY16]](s32), [[COPY17]](s32)

  ; CHECK:   [[MV9:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY18]](s32), [[COPY19]](s32)
  ; CHECK:   [[MV9:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY18]](s32), [[COPY19]](s32)

  ; CHECK:   [[MV10:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY20]](s32), [[COPY21]](s32)
  ; CHECK:   [[MV10:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY20]](s32), [[COPY21]](s32)

  ; CHECK:   [[MV11:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY22]](s32), [[COPY23]](s32)
  ; CHECK:   [[MV11:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY22]](s32), [[COPY23]](s32)

  ; CHECK:   [[MV12:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY24]](s32), [[COPY25]](s32)
  ; CHECK:   [[MV12:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY24]](s32), [[COPY25]](s32)

  ; CHECK:   [[MV13:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY26]](s32), [[COPY27]](s32)
  ; CHECK:   [[MV13:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY26]](s32), [[COPY27]](s32)

  ; CHECK:   [[MV14:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY28]](s32), [[COPY29]](s32)
  ; CHECK:   [[MV14:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY28]](s32), [[COPY29]](s32)

  ; CHECK:   [[MV15:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY30]](s32), [[COPY31]](s32)
  ; CHECK:   [[MV15:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64), [[MV8]](s64), [[MV9]](s64), [[MV10]](s64), [[MV11]](s64), [[MV12]](s64), [[MV13]](s64), [[MV14]](s64), [[MV15]](s64)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64), [[MV8]](s64), [[MV9]](s64), [[MV10]](s64), [[MV11]](s64), [[MV12]](s64), [[MV13]](s64), [[MV14]](s64), [[MV15]](s64)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<16 x s64>), [[DEF]](p1) :: (store 128 into `<16 x i64> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<16 x s64>), [[DEF]](p1) :: (store 128 into `<16 x i64> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY33]]
  ; CHECK:   S_SETPC_B64_return [[COPY33]]

  store <16 x i64> %arg0, <16 x i64> addrspace(1)* undef
  store <16 x i64> %arg0, <16 x i64> addrspace(1)* undef

  ret void
  ret void

}
}




Show All 12 Lines
}
}




define void @void_func_v3i16(<3 x i16> %arg0) #0 {
define void @void_func_v3i16(<3 x i16> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v3i16
  ; CHECK-LABEL: name: void_func_v3i16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[DEF]](<2 x s16>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[DEF]](<2 x s16>)

  ; CHECK:   [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
  ; CHECK:   [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[UV]](<3 x s16>), [[DEF1]](p1) :: (store 6 into `<3 x i16> addrspace(1)* undef`, align 8, addrspace 1)
  ; CHECK:   G_STORE [[UV]](<3 x s16>), [[DEF1]](p1) :: (store 6 into `<3 x i16> addrspace(1)* undef`, align 8, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store <3 x i16> %arg0, <3 x i16> addrspace(1)* undef
  store <3 x i16> %arg0, <3 x i16> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v4i16(<4 x i16> %arg0) #0 {
define void @void_func_v4i16(<4 x i16> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v4i16
  ; CHECK-LABEL: name: void_func_v4i16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[CONCAT_VECTORS]](<4 x s16>), [[DEF]](p1) :: (store 8 into `<4 x i16> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[CONCAT_VECTORS]](<4 x s16>), [[DEF]](p1) :: (store 8 into `<4 x i16> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store <4 x i16> %arg0, <4 x i16> addrspace(1)* undef
  store <4 x i16> %arg0, <4 x i16> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v5i16(<5 x i16> %arg0) #0 {
define void @void_func_v5i16(<5 x i16> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v5i16
  ; CHECK-LABEL: name: void_func_v5i16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)

  ; CHECK:   [[UV:%[0-9]+]]:_(<5 x s16>), [[UV1:%[0-9]+]]:_(<5 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<10 x s16>)
  ; CHECK:   [[UV:%[0-9]+]]:_(<5 x s16>), [[UV1:%[0-9]+]]:_(<5 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<10 x s16>)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[UV]](<5 x s16>), [[DEF1]](p1) :: (store 10 into `<5 x i16> addrspace(1)* undef`, align 16, addrspace 1)
  ; CHECK:   G_STORE [[UV]](<5 x s16>), [[DEF1]](p1) :: (store 10 into `<5 x i16> addrspace(1)* undef`, align 16, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  store <5 x i16> %arg0, <5 x i16> addrspace(1)* undef
  store <5 x i16> %arg0, <5 x i16> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v8i16(<8 x i16> %arg0) #0 {
define void @void_func_v8i16(<8 x i16> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v8i16
  ; CHECK-LABEL: name: void_func_v8i16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[CONCAT_VECTORS]](<8 x s16>), [[DEF]](p1) :: (store 16 into `<8 x i16> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[CONCAT_VECTORS]](<8 x s16>), [[DEF]](p1) :: (store 16 into `<8 x i16> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]]
  ; CHECK:   S_SETPC_B64_return [[COPY5]]

  store <8 x i16> %arg0, <8 x i16> addrspace(1)* undef
  store <8 x i16> %arg0, <8 x i16> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v16i16(<16 x i16> %arg0) #0 {
define void @void_func_v16i16(<16 x i16> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v16i16
  ; CHECK-LABEL: name: void_func_v16i16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr7
  ; CHECK:   [[COPY7:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr7

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>), [[COPY4]](<2 x s16>), [[COPY5]](<2 x s16>), [[COPY6]](<2 x s16>), [[COPY7]](<2 x s16>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>), [[COPY4]](<2 x s16>), [[COPY5]](<2 x s16>), [[COPY6]](<2 x s16>), [[COPY7]](<2 x s16>)

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[CONCAT_VECTORS]](<16 x s16>), [[DEF]](p1) :: (store 32 into `<16 x i16> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[CONCAT_VECTORS]](<16 x s16>), [[DEF]](p1) :: (store 32 into `<16 x i16> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]
  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]

  ; CHECK:   S_SETPC_B64_return [[COPY9]]
  ; CHECK:   S_SETPC_B64_return [[COPY9]]

  store <16 x i16> %arg0, <16 x i16> addrspace(1)* undef
  store <16 x i16> %arg0, <16 x i16> addrspace(1)* undef

  ret void
  ret void

}
}




Show All 32 Linesdefine void @void_func_v65i16(<65 x i16> %arg0) #0 {

  ; CHECK:   [[COPY26:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr31

  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0

  ; CHECK:   [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.0, align 16, addrspace 5)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.0, align 16, addrspace 5)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<130 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>), [[COPY4]](<2 x s16>), [[COPY5]](<2 x s16>), [[COPY6]](<2 x s16>), [[COPY7]](<2 x s16>), [[COPY8]](<2 x s16>), [[COPY9]](<2 x s16>), [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[COPY12]](<2 x s16>), [[COPY13]](<2 x s16>), [[COPY14]](<2 x s16>), [[COPY15]](<2 x s16>), [[COPY16]](<2 x s16>), [[COPY17]](<2 x s16>), [[COPY18]](<2 x s16>), [[COPY19]](<2 x s16>), [[COPY20]](<2 x s16>), [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>), [[COPY23]](<2 x s16>), [[COPY24]](<2 x s16>), [[COPY25]](<2 x s16>), [[COPY26]](<2 x s16>), [[COPY27]](<2 x s16>), [[COPY28]](<2 x s16>), [[COPY29]](<2 x s16>), [[COPY30]](<2 x s16>), [[COPY31]](<2 x s16>), [[LOAD]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<130 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>), [[COPY4]](<2 x s16>), [[COPY5]](<2 x s16>), [[COPY6]](<2 x s16>), [[COPY7]](<2 x s16>), [[COPY8]](<2 x s16>), [[COPY9]](<2 x s16>), [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[COPY12]](<2 x s16>), [[COPY13]](<2 x s16>), [[COPY14]](<2 x s16>), [[COPY15]](<2 x s16>), [[COPY16]](<2 x s16>), [[COPY17]](<2 x s16>), [[COPY18]](<2 x s16>), [[COPY19]](<2 x s16>), [[COPY20]](<2 x s16>), [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>), [[COPY23]](<2 x s16>), [[COPY24]](<2 x s16>), [[COPY25]](<2 x s16>), [[COPY26]](<2 x s16>), [[COPY27]](<2 x s16>), [[COPY28]](<2 x s16>), [[COPY29]](<2 x s16>), [[COPY30]](<2 x s16>), [[COPY31]](<2 x s16>), [[LOAD]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)

  ; CHECK:   [[UV:%[0-9]+]]:_(<65 x s16>), [[UV1:%[0-9]+]]:_(<65 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<130 x s16>)
  ; CHECK:   [[UV:%[0-9]+]]:_(<65 x s16>), [[UV1:%[0-9]+]]:_(<65 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<130 x s16>)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[UV]](<65 x s16>), [[DEF1]](p1) :: (store 130 into `<65 x i16> addrspace(1)* undef`, align 256, addrspace 1)
  ; CHECK:   G_STORE [[UV]](<65 x s16>), [[DEF1]](p1) :: (store 130 into `<65 x i16> addrspace(1)* undef`, align 256, addrspace 1)

  ; CHECK:   [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY33]]
  ; CHECK:   S_SETPC_B64_return [[COPY33]]

  store <65 x i16> %arg0, <65 x i16> addrspace(1)* undef
  store <65 x i16> %arg0, <65 x i16> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v2f32(<2 x float> %arg0) #0 {
define void @void_func_v2f32(<2 x float> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v2f32
  ; CHECK-LABEL: name: void_func_v2f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x s32>), [[DEF]](p1) :: (store 8 into `<2 x float> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x s32>), [[DEF]](p1) :: (store 8 into `<2 x float> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store <2 x float> %arg0, <2 x float> addrspace(1)* undef
  store <2 x float> %arg0, <2 x float> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v3f32(<3 x float> %arg0) #0 {
define void @void_func_v3f32(<3 x float> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v3f32
  ; CHECK-LABEL: name: void_func_v3f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<3 x s32>), [[DEF]](p1) :: (store 12 into `<3 x float> addrspace(1)* undef`, align 16, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<3 x s32>), [[DEF]](p1) :: (store 12 into `<3 x float> addrspace(1)* undef`, align 16, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  store <3 x float> %arg0, <3 x float> addrspace(1)* undef
  store <3 x float> %arg0, <3 x float> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v4f32(<4 x float> %arg0) #0 {
define void @void_func_v4f32(<4 x float> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v4f32
  ; CHECK-LABEL: name: void_func_v4f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]]
  ; CHECK:   S_SETPC_B64_return [[COPY5]]

  store <4 x float> %arg0, <4 x float> addrspace(1)* undef
  store <4 x float> %arg0, <4 x float> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v8f32(<8 x float> %arg0) #0 {
define void @void_func_v8f32(<8 x float> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v8f32
  ; CHECK-LABEL: name: void_func_v8f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<8 x s32>), [[DEF]](p1) :: (store 32 into `<8 x float> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<8 x s32>), [[DEF]](p1) :: (store 32 into `<8 x float> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]
  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]

  ; CHECK:   S_SETPC_B64_return [[COPY9]]
  ; CHECK:   S_SETPC_B64_return [[COPY9]]

  store <8 x float> %arg0, <8 x float> addrspace(1)* undef
  store <8 x float> %arg0, <8 x float> addrspace(1)* undef

  ret void
  ret void

}
}




Show All 12 Linesdefine void @void_func_v16f32(<16 x float> %arg0) #0 {

  ; CHECK:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; CHECK:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; CHECK:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9
  ; CHECK:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9

  ; CHECK:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr10
  ; CHECK:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr10

  ; CHECK:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11
  ; CHECK:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11

  ; CHECK:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12
  ; CHECK:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12

  ; CHECK:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
  ; CHECK:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13

  ; CHECK:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
  ; CHECK:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14

  ; CHECK:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
  ; CHECK:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15

  ; CHECK:   [[COPY16:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)

  ; CHECK:   [[COPY16:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<16 x s32>), [[DEF]](p1) :: (store 64 into `<16 x float> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<16 x s32>), [[DEF]](p1) :: (store 64 into `<16 x float> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY17:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY16]]
  ; CHECK:   [[COPY17:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY16]]

  ; CHECK:   S_SETPC_B64_return [[COPY17]]
  ; CHECK:   S_SETPC_B64_return [[COPY17]]

  store <16 x float> %arg0, <16 x float> addrspace(1)* undef
  store <16 x float> %arg0, <16 x float> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v2f64(<2 x double> %arg0) #0 {
define void @void_func_v2f64(<2 x double> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v2f64
  ; CHECK-LABEL: name: void_func_v2f64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x s64>), [[DEF]](p1) :: (store 16 into `<2 x double> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<2 x s64>), [[DEF]](p1) :: (store 16 into `<2 x double> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]]
  ; CHECK:   S_SETPC_B64_return [[COPY5]]

  store <2 x double> %arg0, <2 x double> addrspace(1)* undef
  store <2 x double> %arg0, <2 x double> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v3f64(<3 x double> %arg0) #0 {
define void @void_func_v3f64(<3 x double> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v3f64
  ; CHECK-LABEL: name: void_func_v3f64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64)

  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<3 x s64>), [[DEF]](p1) :: (store 24 into `<3 x double> addrspace(1)* undef`, align 32, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<3 x s64>), [[DEF]](p1) :: (store 24 into `<3 x double> addrspace(1)* undef`, align 32, addrspace 1)

  ; CHECK:   [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY6]]
  ; CHECK:   [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY6]]

  ; CHECK:   S_SETPC_B64_return [[COPY7]]
  ; CHECK:   S_SETPC_B64_return [[COPY7]]

  store <3 x double> %arg0, <3 x double> addrspace(1)* undef
  store <3 x double> %arg0, <3 x double> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v4f64(<4 x double> %arg0) #0 {
define void @void_func_v4f64(<4 x double> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v4f64
  ; CHECK-LABEL: name: void_func_v4f64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<4 x s64>), [[DEF]](p1) :: (store 32 into `<4 x double> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<4 x s64>), [[DEF]](p1) :: (store 32 into `<4 x double> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]
  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]

  ; CHECK:   S_SETPC_B64_return [[COPY9]]
  ; CHECK:   S_SETPC_B64_return [[COPY9]]

  store <4 x double> %arg0, <4 x double> addrspace(1)* undef
  store <4 x double> %arg0, <4 x double> addrspace(1)* undef

  ret void
  ret void

}
}




Show All 12 Linesdefine void @void_func_v8f64(<8 x double> %arg0) #0 {

  ; CHECK:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; CHECK:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; CHECK:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9
  ; CHECK:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9

  ; CHECK:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr10
  ; CHECK:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr10

  ; CHECK:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11
  ; CHECK:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11

  ; CHECK:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12
  ; CHECK:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12

  ; CHECK:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
  ; CHECK:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13

  ; CHECK:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
  ; CHECK:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14

  ; CHECK:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
  ; CHECK:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15

  ; CHECK:   [[COPY16:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)

  ; CHECK:   [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)
  ; CHECK:   [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)

  ; CHECK:   [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY10]](s32), [[COPY11]](s32)
  ; CHECK:   [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY10]](s32), [[COPY11]](s32)

  ; CHECK:   [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY12]](s32), [[COPY13]](s32)
  ; CHECK:   [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY12]](s32), [[COPY13]](s32)

  ; CHECK:   [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY14]](s32), [[COPY15]](s32)
  ; CHECK:   [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY14]](s32), [[COPY15]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64)

  ; CHECK:   [[COPY16:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<8 x s64>), [[DEF]](p1) :: (store 64 into `<8 x double> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<8 x s64>), [[DEF]](p1) :: (store 64 into `<8 x double> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY17:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY16]]
  ; CHECK:   [[COPY17:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY16]]

  ; CHECK:   S_SETPC_B64_return [[COPY17]]
  ; CHECK:   S_SETPC_B64_return [[COPY17]]

  store <8 x double> %arg0, <8 x double> addrspace(1)* undef
  store <8 x double> %arg0, <8 x double> addrspace(1)* undef

  ret void
  ret void

}
}




Show All 28 Linesdefine void @void_func_v16f64(<16 x double> %arg0) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)

  ; CHECK:   [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)
  ; CHECK:   [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)

  ; CHECK:   [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY10]](s32), [[COPY11]](s32)
  ; CHECK:   [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY10]](s32), [[COPY11]](s32)

  ; CHECK:   [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY12]](s32), [[COPY13]](s32)
  ; CHECK:   [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY12]](s32), [[COPY13]](s32)

  ; CHECK:   [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY14]](s32), [[COPY15]](s32)
  ; CHECK:   [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY14]](s32), [[COPY15]](s32)

  ; CHECK:   [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY16]](s32), [[COPY17]](s32)
  ; CHECK:   [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY16]](s32), [[COPY17]](s32)

  ; CHECK:   [[MV9:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY18]](s32), [[COPY19]](s32)
  ; CHECK:   [[MV9:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY18]](s32), [[COPY19]](s32)

  ; CHECK:   [[MV10:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY20]](s32), [[COPY21]](s32)
  ; CHECK:   [[MV10:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY20]](s32), [[COPY21]](s32)

  ; CHECK:   [[MV11:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY22]](s32), [[COPY23]](s32)
  ; CHECK:   [[MV11:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY22]](s32), [[COPY23]](s32)

  ; CHECK:   [[MV12:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY24]](s32), [[COPY25]](s32)
  ; CHECK:   [[MV12:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY24]](s32), [[COPY25]](s32)

  ; CHECK:   [[MV13:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY26]](s32), [[COPY27]](s32)
  ; CHECK:   [[MV13:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY26]](s32), [[COPY27]](s32)

  ; CHECK:   [[MV14:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY28]](s32), [[COPY29]](s32)
  ; CHECK:   [[MV14:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY28]](s32), [[COPY29]](s32)

  ; CHECK:   [[MV15:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY30]](s32), [[COPY31]](s32)
  ; CHECK:   [[MV15:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64), [[MV8]](s64), [[MV9]](s64), [[MV10]](s64), [[MV11]](s64), [[MV12]](s64), [[MV13]](s64), [[MV14]](s64), [[MV15]](s64)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64), [[MV8]](s64), [[MV9]](s64), [[MV10]](s64), [[MV11]](s64), [[MV12]](s64), [[MV13]](s64), [[MV14]](s64), [[MV15]](s64)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<16 x s64>), [[DEF]](p1) :: (store 128 into `<16 x double> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<16 x s64>), [[DEF]](p1) :: (store 128 into `<16 x double> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY33]]
  ; CHECK:   S_SETPC_B64_return [[COPY33]]

  store <16 x double> %arg0, <16 x double> addrspace(1)* undef
  store <16 x double> %arg0, <16 x double> addrspace(1)* undef

  ret void
  ret void

}
}




Show All 12 Lines
}
}




define void @void_func_v3f16(<3 x half> %arg0) #0 {
define void @void_func_v3f16(<3 x half> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v3f16
  ; CHECK-LABEL: name: void_func_v3f16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[DEF]](<2 x s16>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[DEF]](<2 x s16>)

  ; CHECK:   [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
  ; CHECK:   [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[UV]](<3 x s16>), [[DEF1]](p1) :: (store 6 into `<3 x half> addrspace(1)* undef`, align 8, addrspace 1)
  ; CHECK:   G_STORE [[UV]](<3 x s16>), [[DEF1]](p1) :: (store 6 into `<3 x half> addrspace(1)* undef`, align 8, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store <3 x half> %arg0, <3 x half> addrspace(1)* undef
  store <3 x half> %arg0, <3 x half> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v4f16(<4 x half> %arg0) #0 {
define void @void_func_v4f16(<4 x half> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v4f16
  ; CHECK-LABEL: name: void_func_v4f16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[CONCAT_VECTORS]](<4 x s16>), [[DEF]](p1) :: (store 8 into `<4 x half> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[CONCAT_VECTORS]](<4 x s16>), [[DEF]](p1) :: (store 8 into `<4 x half> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY3]]
  ; CHECK:   S_SETPC_B64_return [[COPY3]]

  store <4 x half> %arg0, <4 x half> addrspace(1)* undef
  store <4 x half> %arg0, <4 x half> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v8f16(<8 x half> %arg0) #0 {
define void @void_func_v8f16(<8 x half> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v8f16
  ; CHECK-LABEL: name: void_func_v8f16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[CONCAT_VECTORS]](<8 x s16>), [[DEF]](p1) :: (store 16 into `<8 x half> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[CONCAT_VECTORS]](<8 x s16>), [[DEF]](p1) :: (store 16 into `<8 x half> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]]
  ; CHECK:   S_SETPC_B64_return [[COPY5]]

  store <8 x half> %arg0, <8 x half> addrspace(1)* undef
  store <8 x half> %arg0, <8 x half> addrspace(1)* undef

  ret void
  ret void

}
}




define void @void_func_v16f16(<16 x half> %arg0) #0 {
define void @void_func_v16f16(<16 x half> %arg0) #0 {

  ; CHECK-LABEL: name: void_func_v16f16
  ; CHECK-LABEL: name: void_func_v16f16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr7
  ; CHECK:   [[COPY7:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr7

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>), [[COPY4]](<2 x s16>), [[COPY5]](<2 x s16>), [[COPY6]](<2 x s16>), [[COPY7]](<2 x s16>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>), [[COPY4]](<2 x s16>), [[COPY5]](<2 x s16>), [[COPY6]](<2 x s16>), [[COPY7]](<2 x s16>)

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[CONCAT_VECTORS]](<16 x s16>), [[DEF]](p1) :: (store 32 into `<16 x half> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[CONCAT_VECTORS]](<16 x s16>), [[DEF]](p1) :: (store 32 into `<16 x half> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]
  ; CHECK:   [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]

  ; CHECK:   S_SETPC_B64_return [[COPY9]]
  ; CHECK:   S_SETPC_B64_return [[COPY9]]

  store <16 x half> %arg0, <16 x half> addrspace(1)* undef
  store <16 x half> %arg0, <16 x half> addrspace(1)* undef

  ret void
  ret void

}
}




; Make sure there is no alignment requirement for passed vgprs.
; Make sure there is no alignment requirement for passed vgprs.

define void @void_func_i32_i64_i32(i32 %arg0, i64 %arg1, i32 %arg2) #0 {
define void @void_func_i32_i64_i32(i32 %arg0, i64 %arg1, i32 %arg2) #0 {

  ; CHECK-LABEL: name: void_func_i32_i64_i32
  ; CHECK-LABEL: name: void_func_i32_i64_i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY5:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY5:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   G_STORE [[COPY]](s32), [[DEF]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[COPY]](s32), [[DEF]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[MV]](s64), [[COPY5]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[MV]](s64), [[COPY5]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[COPY3]](s32), [[DEF]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[COPY3]](s32), [[DEF]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY6]]
  ; CHECK:   S_SETPC_B64_return [[COPY6]]

  store volatile i32 %arg0, i32 addrspace(1)* undef
  store volatile i32 %arg0, i32 addrspace(1)* undef

▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Linesdefine void @void_func_v32i32_i32_i64(<32 x i32> %arg0, i32 %arg1, i64 %arg2) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2

  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.2, align 16, addrspace 5)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.2, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1

  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5)
  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5)

  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0

  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.0, align 8, addrspace 5)
  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.0, align 8, addrspace 5)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[LOAD2]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[LOAD2]](s32)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[LOAD]](s32), [[COPY33]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[LOAD]](s32), [[COPY33]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[MV]](s64), [[COPY34]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[MV]](s64), [[COPY34]](p1) :: (volatile store 8 into `i64 addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY35]]
  ; CHECK:   S_SETPC_B64_return [[COPY35]]

Show All 35 Linesdefine void @void_func_v32i32_i1_i8_i16(<32 x i32> %arg0, i1 %arg1, i8 %arg2, i16 %arg3, half %arg4) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3

  ; CHECK:   [[LOAD:%[0-9]+]]:_(s1) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 1 from %fixed-stack.3, align 16, addrspace 5)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(s1) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 1 from %fixed-stack.3, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2

  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 1 from %fixed-stack.2, align 4, addrspace 5)
  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 1 from %fixed-stack.2, align 4, addrspace 5)

  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1

  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 2 from %fixed-stack.1, align 8, addrspace 5)
  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 2 from %fixed-stack.1, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0

  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 2 from %fixed-stack.0, align 4, addrspace 5)
  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 2 from %fixed-stack.0, align 4, addrspace 5)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   [[COPY35:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY35:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   [[COPY36:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY36:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[LOAD]](s1), [[COPY33]](p1) :: (volatile store 1 into `i1 addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[LOAD]](s1), [[COPY33]](p1) :: (volatile store 1 into `i1 addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[LOAD1]](s8), [[COPY34]](p1) :: (volatile store 1 into `i8 addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[LOAD1]](s8), [[COPY34]](p1) :: (volatile store 1 into `i8 addrspace(1)* undef`, addrspace 1)

Show All 40 Linesdefine void @void_func_v32i32_p3_p5_i16(<32 x i32> %arg0, i8 addrspace(3)* %arg1, i8 addrspace(5)* %arg2) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1

  ; CHECK:   [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, align 16, addrspace 5)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0

  ; CHECK:   [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
  ; CHECK:   [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[LOAD]](p3), [[COPY33]](p1) :: (volatile store 4 into `i8 addrspace(3)* addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[LOAD]](p3), [[COPY33]](p1) :: (volatile store 4 into `i8 addrspace(3)* addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[LOAD1]](p5), [[COPY34]](p1) :: (volatile store 4 into `i8 addrspace(5)* addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[LOAD1]](p5), [[COPY34]](p1) :: (volatile store 4 into `i8 addrspace(5)* addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY35]]
  ; CHECK:   S_SETPC_B64_return [[COPY35]]

Show All 34 Linesdefine void @void_func_v32i32_v2i32_v2f32(<32 x i32> %arg0, <2 x i32> %arg1, <2 x float> %arg2) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3

  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2

  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)
  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)

  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1

  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5)
  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0

  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)

  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD2]](s32), [[LOAD3]](s32)
  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD2]](s32), [[LOAD3]](s32)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[BUILD_VECTOR1]](<2 x s32>), [[COPY33]](p1) :: (volatile store 8 into `<2 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR1]](<2 x s32>), [[COPY33]](p1) :: (volatile store 8 into `<2 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[BUILD_VECTOR2]](<2 x s32>), [[COPY34]](p1) :: (volatile store 8 into `<2 x float> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR2]](<2 x s32>), [[COPY34]](p1) :: (volatile store 8 into `<2 x float> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY35]]
  ; CHECK:   S_SETPC_B64_return [[COPY35]]

Show All 34 Linesdefine void @void_func_v32i32_v2i16_v2f16(<32 x i32> %arg0, <2 x i16> %arg1, <2 x half> %arg2) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1

  ; CHECK:   [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, align 16, addrspace 5)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0

  ; CHECK:   [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
  ; CHECK:   [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[LOAD]](<2 x s16>), [[COPY33]](p1) :: (volatile store 4 into `<2 x i16> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[LOAD]](<2 x s16>), [[COPY33]](p1) :: (volatile store 4 into `<2 x i16> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[LOAD1]](<2 x s16>), [[COPY34]](p1) :: (volatile store 4 into `<2 x half> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[LOAD1]](<2 x s16>), [[COPY34]](p1) :: (volatile store 4 into `<2 x half> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY35]]
  ; CHECK:   S_SETPC_B64_return [[COPY35]]

Show All 34 Linesdefine void @void_func_v32i32_v2i64_v2f64(<32 x i32> %arg0, <2 x i64> %arg1, <2 x double> %arg2) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7
  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7

  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.7, align 16, addrspace 5)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.7, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6
  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6

  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5)
  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5)

  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5
  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5

  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.5, align 8, addrspace 5)
  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.5, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4
  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4

  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5)
  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5)

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)

  ; CHECK:   [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
  ; CHECK:   [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3

  ; CHECK:   [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5)
  ; CHECK:   [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
  ; CHECK:   [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2

  ; CHECK:   [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)
  ; CHECK:   [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)

  ; CHECK:   [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
  ; CHECK:   [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1

  ; CHECK:   [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5)
  ; CHECK:   [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
  ; CHECK:   [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0

  ; CHECK:   [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
  ; CHECK:   [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD4]](s32), [[LOAD5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD4]](s32), [[LOAD5]](s32)

  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD6]](s32), [[LOAD7]](s32)
  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD6]](s32), [[LOAD7]](s32)

  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV3]](s64)
  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV3]](s64)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[BUILD_VECTOR1]](<2 x s64>), [[COPY33]](p1) :: (volatile store 16 into `<2 x i64> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR1]](<2 x s64>), [[COPY33]](p1) :: (volatile store 16 into `<2 x i64> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[BUILD_VECTOR2]](<2 x s64>), [[COPY34]](p1) :: (volatile store 16 into `<2 x double> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR2]](<2 x s64>), [[COPY34]](p1) :: (volatile store 16 into `<2 x double> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY35]]
  ; CHECK:   S_SETPC_B64_return [[COPY35]]

Show All 34 Linesdefine void @void_func_v32i32_v4i32_v4f32(<32 x i32> %arg0, <4 x i32> %arg1, <4 x float> %arg2) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7
  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7

  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.7, align 16, addrspace 5)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.7, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6
  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6

  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5)
  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5)

  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5
  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5

  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.5, align 8, addrspace 5)
  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.5, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4
  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4

  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5)
  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)

  ; CHECK:   [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
  ; CHECK:   [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3

  ; CHECK:   [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5)
  ; CHECK:   [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
  ; CHECK:   [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2

  ; CHECK:   [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)
  ; CHECK:   [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)

  ; CHECK:   [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
  ; CHECK:   [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1

  ; CHECK:   [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5)
  ; CHECK:   [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
  ; CHECK:   [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0

  ; CHECK:   [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
  ; CHECK:   [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)

  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[BUILD_VECTOR1]](<4 x s32>), [[COPY33]](p1) :: (volatile store 16 into `<4 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR1]](<4 x s32>), [[COPY33]](p1) :: (volatile store 16 into `<4 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[BUILD_VECTOR2]](<4 x s32>), [[COPY34]](p1) :: (volatile store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR2]](<4 x s32>), [[COPY34]](p1) :: (volatile store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY35]]
  ; CHECK:   S_SETPC_B64_return [[COPY35]]

Show All 34 Linesdefine void @void_func_v32i32_v8i32_v8f32(<32 x i32> %arg0, <8 x i32> %arg1, <8 x float> %arg2) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.15
  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.15

  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.15, align 16, addrspace 5)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.15, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.14
  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.14

  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.14, addrspace 5)
  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.14, addrspace 5)

  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.13
  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.13

  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.13, align 8, addrspace 5)
  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.13, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.12
  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.12

  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.12, addrspace 5)
  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.12, addrspace 5)

  ; CHECK:   [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.11
  ; CHECK:   [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.11

  ; CHECK:   [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.11, align 16, addrspace 5)
  ; CHECK:   [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.11, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.10
  ; CHECK:   [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.10

  ; CHECK:   [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.10, addrspace 5)
  ; CHECK:   [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.10, addrspace 5)

  ; CHECK:   [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.9
  ; CHECK:   [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.9

  ; CHECK:   [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.9, align 8, addrspace 5)
  ; CHECK:   [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.9, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.8
  ; CHECK:   [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.8

  ; CHECK:   [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.8, addrspace 5)
  ; CHECK:   [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.8, addrspace 5)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)

  ; CHECK:   [[FRAME_INDEX8:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7
  ; CHECK:   [[FRAME_INDEX8:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7

  ; CHECK:   [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p5) :: (invariant load 4 from %fixed-stack.7, align 16, addrspace 5)
  ; CHECK:   [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p5) :: (invariant load 4 from %fixed-stack.7, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX9:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6
  ; CHECK:   [[FRAME_INDEX9:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6

  ; CHECK:   [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5)
  ; CHECK:   [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5)

  ; CHECK:   [[FRAME_INDEX10:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5
  ; CHECK:   [[FRAME_INDEX10:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5

  ; CHECK:   [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p5) :: (invariant load 4 from %fixed-stack.5, align 8, addrspace 5)
  ; CHECK:   [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p5) :: (invariant load 4 from %fixed-stack.5, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX11:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4
  ; CHECK:   [[FRAME_INDEX11:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4

  ; CHECK:   [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5)
  ; CHECK:   [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5)

  ; CHECK:   [[FRAME_INDEX12:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
  ; CHECK:   [[FRAME_INDEX12:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3

  ; CHECK:   [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5)
  ; CHECK:   [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX13:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
  ; CHECK:   [[FRAME_INDEX13:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2

  ; CHECK:   [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)
  ; CHECK:   [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)

  ; CHECK:   [[FRAME_INDEX14:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
  ; CHECK:   [[FRAME_INDEX14:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1

  ; CHECK:   [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5)
  ; CHECK:   [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX15:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
  ; CHECK:   [[FRAME_INDEX15:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0

  ; CHECK:   [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
  ; CHECK:   [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)

  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[BUILD_VECTOR1]](<8 x s32>), [[COPY33]](p1) :: (volatile store 32 into `<8 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR1]](<8 x s32>), [[COPY33]](p1) :: (volatile store 32 into `<8 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[BUILD_VECTOR2]](<8 x s32>), [[COPY34]](p1) :: (volatile store 32 into `<8 x float> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR2]](<8 x s32>), [[COPY34]](p1) :: (volatile store 32 into `<8 x float> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY35]]
  ; CHECK:   S_SETPC_B64_return [[COPY35]]

Show All 34 Linesdefine void @void_func_v32i32_v16i32_v16f32(<32 x i32> %arg0, <16 x i32> %arg1, <16 x float> %arg2) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.31
  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.31

  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.31, align 16, addrspace 5)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.31, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.30
  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.30

  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.30, addrspace 5)
  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.30, addrspace 5)

  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.29
  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.29

  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.29, align 8, addrspace 5)
  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.29, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.28
  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.28

  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.28, addrspace 5)
  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.28, addrspace 5)

Show All 16 Linesdefine void @void_func_v32i32_v16i32_v16f32(<32 x i32> %arg0, <16 x i32> %arg1, <16 x float> %arg2) #0 {

  ; CHECK:   [[FRAME_INDEX12:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.19
  ; CHECK:   [[FRAME_INDEX12:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.19

  ; CHECK:   [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p5) :: (invariant load 4 from %fixed-stack.19, align 16, addrspace 5)
  ; CHECK:   [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p5) :: (invariant load 4 from %fixed-stack.19, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX13:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.18
  ; CHECK:   [[FRAME_INDEX13:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.18

  ; CHECK:   [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p5) :: (invariant load 4 from %fixed-stack.18, addrspace 5)
  ; CHECK:   [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p5) :: (invariant load 4 from %fixed-stack.18, addrspace 5)

  ; CHECK:   [[FRAME_INDEX14:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.17
  ; CHECK:   [[FRAME_INDEX14:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.17

  ; CHECK:   [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p5) :: (invariant load 4 from %fixed-stack.17, align 8, addrspace 5)
  ; CHECK:   [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p5) :: (invariant load 4 from %fixed-stack.17, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX15:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.16
  ; CHECK:   [[FRAME_INDEX15:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.16

  ; CHECK:   [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p5) :: (invariant load 4 from %fixed-stack.16, addrspace 5)
  ; CHECK:   [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p5) :: (invariant load 4 from %fixed-stack.16, addrspace 5)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)

  ; CHECK:   [[FRAME_INDEX16:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.15
  ; CHECK:   [[FRAME_INDEX16:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.15

  ; CHECK:   [[LOAD16:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX16]](p5) :: (invariant load 4 from %fixed-stack.15, align 16, addrspace 5)
  ; CHECK:   [[LOAD16:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX16]](p5) :: (invariant load 4 from %fixed-stack.15, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX17:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.14
  ; CHECK:   [[FRAME_INDEX17:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.14

  ; CHECK:   [[LOAD17:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX17]](p5) :: (invariant load 4 from %fixed-stack.14, addrspace 5)
  ; CHECK:   [[LOAD17:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX17]](p5) :: (invariant load 4 from %fixed-stack.14, addrspace 5)

  ; CHECK:   [[FRAME_INDEX18:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.13
  ; CHECK:   [[FRAME_INDEX18:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.13

  ; CHECK:   [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX18]](p5) :: (invariant load 4 from %fixed-stack.13, align 8, addrspace 5)
  ; CHECK:   [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX18]](p5) :: (invariant load 4 from %fixed-stack.13, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX19:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.12
  ; CHECK:   [[FRAME_INDEX19:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.12

  ; CHECK:   [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX19]](p5) :: (invariant load 4 from %fixed-stack.12, addrspace 5)
  ; CHECK:   [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX19]](p5) :: (invariant load 4 from %fixed-stack.12, addrspace 5)

Show All 16 Linesdefine void @void_func_v32i32_v16i32_v16f32(<32 x i32> %arg0, <16 x i32> %arg1, <16 x float> %arg2) #0 {

  ; CHECK:   [[FRAME_INDEX28:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
  ; CHECK:   [[FRAME_INDEX28:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3

  ; CHECK:   [[LOAD28:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX28]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5)
  ; CHECK:   [[LOAD28:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX28]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX29:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
  ; CHECK:   [[FRAME_INDEX29:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2

  ; CHECK:   [[LOAD29:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX29]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)
  ; CHECK:   [[LOAD29:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX29]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)

  ; CHECK:   [[FRAME_INDEX30:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
  ; CHECK:   [[FRAME_INDEX30:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1

  ; CHECK:   [[LOAD30:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX30]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5)
  ; CHECK:   [[LOAD30:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX30]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX31:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
  ; CHECK:   [[FRAME_INDEX31:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0

  ; CHECK:   [[LOAD31:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX31]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
  ; CHECK:   [[LOAD31:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX31]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)

  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD16]](s32), [[LOAD17]](s32), [[LOAD18]](s32), [[LOAD19]](s32), [[LOAD20]](s32), [[LOAD21]](s32), [[LOAD22]](s32), [[LOAD23]](s32), [[LOAD24]](s32), [[LOAD25]](s32), [[LOAD26]](s32), [[LOAD27]](s32), [[LOAD28]](s32), [[LOAD29]](s32), [[LOAD30]](s32), [[LOAD31]](s32)
  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD16]](s32), [[LOAD17]](s32), [[LOAD18]](s32), [[LOAD19]](s32), [[LOAD20]](s32), [[LOAD21]](s32), [[LOAD22]](s32), [[LOAD23]](s32), [[LOAD24]](s32), [[LOAD25]](s32), [[LOAD26]](s32), [[LOAD27]](s32), [[LOAD28]](s32), [[LOAD29]](s32), [[LOAD30]](s32), [[LOAD31]](s32)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[BUILD_VECTOR1]](<16 x s32>), [[COPY33]](p1) :: (volatile store 64 into `<16 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR1]](<16 x s32>), [[COPY33]](p1) :: (volatile store 64 into `<16 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[BUILD_VECTOR2]](<16 x s32>), [[COPY34]](p1) :: (volatile store 64 into `<16 x float> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR2]](<16 x s32>), [[COPY34]](p1) :: (volatile store 64 into `<16 x float> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY35:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY35]]
  ; CHECK:   S_SETPC_B64_return [[COPY35]]

  store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef
  store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef

  store volatile <16 x i32> %arg1, <16 x i32> addrspace(1)* undef
  store volatile <16 x i32> %arg1, <16 x i32> addrspace(1)* undef

  store volatile <16 x float> %arg2, <16 x float> addrspace(1)* undef
  store volatile <16 x float> %arg2, <16 x float> addrspace(1)* undef

  ret void
  ret void

}
}




; Make sure v3 isn't a wasted register because of v3 types being promoted to v4
; Make sure v3 isn't a wasted register because of v3 types being promoted to v4

define void @void_func_v3f32_wasted_reg(<3 x float> %arg0, i32 %arg1) #0 {
define void @void_func_v3f32_wasted_reg(<3 x float> %arg0, i32 %arg1) #0 {

  ; CHECK-LABEL: name: void_func_v3f32_wasted_reg
  ; CHECK-LABEL: name: void_func_v3f32_wasted_reg

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1

  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2

  ; CHECK:   [[DEF:%[0-9]+]]:_(p3) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p3) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY5:%[0-9]+]]:_(p3) = COPY [[DEF]](p3)
  ; CHECK:   [[COPY5:%[0-9]+]]:_(p3) = COPY [[DEF]](p3)

  ; CHECK:   [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C]](s32)
  ; CHECK:   [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C]](s32)

  ; CHECK:   [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C1]](s32)
  ; CHECK:   [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C1]](s32)

  ; CHECK:   [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C2]](s32)
  ; CHECK:   [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C2]](s32)

Show All 15 Lines



define void @void_func_v3i32_wasted_reg(<3 x i32> %arg0, i32 %arg1) #0 {
define void @void_func_v3i32_wasted_reg(<3 x i32> %arg0, i32 %arg1) #0 {

  ; CHECK-LABEL: name: void_func_v3i32_wasted_reg
  ; CHECK-LABEL: name: void_func_v3i32_wasted_reg

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1

  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2

  ; CHECK:   [[DEF:%[0-9]+]]:_(p3) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p3) = G_IMPLICIT_DEF

  ; CHECK:   [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C]](s32)
  ; CHECK:   [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C]](s32)

  ; CHECK:   [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C1]](s32)
  ; CHECK:   [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C1]](s32)

  ; CHECK:   [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C2]](s32)
  ; CHECK:   [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C2]](s32)

  ; CHECK:   G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store 4 into `i32 addrspace(3)* undef`, addrspace 3)
  ; CHECK:   G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store 4 into `i32 addrspace(3)* undef`, addrspace 3)

▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesdefine void @void_func_v16i8(<16 x i8> %arg0) #0 {

  ; CHECK:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12
  ; CHECK:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12

  ; CHECK:   [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[COPY12]](s32)
  ; CHECK:   [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[COPY12]](s32)

  ; CHECK:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
  ; CHECK:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13

  ; CHECK:   [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[COPY13]](s32)
  ; CHECK:   [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[COPY13]](s32)

  ; CHECK:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
  ; CHECK:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14

  ; CHECK:   [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[COPY14]](s32)
  ; CHECK:   [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[COPY14]](s32)

  ; CHECK:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
  ; CHECK:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15

  ; CHECK:   [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[COPY15]](s32)
  ; CHECK:   [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[COPY15]](s32)

  ; CHECK:   [[COPY16:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16), [[TRUNC4]](s16), [[TRUNC5]](s16), [[TRUNC6]](s16), [[TRUNC7]](s16), [[TRUNC8]](s16), [[TRUNC9]](s16), [[TRUNC10]](s16), [[TRUNC11]](s16), [[TRUNC12]](s16), [[TRUNC13]](s16), [[TRUNC14]](s16), [[TRUNC15]](s16)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16), [[TRUNC4]](s16), [[TRUNC5]](s16), [[TRUNC6]](s16), [[TRUNC7]](s16), [[TRUNC8]](s16), [[TRUNC9]](s16), [[TRUNC10]](s16), [[TRUNC11]](s16), [[TRUNC12]](s16), [[TRUNC13]](s16), [[TRUNC14]](s16), [[TRUNC15]](s16)

  ; CHECK:   [[TRUNC16:%[0-9]+]]:_(<16 x s8>) = G_TRUNC [[BUILD_VECTOR]](<16 x s16>)
  ; CHECK:   [[TRUNC16:%[0-9]+]]:_(<16 x s8>) = G_TRUNC [[BUILD_VECTOR]](<16 x s16>)

  ; CHECK:   [[COPY16:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   G_STORE [[TRUNC16]](<16 x s8>), [[DEF]](p1) :: (volatile store 16 into `<16 x i8> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[TRUNC16]](<16 x s8>), [[DEF]](p1) :: (volatile store 16 into `<16 x i8> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY17:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY16]]
  ; CHECK:   [[COPY17:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY16]]

  ; CHECK:   S_SETPC_B64_return [[COPY17]]
  ; CHECK:   S_SETPC_B64_return [[COPY17]]

  store volatile <16 x i8> %arg0, <16 x i8> addrspace(1)* undef
  store volatile <16 x i8> %arg0, <16 x i8> addrspace(1)* undef

  ret void
  ret void

}
}




Show All 29 Linesdefine void @void_func_v32i32_v16i8(<32 x i32> %arg0, <16 x i8> %arg1) #0 {

  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
  ; CHECK:   [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24

  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
  ; CHECK:   [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25

  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
  ; CHECK:   [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26

  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
  ; CHECK:   [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27

  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
  ; CHECK:   [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28

  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
  ; CHECK:   [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29

  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
  ; CHECK:   [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30

  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
  ; CHECK:   [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.15
  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.15

  ; CHECK:   [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 2 from %fixed-stack.15, align 16, addrspace 5)
  ; CHECK:   [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 2 from %fixed-stack.15, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.14
  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.14

  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 2 from %fixed-stack.14, align 4, addrspace 5)
  ; CHECK:   [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 2 from %fixed-stack.14, align 4, addrspace 5)

  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.13
  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.13

  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 2 from %fixed-stack.13, align 8, addrspace 5)
  ; CHECK:   [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 2 from %fixed-stack.13, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.12
  ; CHECK:   [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.12

  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 2 from %fixed-stack.12, align 4, addrspace 5)
  ; CHECK:   [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 2 from %fixed-stack.12, align 4, addrspace 5)

Show All 16 Linesdefine void @void_func_v32i32_v16i8(<32 x i32> %arg0, <16 x i8> %arg1) #0 {

  ; CHECK:   [[FRAME_INDEX12:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
  ; CHECK:   [[FRAME_INDEX12:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3

  ; CHECK:   [[LOAD12:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX12]](p5) :: (invariant load 2 from %fixed-stack.3, align 16, addrspace 5)
  ; CHECK:   [[LOAD12:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX12]](p5) :: (invariant load 2 from %fixed-stack.3, align 16, addrspace 5)

  ; CHECK:   [[FRAME_INDEX13:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
  ; CHECK:   [[FRAME_INDEX13:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2

  ; CHECK:   [[LOAD13:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX13]](p5) :: (invariant load 2 from %fixed-stack.2, align 4, addrspace 5)
  ; CHECK:   [[LOAD13:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX13]](p5) :: (invariant load 2 from %fixed-stack.2, align 4, addrspace 5)

  ; CHECK:   [[FRAME_INDEX14:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
  ; CHECK:   [[FRAME_INDEX14:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1

  ; CHECK:   [[LOAD14:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX14]](p5) :: (invariant load 2 from %fixed-stack.1, align 8, addrspace 5)
  ; CHECK:   [[LOAD14:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX14]](p5) :: (invariant load 2 from %fixed-stack.1, align 8, addrspace 5)

  ; CHECK:   [[FRAME_INDEX15:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
  ; CHECK:   [[FRAME_INDEX15:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0

  ; CHECK:   [[LOAD15:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX15]](p5) :: (invariant load 2 from %fixed-stack.0, align 4, addrspace 5)
  ; CHECK:   [[LOAD15:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX15]](p5) :: (invariant load 2 from %fixed-stack.0, align 4, addrspace 5)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s16>) = G_BUILD_VECTOR [[LOAD]](s16), [[LOAD1]](s16), [[LOAD2]](s16), [[LOAD3]](s16), [[LOAD4]](s16), [[LOAD5]](s16), [[LOAD6]](s16), [[LOAD7]](s16), [[LOAD8]](s16), [[LOAD9]](s16), [[LOAD10]](s16), [[LOAD11]](s16), [[LOAD12]](s16), [[LOAD13]](s16), [[LOAD14]](s16), [[LOAD15]](s16)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s16>) = G_BUILD_VECTOR [[LOAD]](s16), [[LOAD1]](s16), [[LOAD2]](s16), [[LOAD3]](s16), [[LOAD4]](s16), [[LOAD5]](s16), [[LOAD6]](s16), [[LOAD7]](s16), [[LOAD8]](s16), [[LOAD9]](s16), [[LOAD10]](s16), [[LOAD11]](s16), [[LOAD12]](s16), [[LOAD13]](s16), [[LOAD14]](s16), [[LOAD15]](s16)

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(<16 x s8>) = G_TRUNC [[BUILD_VECTOR1]](<16 x s16>)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(<16 x s8>) = G_TRUNC [[BUILD_VECTOR1]](<16 x s16>)

  ; CHECK:   [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
  ; CHECK:   [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)

  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   G_STORE [[TRUNC]](<16 x s8>), [[COPY33]](p1) :: (volatile store 16 into `<16 x i8> addrspace(1)* undef`, addrspace 1)
  ; CHECK:   G_STORE [[TRUNC]](<16 x s8>), [[COPY33]](p1) :: (volatile store 16 into `<16 x i8> addrspace(1)* undef`, addrspace 1)

  ; CHECK:   [[COPY34:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
  ; CHECK:   [[COPY34:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]

  ; CHECK:   S_SETPC_B64_return [[COPY34]]
  ; CHECK:   S_SETPC_B64_return [[COPY34]]

  store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef
  store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef

  store volatile <16 x i8> %arg1, <16 x i8> addrspace(1)* undef
  store volatile <16 x i8> %arg1, <16 x i8> addrspace(1)* undef

  ret void
  ret void

}
}




attributes #0 = { nounwind }
attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -stop-after=irtranslator -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -stop-after=irtranslator -o - %s | FileCheck %s




; Test 64-bit pointer with 64-bit index
; Test 64-bit pointer with 64-bit index

define <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_v2i64(<2 x i32 addrspace(1)*> %ptr, <2 x i64> %idx) {
define <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_v2i64(<2 x i32 addrspace(1)*> %ptr, <2 x i64> %idx) {

  ; CHECK-LABEL: name: vector_gep_v2p1_index_v2i64
  ; CHECK-LABEL: name: vector_gep_v2p1_index_v2i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV3]](s64)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV3]](s64)

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4

  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)

  ; CHECK:   [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
  ; CHECK:   [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]

  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)

  ; CHECK:   [[COPY9:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
  ; CHECK:   [[COPY9:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY9]](<2 x p1>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY9]](<2 x p1>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   $vgpr2 = COPY [[UV2]](s32)
  ; CHECK:   $vgpr2 = COPY [[UV2]](s32)

  ; CHECK:   $vgpr3 = COPY [[UV3]](s32)
  ; CHECK:   $vgpr3 = COPY [[UV3]](s32)

  ; CHECK:   [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]
  ; CHECK:   [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]

  ; CHECK:   S_SETPC_B64_return [[COPY10]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; CHECK:   S_SETPC_B64_return [[COPY10]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  %gep = getelementptr i32, <2 x i32 addrspace(1)*> %ptr, <2 x i64> %idx
  %gep = getelementptr i32, <2 x i32 addrspace(1)*> %ptr, <2 x i64> %idx

  ret <2 x i32 addrspace(1)*> %gep
  ret <2 x i32 addrspace(1)*> %gep

}
}




; Test 32-bit pointer with 32-bit index
; Test 32-bit pointer with 32-bit index

define <2 x i32 addrspace(3)*> @vector_gep_v2p3_index_v2i32(<2 x i32 addrspace(3)*> %ptr, <2 x i32> %idx) {
define <2 x i32 addrspace(3)*> @vector_gep_v2p3_index_v2i32(<2 x i32 addrspace(3)*> %ptr, <2 x i32> %idx) {

  ; CHECK-LABEL: name: vector_gep_v2p3_index_v2i32
  ; CHECK-LABEL: name: vector_gep_v2p3_index_v2i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY]](p3), [[COPY1]](p3)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY]](p3), [[COPY1]](p3)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4

  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)

  ; CHECK:   [[MUL:%[0-9]+]]:_(<2 x s32>) = G_MUL [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
  ; CHECK:   [[MUL:%[0-9]+]]:_(<2 x s32>) = G_MUL [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]

  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(<2 x p3>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s32>)
  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(<2 x p3>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s32>)

  ; CHECK:   [[COPY5:%[0-9]+]]:_(<2 x p3>) = COPY [[PTR_ADD]](<2 x p3>)
  ; CHECK:   [[COPY5:%[0-9]+]]:_(<2 x p3>) = COPY [[PTR_ADD]](<2 x p3>)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY5]](<2 x p3>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY5]](<2 x p3>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY6]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY6]], implicit $vgpr0, implicit $vgpr1

  %gep = getelementptr i32, <2 x i32 addrspace(3)*> %ptr, <2 x i32> %idx
  %gep = getelementptr i32, <2 x i32 addrspace(3)*> %ptr, <2 x i32> %idx

  ret <2 x i32 addrspace(3)*> %gep
  ret <2 x i32 addrspace(3)*> %gep

}
}




; Test 64-bit pointer with 32-bit index
; Test 64-bit pointer with 32-bit index

define <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_v2i32(<2 x i32 addrspace(1)*> %ptr, <2 x i32> %idx) {
define <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_v2i32(<2 x i32 addrspace(1)*> %ptr, <2 x i32> %idx) {

  ; CHECK-LABEL: name: vector_gep_v2p1_index_v2i32
  ; CHECK-LABEL: name: vector_gep_v2p1_index_v2i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[BUILD_VECTOR1]](<2 x s32>)
  ; CHECK:   [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[BUILD_VECTOR1]](<2 x s32>)

  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4

  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)

  ; CHECK:   [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[SEXT]], [[BUILD_VECTOR2]]
  ; CHECK:   [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[SEXT]], [[BUILD_VECTOR2]]

  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)

  ; CHECK:   [[COPY7:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
  ; CHECK:   [[COPY7:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY7]](<2 x p1>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY7]](<2 x p1>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

Show All 10 Lines
define <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_i64(<2 x i32 addrspace(1)*> %ptr, i64 %idx) {
define <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_i64(<2 x i32 addrspace(1)*> %ptr, i64 %idx) {

  ; CHECK-LABEL: name: vector_gep_v2p1_index_i64
  ; CHECK-LABEL: name: vector_gep_v2p1_index_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV2]](s64)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV2]](s64)

  ; CHECK:   [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY [[BUILD_VECTOR1]](<2 x s64>)
  ; CHECK:   [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY [[BUILD_VECTOR1]](<2 x s64>)

  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4

  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)

  ; CHECK:   [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[COPY7]], [[BUILD_VECTOR2]]
  ; CHECK:   [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[COPY7]], [[BUILD_VECTOR2]]

  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)

  ; CHECK:   [[COPY8:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
  ; CHECK:   [[COPY8:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY8]](<2 x p1>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY8]](<2 x p1>)

Show All 11 Lines
define <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_i32(<2 x i32 addrspace(1)*> %ptr, i32 %idx) {
define <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_i32(<2 x i32 addrspace(1)*> %ptr, i32 %idx) {

  ; CHECK-LABEL: name: vector_gep_v2p1_index_i32
  ; CHECK-LABEL: name: vector_gep_v2p1_index_i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY4]](s32)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY4]](s32)

  ; CHECK:   [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[BUILD_VECTOR1]](<2 x s32>)
  ; CHECK:   [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[BUILD_VECTOR1]](<2 x s32>)

  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4

  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)

  ; CHECK:   [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[SEXT]], [[BUILD_VECTOR2]]
  ; CHECK:   [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[SEXT]], [[BUILD_VECTOR2]]

  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)

  ; CHECK:   [[COPY6:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
  ; CHECK:   [[COPY6:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY6]](<2 x p1>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY6]](<2 x p1>)

Show All 11 Lines
define <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_v2i64_constant(<2 x i32 addrspace(1)*> %ptr, <2 x i64> %idx) {
define <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_v2i64_constant(<2 x i32 addrspace(1)*> %ptr, <2 x i64> %idx) {

  ; CHECK-LABEL: name: vector_gep_v2p1_index_v2i64_constant
  ; CHECK-LABEL: name: vector_gep_v2p1_index_v2i64_constant

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)

  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; CHECK:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)

  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; CHECK:   [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)

  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
  ; CHECK:   [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV3]](s64)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV3]](s64)

  ; CHECK:   [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1

  ; CHECK:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
  ; CHECK:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2

  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64)
  ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64)

  ; CHECK:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
  ; CHECK:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4

  ; CHECK:   [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64)
  ; CHECK:   [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64)

  ; CHECK:   [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[BUILD_VECTOR2]], [[BUILD_VECTOR3]]
  ; CHECK:   [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[BUILD_VECTOR2]], [[BUILD_VECTOR3]]

  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)

  ; CHECK:   [[COPY9:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
  ; CHECK:   [[COPY9:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)

Show All 10 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
}
}




define amdgpu_gfx void @test_gfx_indirect_call_sgpr_ptr(void()* %fptr) {
define amdgpu_gfx void @test_gfx_indirect_call_sgpr_ptr(void()* %fptr) {

  ; CHECK-LABEL: name: test_gfx_indirect_call_sgpr_ptr
  ; CHECK-LABEL: name: test_gfx_indirect_call_sgpr_ptr

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:sreg_64(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:sreg_64(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   ADJCALLSTACKUP 0, 0, implicit-def $scc
  ; CHECK:   ADJCALLSTACKUP 0, 0, implicit-def $scc

  ; CHECK:   [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3

  ; CHECK:   $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY3]](<4 x s32>)
  ; CHECK:   $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY3]](<4 x s32>)

  ; CHECK:   $sgpr30_sgpr31 = SI_CALL [[MV]](p0), 0, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3
  ; CHECK:   $sgpr30_sgpr31 = SI_CALL [[MV]](p0), 0, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3

  ; CHECK:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc
  ; CHECK:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call amdgpu_gfx void %fptr()
  call amdgpu_gfx void %fptr()

  ret void
  ret void

}
}

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -march=amdgcn -O0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
; RUN: llc -global-isel -march=amdgcn -O0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s




; Size operand should be the minimum of the two pointer sizes.
; Size operand should be the minimum of the two pointer sizes.




define void @test_memcpy_p1_p3_i64(i8 addrspace(1)* %dst, i8 addrspace(3)* %src) {
define void @test_memcpy_p1_p3_i64(i8 addrspace(1)* %dst, i8 addrspace(3)* %src) {

  ; CHECK-LABEL: name: test_memcpy_p1_p3_i64
  ; CHECK-LABEL: name: test_memcpy_p1_p3_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256
  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)

  ; CHECK:   G_MEMCPY [[MV]](p1), [[COPY2]](p3), [[TRUNC]](s32), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 3)
  ; CHECK:   G_MEMCPY [[MV]](p1), [[COPY2]](p3), [[TRUNC]](s32), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 3)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call void @llvm.memcpy.p1i8.p3i8.i64(i8 addrspace(1)* %dst, i8 addrspace(3)* %src, i64 256, i1 false)
  call void @llvm.memcpy.p1i8.p3i8.i64(i8 addrspace(1)* %dst, i8 addrspace(3)* %src, i64 256, i1 false)

  ret void
  ret void

}
}




define void @test_memcpy_p1_p3_i32(i8 addrspace(1)* %dst, i8 addrspace(3)* %src) {
define void @test_memcpy_p1_p3_i32(i8 addrspace(1)* %dst, i8 addrspace(3)* %src) {

  ; CHECK-LABEL: name: test_memcpy_p1_p3_i32
  ; CHECK-LABEL: name: test_memcpy_p1_p3_i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256

  ; CHECK:   G_MEMCPY [[MV]](p1), [[COPY2]](p3), [[C]](s32), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 3)
  ; CHECK:   G_MEMCPY [[MV]](p1), [[COPY2]](p3), [[C]](s32), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 3)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %dst, i8 addrspace(3)* %src, i32 256, i1 false)
  call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %dst, i8 addrspace(3)* %src, i32 256, i1 false)

  ret void
  ret void

}
}




define void @test_memcpy_p1_p3_i16(i8 addrspace(1)* %dst, i8 addrspace(3)* %src) {
define void @test_memcpy_p1_p3_i16(i8 addrspace(1)* %dst, i8 addrspace(3)* %src) {

  ; CHECK-LABEL: name: test_memcpy_p1_p3_i16
  ; CHECK-LABEL: name: test_memcpy_p1_p3_i16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 256
  ; CHECK:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 256

  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s16)
  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s16)

  ; CHECK:   G_MEMCPY [[MV]](p1), [[COPY2]](p3), [[ZEXT]](s32), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 3)
  ; CHECK:   G_MEMCPY [[MV]](p1), [[COPY2]](p3), [[ZEXT]](s32), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 3)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call void @llvm.memcpy.p1i8.p3i8.i16(i8 addrspace(1)* %dst, i8 addrspace(3)* %src, i16 256, i1 false)
  call void @llvm.memcpy.p1i8.p3i8.i16(i8 addrspace(1)* %dst, i8 addrspace(3)* %src, i16 256, i1 false)

  ret void
  ret void

}
}




define void @test_memcpy_p3_p1_i64(i8 addrspace(3)* %dst, i8 addrspace(1)* %src) {
define void @test_memcpy_p3_p1_i64(i8 addrspace(3)* %dst, i8 addrspace(1)* %src) {

  ; CHECK-LABEL: name: test_memcpy_p3_p1_i64
  ; CHECK-LABEL: name: test_memcpy_p3_p1_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256
  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)

  ; CHECK:   G_MEMCPY [[COPY]](p3), [[MV]](p1), [[TRUNC]](s32), 0 :: (store 1 into %ir.dst, addrspace 3), (load 1 from %ir.src, addrspace 1)
  ; CHECK:   G_MEMCPY [[COPY]](p3), [[MV]](p1), [[TRUNC]](s32), 0 :: (store 1 into %ir.dst, addrspace 3), (load 1 from %ir.src, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call void @llvm.memcpy.p3i8.p1i8.i64(i8 addrspace(3)* %dst, i8 addrspace(1)* %src, i64 256, i1 false)
  call void @llvm.memcpy.p3i8.p1i8.i64(i8 addrspace(3)* %dst, i8 addrspace(1)* %src, i64 256, i1 false)

  ret void
  ret void

}
}




define void @test_memcpy_p3_p1_i32(i8 addrspace(3)* %dst, i8 addrspace(1)* %src) {
define void @test_memcpy_p3_p1_i32(i8 addrspace(3)* %dst, i8 addrspace(1)* %src) {

  ; CHECK-LABEL: name: test_memcpy_p3_p1_i32
  ; CHECK-LABEL: name: test_memcpy_p3_p1_i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256

  ; CHECK:   G_MEMCPY [[COPY]](p3), [[MV]](p1), [[C]](s32), 0 :: (store 1 into %ir.dst, addrspace 3), (load 1 from %ir.src, addrspace 1)
  ; CHECK:   G_MEMCPY [[COPY]](p3), [[MV]](p1), [[C]](s32), 0 :: (store 1 into %ir.dst, addrspace 3), (load 1 from %ir.src, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %dst, i8 addrspace(1)* %src, i32 256, i1 false)
  call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %dst, i8 addrspace(1)* %src, i32 256, i1 false)

  ret void
  ret void

}
}




define void @test_memcpy_p3_p1_i16(i8 addrspace(3)* %dst, i8 addrspace(1)* %src) {
define void @test_memcpy_p3_p1_i16(i8 addrspace(3)* %dst, i8 addrspace(1)* %src) {

  ; CHECK-LABEL: name: test_memcpy_p3_p1_i16
  ; CHECK-LABEL: name: test_memcpy_p3_p1_i16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 256
  ; CHECK:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 256

  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s16)
  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s16)

  ; CHECK:   G_MEMCPY [[COPY]](p3), [[MV]](p1), [[ZEXT]](s32), 0 :: (store 1 into %ir.dst, addrspace 3), (load 1 from %ir.src, addrspace 1)
  ; CHECK:   G_MEMCPY [[COPY]](p3), [[MV]](p1), [[ZEXT]](s32), 0 :: (store 1 into %ir.dst, addrspace 3), (load 1 from %ir.src, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call void @llvm.memcpy.p3i8.p1i8.i16(i8 addrspace(3)* %dst, i8 addrspace(1)* %src, i16 256, i1 false)
  call void @llvm.memcpy.p3i8.p1i8.i16(i8 addrspace(3)* %dst, i8 addrspace(1)* %src, i16 256, i1 false)

  ret void
  ret void

}
}




define void @test_memmove_p1_p3_i64(i8 addrspace(1)* %dst, i8 addrspace(3)* %src) {
define void @test_memmove_p1_p3_i64(i8 addrspace(1)* %dst, i8 addrspace(3)* %src) {

  ; CHECK-LABEL: name: test_memmove_p1_p3_i64
  ; CHECK-LABEL: name: test_memmove_p1_p3_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256
  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)

  ; CHECK:   G_MEMMOVE [[MV]](p1), [[COPY2]](p3), [[TRUNC]](s32), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 3)
  ; CHECK:   G_MEMMOVE [[MV]](p1), [[COPY2]](p3), [[TRUNC]](s32), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 3)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call void @llvm.memmove.p1i8.p3i8.i64(i8 addrspace(1)* %dst, i8 addrspace(3)* %src, i64 256, i1 false)
  call void @llvm.memmove.p1i8.p3i8.i64(i8 addrspace(1)* %dst, i8 addrspace(3)* %src, i64 256, i1 false)

  ret void
  ret void

}
}




define void @test_memmove_p1_p3_i32(i8 addrspace(1)* %dst, i8 addrspace(3)* %src) {
define void @test_memmove_p1_p3_i32(i8 addrspace(1)* %dst, i8 addrspace(3)* %src) {

  ; CHECK-LABEL: name: test_memmove_p1_p3_i32
  ; CHECK-LABEL: name: test_memmove_p1_p3_i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256

  ; CHECK:   G_MEMMOVE [[MV]](p1), [[COPY2]](p3), [[C]](s32), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 3)
  ; CHECK:   G_MEMMOVE [[MV]](p1), [[COPY2]](p3), [[C]](s32), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 3)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call void @llvm.memmove.p1i8.p3i8.i32(i8 addrspace(1)* %dst, i8 addrspace(3)* %src, i32 256, i1 false)
  call void @llvm.memmove.p1i8.p3i8.i32(i8 addrspace(1)* %dst, i8 addrspace(3)* %src, i32 256, i1 false)

  ret void
  ret void

}
}




define void @test_memmove_p1_p3_i16(i8 addrspace(1)* %dst, i8 addrspace(3)* %src) {
define void @test_memmove_p1_p3_i16(i8 addrspace(1)* %dst, i8 addrspace(3)* %src) {

  ; CHECK-LABEL: name: test_memmove_p1_p3_i16
  ; CHECK-LABEL: name: test_memmove_p1_p3_i16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 256
  ; CHECK:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 256

  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s16)
  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s16)

  ; CHECK:   G_MEMMOVE [[MV]](p1), [[COPY2]](p3), [[ZEXT]](s32), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 3)
  ; CHECK:   G_MEMMOVE [[MV]](p1), [[COPY2]](p3), [[ZEXT]](s32), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 3)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call void @llvm.memmove.p1i8.p3i8.i16(i8 addrspace(1)* %dst, i8 addrspace(3)* %src, i16 256, i1 false)
  call void @llvm.memmove.p1i8.p3i8.i16(i8 addrspace(1)* %dst, i8 addrspace(3)* %src, i16 256, i1 false)

  ret void
  ret void

}
}




define void @test_memset_p1_i64(i8 addrspace(1)* %dst, i8 %val) {
define void @test_memset_p1_i64(i8 addrspace(1)* %dst, i8 %val) {

  ; CHECK-LABEL: name: test_memset_p1_i64
  ; CHECK-LABEL: name: test_memset_p1_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256
  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256

  ; CHECK:   G_MEMSET [[MV]](p1), [[TRUNC]](s8), [[C]](s64), 0 :: (store 1 into %ir.dst, addrspace 1)
  ; CHECK:   G_MEMSET [[MV]](p1), [[TRUNC]](s8), [[C]](s64), 0 :: (store 1 into %ir.dst, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call void @llvm.memset.p1i8.i64(i8 addrspace(1)* %dst, i8 %val, i64 256, i1 false)
  call void @llvm.memset.p1i8.i64(i8 addrspace(1)* %dst, i8 %val, i64 256, i1 false)

  ret void
  ret void

}
}




define void @test_memset_p1_i32(i8 addrspace(1)* %dst, i8 %val) {
define void @test_memset_p1_i32(i8 addrspace(1)* %dst, i8 %val) {

  ; CHECK-LABEL: name: test_memset_p1_i32
  ; CHECK-LABEL: name: test_memset_p1_i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256

  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)

  ; CHECK:   G_MEMSET [[MV]](p1), [[TRUNC]](s8), [[ZEXT]](s64), 0 :: (store 1 into %ir.dst, addrspace 1)
  ; CHECK:   G_MEMSET [[MV]](p1), [[TRUNC]](s8), [[ZEXT]](s64), 0 :: (store 1 into %ir.dst, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call void @llvm.memset.p1i8.i32(i8 addrspace(1)* %dst, i8 %val, i32 256, i1 false)
  call void @llvm.memset.p1i8.i32(i8 addrspace(1)* %dst, i8 %val, i32 256, i1 false)

  ret void
  ret void

}
}




define void @test_memset_p1_i16(i8 addrspace(1)* %dst, i8 %val) {
define void @test_memset_p1_i16(i8 addrspace(1)* %dst, i8 %val) {

  ; CHECK-LABEL: name: test_memset_p1_i16
  ; CHECK-LABEL: name: test_memset_p1_i16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 256
  ; CHECK:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 256

  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s16)
  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s16)

  ; CHECK:   G_MEMSET [[MV]](p1), [[TRUNC]](s8), [[ZEXT]](s64), 0 :: (store 1 into %ir.dst, addrspace 1)
  ; CHECK:   G_MEMSET [[MV]](p1), [[TRUNC]](s8), [[ZEXT]](s64), 0 :: (store 1 into %ir.dst, addrspace 1)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]]
  ; CHECK:   S_SETPC_B64_return [[COPY4]]

  call void @llvm.memset.p1i8.i16(i8 addrspace(1)* %dst, i8 %val, i16 256, i1 false)
  call void @llvm.memset.p1i8.i16(i8 addrspace(1)* %dst, i8 %val, i16 256, i1 false)

  ret void
  ret void

}
}

▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s




define i8* @ptrmask_flat_i64(i8* %ptr, i64 %mask) {
define i8* @ptrmask_flat_i64(i8* %ptr, i64 %mask) {

  ; CHECK-LABEL: name: ptrmask_flat_i64
  ; CHECK-LABEL: name: ptrmask_flat_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[MV]], [[MV1]](s64)
  ; CHECK:   [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[MV]], [[MV1]](s64)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRMASK]](p0)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRMASK]](p0)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %masked = call i8* @llvm.ptrmask.p0i8.i64(i8* %ptr, i64 %mask)
  %masked = call i8* @llvm.ptrmask.p0i8.i64(i8* %ptr, i64 %mask)

  ret i8* %masked
  ret i8* %masked

}
}




define i8* @ptrmask_flat_i32(i8* %ptr, i32 %mask) {
define i8* @ptrmask_flat_i32(i8* %ptr, i32 %mask) {

  ; CHECK-LABEL: name: ptrmask_flat_i32
  ; CHECK-LABEL: name: ptrmask_flat_i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[MV]], [[COPY2]](s32)
  ; CHECK:   [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[MV]], [[COPY2]](s32)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRMASK]](p0)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRMASK]](p0)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY4]], implicit $vgpr0, implicit $vgpr1

  %masked = call i8* @llvm.ptrmask.p0i8.i32(i8* %ptr, i32 %mask)
  %masked = call i8* @llvm.ptrmask.p0i8.i32(i8* %ptr, i32 %mask)

  ret i8* %masked
  ret i8* %masked

}
}




define i8* @ptrmask_flat_i16(i8* %ptr, i16 %mask) {
define i8* @ptrmask_flat_i16(i8* %ptr, i16 %mask) {

  ; CHECK-LABEL: name: ptrmask_flat_i16
  ; CHECK-LABEL: name: ptrmask_flat_i16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[MV]], [[TRUNC]](s16)
  ; CHECK:   [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[MV]], [[TRUNC]](s16)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRMASK]](p0)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRMASK]](p0)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY4]], implicit $vgpr0, implicit $vgpr1

  %masked = call i8* @llvm.ptrmask.p0i8.i16(i8* %ptr, i16 %mask)
  %masked = call i8* @llvm.ptrmask.p0i8.i16(i8* %ptr, i16 %mask)

  ret i8* %masked
  ret i8* %masked

}
}




define i8* @ptrmask_flat_i1(i8* %ptr, i1 %mask) {
define i8* @ptrmask_flat_i1(i8* %ptr, i1 %mask) {

  ; CHECK-LABEL: name: ptrmask_flat_i1
  ; CHECK-LABEL: name: ptrmask_flat_i1

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[MV]], [[TRUNC]](s1)
  ; CHECK:   [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[MV]], [[TRUNC]](s1)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRMASK]](p0)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRMASK]](p0)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY4]], implicit $vgpr0, implicit $vgpr1

  %masked = call i8* @llvm.ptrmask.p0i8.i1(i8* %ptr, i1 %mask)
  %masked = call i8* @llvm.ptrmask.p0i8.i1(i8* %ptr, i1 %mask)

  ret i8* %masked
  ret i8* %masked

}
}




define i8 addrspace(3)* @ptrmask_local_i64(i8 addrspace(3)* %ptr, i64 %mask) {
define i8 addrspace(3)* @ptrmask_local_i64(i8 addrspace(3)* %ptr, i64 %mask) {

  ; CHECK-LABEL: name: ptrmask_local_i64
  ; CHECK-LABEL: name: ptrmask_local_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[PTRMASK:%[0-9]+]]:_(p3) = G_PTRMASK [[COPY]], [[MV]](s64)
  ; CHECK:   [[PTRMASK:%[0-9]+]]:_(p3) = G_PTRMASK [[COPY]], [[MV]](s64)

  ; CHECK:   $vgpr0 = COPY [[PTRMASK]](p3)
  ; CHECK:   $vgpr0 = COPY [[PTRMASK]](p3)

  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]

  ; CHECK:   S_SETPC_B64_return [[COPY4]], implicit $vgpr0
  ; CHECK:   S_SETPC_B64_return [[COPY4]], implicit $vgpr0

  %masked = call i8 addrspace(3)* @llvm.ptrmask.p3i8.i64(i8 addrspace(3)* %ptr, i64 %mask)
  %masked = call i8 addrspace(3)* @llvm.ptrmask.p3i8.i64(i8 addrspace(3)* %ptr, i64 %mask)

  ret i8 addrspace(3)* %masked
  ret i8 addrspace(3)* %masked

}
}




▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
Show All 36 Lines
declare i32 @llvm.uadd.sat.i32(i32, i32)
declare i32 @llvm.uadd.sat.i32(i32, i32)




define i64 @uaddsat_i64(i64 %lhs, i64 %rhs) {
define i64 @uaddsat_i64(i64 %lhs, i64 %rhs) {

  ; CHECK-LABEL: name: uaddsat_i64
  ; CHECK-LABEL: name: uaddsat_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[UADDSAT:%[0-9]+]]:_(s64) = G_UADDSAT [[MV]], [[MV1]]
  ; CHECK:   [[UADDSAT:%[0-9]+]]:_(s64) = G_UADDSAT [[MV]], [[MV1]]

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](s64)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](s64)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %res = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
  %res = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)

  ret i64 %res
  ret i64 %res

}
}

declare i64 @llvm.uadd.sat.i64(i64, i64)
declare i64 @llvm.uadd.sat.i64(i64, i64)




define <2 x i32> @uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
define <2 x i32> @uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {

  ; CHECK-LABEL: name: uaddsat_v2i32
  ; CHECK-LABEL: name: uaddsat_v2i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[UADDSAT:%[0-9]+]]:_(<2 x s32>) = G_UADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
  ; CHECK:   [[UADDSAT:%[0-9]+]]:_(<2 x s32>) = G_UADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](<2 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](<2 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %res = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
  %res = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)

  ret <2 x i32> %res
  ret <2 x i32> %res

Show All 36 Lines
declare i32 @llvm.sadd.sat.i32(i32, i32)
declare i32 @llvm.sadd.sat.i32(i32, i32)




define i64 @saddsat_i64(i64 %lhs, i64 %rhs) {
define i64 @saddsat_i64(i64 %lhs, i64 %rhs) {

  ; CHECK-LABEL: name: saddsat_i64
  ; CHECK-LABEL: name: saddsat_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[SADDSAT:%[0-9]+]]:_(s64) = G_SADDSAT [[MV]], [[MV1]]
  ; CHECK:   [[SADDSAT:%[0-9]+]]:_(s64) = G_SADDSAT [[MV]], [[MV1]]

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](s64)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](s64)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %res = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
  %res = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)

  ret i64 %res
  ret i64 %res

}
}

declare i64 @llvm.sadd.sat.i64(i64, i64)
declare i64 @llvm.sadd.sat.i64(i64, i64)




define <2 x i32> @saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
define <2 x i32> @saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {

  ; CHECK-LABEL: name: saddsat_v2i32
  ; CHECK-LABEL: name: saddsat_v2i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[SADDSAT:%[0-9]+]]:_(<2 x s32>) = G_SADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
  ; CHECK:   [[SADDSAT:%[0-9]+]]:_(<2 x s32>) = G_SADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](<2 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](<2 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %res = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
  %res = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)

  ret <2 x i32> %res
  ret <2 x i32> %res

Show All 36 Lines
declare i32 @llvm.usub.sat.i32(i32, i32)
declare i32 @llvm.usub.sat.i32(i32, i32)




define i64 @usubsat_i64(i64 %lhs, i64 %rhs) {
define i64 @usubsat_i64(i64 %lhs, i64 %rhs) {

  ; CHECK-LABEL: name: usubsat_i64
  ; CHECK-LABEL: name: usubsat_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[USUBSAT:%[0-9]+]]:_(s64) = G_USUBSAT [[MV]], [[MV1]]
  ; CHECK:   [[USUBSAT:%[0-9]+]]:_(s64) = G_USUBSAT [[MV]], [[MV1]]

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USUBSAT]](s64)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USUBSAT]](s64)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %res = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
  %res = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)

  ret i64 %res
  ret i64 %res

}
}

declare i64 @llvm.usub.sat.i64(i64, i64)
declare i64 @llvm.usub.sat.i64(i64, i64)




define <2 x i32> @usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
define <2 x i32> @usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {

  ; CHECK-LABEL: name: usubsat_v2i32
  ; CHECK-LABEL: name: usubsat_v2i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[USUBSAT:%[0-9]+]]:_(<2 x s32>) = G_USUBSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
  ; CHECK:   [[USUBSAT:%[0-9]+]]:_(<2 x s32>) = G_USUBSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USUBSAT]](<2 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USUBSAT]](<2 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %res = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
  %res = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)

  ret <2 x i32> %res
  ret <2 x i32> %res

Show All 36 Lines
declare i32 @llvm.ssub.sat.i32(i32, i32)
declare i32 @llvm.ssub.sat.i32(i32, i32)




define i64 @ssubsat_i64(i64 %lhs, i64 %rhs) {
define i64 @ssubsat_i64(i64 %lhs, i64 %rhs) {

  ; CHECK-LABEL: name: ssubsat_i64
  ; CHECK-LABEL: name: ssubsat_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[SSUBSAT:%[0-9]+]]:_(s64) = G_SSUBSAT [[MV]], [[MV1]]
  ; CHECK:   [[SSUBSAT:%[0-9]+]]:_(s64) = G_SSUBSAT [[MV]], [[MV1]]

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSUBSAT]](s64)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSUBSAT]](s64)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %res = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
  %res = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)

  ret i64 %res
  ret i64 %res

}
}

declare i64 @llvm.ssub.sat.i64(i64, i64)
declare i64 @llvm.ssub.sat.i64(i64, i64)




define <2 x i32> @ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
define <2 x i32> @ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {

  ; CHECK-LABEL: name: ssubsat_v2i32
  ; CHECK-LABEL: name: ssubsat_v2i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[SSUBSAT:%[0-9]+]]:_(<2 x s32>) = G_SSUBSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
  ; CHECK:   [[SSUBSAT:%[0-9]+]]:_(<2 x s32>) = G_SSUBSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSUBSAT]](<2 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSUBSAT]](<2 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %res = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
  %res = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)

  ret <2 x i32> %res
  ret <2 x i32> %res

Show All 36 Lines
declare i32 @llvm.ushl.sat.i32(i32, i32)
declare i32 @llvm.ushl.sat.i32(i32, i32)




define i64 @ushlsat_i64(i64 %lhs, i64 %rhs) {
define i64 @ushlsat_i64(i64 %lhs, i64 %rhs) {

  ; CHECK-LABEL: name: ushlsat_i64
  ; CHECK-LABEL: name: ushlsat_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[USHLSAT:%[0-9]+]]:_(s64) = G_USHLSAT [[MV]], [[MV1]](s64)
  ; CHECK:   [[USHLSAT:%[0-9]+]]:_(s64) = G_USHLSAT [[MV]], [[MV1]](s64)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USHLSAT]](s64)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USHLSAT]](s64)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %res = call i64 @llvm.ushl.sat.i64(i64 %lhs, i64 %rhs)
  %res = call i64 @llvm.ushl.sat.i64(i64 %lhs, i64 %rhs)

  ret i64 %res
  ret i64 %res

}
}

declare i64 @llvm.ushl.sat.i64(i64, i64)
declare i64 @llvm.ushl.sat.i64(i64, i64)




define <2 x i32> @ushlsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
define <2 x i32> @ushlsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {

  ; CHECK-LABEL: name: ushlsat_v2i32
  ; CHECK-LABEL: name: ushlsat_v2i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[USHLSAT:%[0-9]+]]:_(<2 x s32>) = G_USHLSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]](<2 x s32>)
  ; CHECK:   [[USHLSAT:%[0-9]+]]:_(<2 x s32>) = G_USHLSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]](<2 x s32>)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USHLSAT]](<2 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USHLSAT]](<2 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %res = call <2 x i32> @llvm.ushl.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
  %res = call <2 x i32> @llvm.ushl.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)

  ret <2 x i32> %res
  ret <2 x i32> %res

Show All 36 Lines
declare i32 @llvm.sshl.sat.i32(i32, i32)
declare i32 @llvm.sshl.sat.i32(i32, i32)




define i64 @sshlsat_i64(i64 %lhs, i64 %rhs) {
define i64 @sshlsat_i64(i64 %lhs, i64 %rhs) {

  ; CHECK-LABEL: name: sshlsat_i64
  ; CHECK-LABEL: name: sshlsat_i64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[SSHLSAT:%[0-9]+]]:_(s64) = G_SSHLSAT [[MV]], [[MV1]](s64)
  ; CHECK:   [[SSHLSAT:%[0-9]+]]:_(s64) = G_SSHLSAT [[MV]], [[MV1]](s64)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](s64)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](s64)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %res = call i64 @llvm.sshl.sat.i64(i64 %lhs, i64 %rhs)
  %res = call i64 @llvm.sshl.sat.i64(i64 %lhs, i64 %rhs)

  ret i64 %res
  ret i64 %res

}
}

declare i64 @llvm.sshl.sat.i64(i64, i64)
declare i64 @llvm.sshl.sat.i64(i64, i64)




define <2 x i32> @sshlsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
define <2 x i32> @sshlsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {

  ; CHECK-LABEL: name: sshlsat_v2i32
  ; CHECK-LABEL: name: sshlsat_v2i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31

  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)

  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31

  ; CHECK:   [[SSHLSAT:%[0-9]+]]:_(<2 x s32>) = G_SSHLSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]](<2 x s32>)
  ; CHECK:   [[SSHLSAT:%[0-9]+]]:_(<2 x s32>) = G_SSHLSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]](<2 x s32>)

  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](<2 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](<2 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]

  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1

  %res = call <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
  %res = call <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)

  ret <2 x i32> %res
  ret <2 x i32> %res

}
}

declare <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32>, <2 x i32>)
declare <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32>, <2 x i32>)

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s




define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9-LABEL: name: atomic_swap_1d
  ; GFX9-LABEL: name: atomic_swap_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.swap.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.swap.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_swap_1d
  ; GFX10NSA-LABEL: name: atomic_swap_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.swap.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.swap.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_add_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
define amdgpu_ps float @atomic_add_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9-LABEL: name: atomic_add_1d
  ; GFX9-LABEL: name: atomic_add_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_add_1d
  ; GFX10NSA-LABEL: name: atomic_add_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_sub_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
define amdgpu_ps float @atomic_sub_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9-LABEL: name: atomic_sub_1d
  ; GFX9-LABEL: name: atomic_sub_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.sub.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.sub.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_sub_1d
  ; GFX10NSA-LABEL: name: atomic_sub_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.sub.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.sub.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_smin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
define amdgpu_ps float @atomic_smin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9-LABEL: name: atomic_smin_1d
  ; GFX9-LABEL: name: atomic_smin_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smin.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smin.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_smin_1d
  ; GFX10NSA-LABEL: name: atomic_smin_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smin.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smin.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}







define amdgpu_ps float @atomic_umin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
define amdgpu_ps float @atomic_umin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9-LABEL: name: atomic_umin_1d
  ; GFX9-LABEL: name: atomic_umin_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umin.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umin.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_umin_1d
  ; GFX10NSA-LABEL: name: atomic_umin_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umin.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umin.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_smax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
define amdgpu_ps float @atomic_smax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9-LABEL: name: atomic_smax_1d
  ; GFX9-LABEL: name: atomic_smax_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smax.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smax.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_smax_1d
  ; GFX10NSA-LABEL: name: atomic_smax_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smax.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smax.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.smax.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.smax.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_umax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
define amdgpu_ps float @atomic_umax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9-LABEL: name: atomic_umax_1d
  ; GFX9-LABEL: name: atomic_umax_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umax.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umax.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_umax_1d
  ; GFX10NSA-LABEL: name: atomic_umax_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umax.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umax.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.umax.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.umax.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_and_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
define amdgpu_ps float @atomic_and_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9-LABEL: name: atomic_and_1d
  ; GFX9-LABEL: name: atomic_and_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.and.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.and.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_and_1d
  ; GFX10NSA-LABEL: name: atomic_and_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.and.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.and.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.and.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.and.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_or_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
define amdgpu_ps float @atomic_or_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9-LABEL: name: atomic_or_1d
  ; GFX9-LABEL: name: atomic_or_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.or.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.or.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_or_1d
  ; GFX10NSA-LABEL: name: atomic_or_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.or.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.or.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.or.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.or.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_xor_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
define amdgpu_ps float @atomic_xor_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9-LABEL: name: atomic_xor_1d
  ; GFX9-LABEL: name: atomic_xor_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.xor.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.xor.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_xor_1d
  ; GFX10NSA-LABEL: name: atomic_xor_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.xor.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.xor.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.xor.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.xor.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_inc_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
define amdgpu_ps float @atomic_inc_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9-LABEL: name: atomic_inc_1d
  ; GFX9-LABEL: name: atomic_inc_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.inc.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.inc.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_inc_1d
  ; GFX10NSA-LABEL: name: atomic_inc_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.inc.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.inc.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.inc.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.inc.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_dec_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
define amdgpu_ps float @atomic_dec_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9-LABEL: name: atomic_dec_1d
  ; GFX9-LABEL: name: atomic_dec_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.dec.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.dec.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_dec_1d
  ; GFX10NSA-LABEL: name: atomic_dec_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.dec.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.dec.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.dec.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.dec.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i16 %s) {
define amdgpu_ps float @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i16 %s) {

  ; GFX9-LABEL: name: atomic_cmpswap_1d
  ; GFX9-LABEL: name: atomic_cmpswap_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.1d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.1d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_cmpswap_1d
  ; GFX10NSA-LABEL: name: atomic_cmpswap_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.1d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.1d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i16(i32 %cmp, i32 %swap, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i16(i32 %cmp, i32 %swap, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t) {
define amdgpu_ps float @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t) {

  ; GFX9-LABEL: name: atomic_add_2d
  ; GFX9-LABEL: name: atomic_add_2d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2d), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2d), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_add_2d
  ; GFX10NSA-LABEL: name: atomic_add_2d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2d), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2d), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i16(i32 %data, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i16(i32 %data, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t, i16 %r) {
define amdgpu_ps float @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t, i16 %r) {

  ; GFX9-LABEL: name: atomic_add_3d
  ; GFX9-LABEL: name: atomic_add_3d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.3d), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.3d), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_add_3d
  ; GFX10NSA-LABEL: name: atomic_add_3d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)

  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.3d), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.3d), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

Show All 12 Linesdefine amdgpu_ps float @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t, i16 %face) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.cube), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.cube), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_add_cube
  ; GFX10NSA-LABEL: name: atomic_add_cube

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)

  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.cube), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.cube), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

Show All 12 Linesdefine amdgpu_ps float @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %slice) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1darray), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1darray), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_add_1darray
  ; GFX10NSA-LABEL: name: atomic_add_1darray

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1darray), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1darray), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i16(i32 %data, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i16(i32 %data, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t, i16 %slice) {
define amdgpu_ps float @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t, i16 %slice) {

  ; GFX9-LABEL: name: atomic_add_2darray
  ; GFX9-LABEL: name: atomic_add_2darray

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darray), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darray), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_add_2darray
  ; GFX10NSA-LABEL: name: atomic_add_2darray

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)

  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darray), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darray), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

Show All 12 Linesdefine amdgpu_ps float @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t, i16 %fragid) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2dmsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2dmsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_add_2dmsaa
  ; GFX10NSA-LABEL: name: atomic_add_2dmsaa

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)

  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2dmsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2dmsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

Show All 12 Linesdefine amdgpu_ps float @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t, i16 %slice, i16 %fragid) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darraymsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darraymsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_add_2darraymsaa
  ; GFX10NSA-LABEL: name: atomic_add_2darraymsaa

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)

  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)

  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darraymsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darraymsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

Show All 12 Linesdefine amdgpu_ps float @atomic_add_1d_slc(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_add_1d_slc
  ; GFX10NSA-LABEL: name: atomic_add_1d_slc

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

  %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
  %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)

  %out = bitcast i32 %v to float
  %out = bitcast i32 %v to float

  ret float %out
  ret float %out

}
}




define amdgpu_ps float @atomic_cmpswap_2d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i16 %s, i16 %t) {
define amdgpu_ps float @atomic_cmpswap_2d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i16 %s, i16 %t) {

  ; GFX9-LABEL: name: atomic_cmpswap_2d
  ; GFX9-LABEL: name: atomic_cmpswap_2d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_cmpswap_2d
  ; GFX10NSA-LABEL: name: atomic_cmpswap_2d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

Show All 9 Linesdefine amdgpu_ps float @atomic_cmpswap_3d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i16 %s, i16 %t, i16 %r) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.3d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.3d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_cmpswap_3d
  ; GFX10NSA-LABEL: name: atomic_cmpswap_3d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)

  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)

  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

Show All 13 Linesdefine amdgpu_ps float @atomic_cmpswap_2darraymsaa(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i16 %s, i16 %t, i16 %slice, i16 %fragid) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2darraymsaa), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2darraymsaa), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store 4 on custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: atomic_cmpswap_2darraymsaa
  ; GFX10NSA-LABEL: name: atomic_cmpswap_2darraymsaa

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)

  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)

  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10NSA:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

Show All 38 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s




define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9-LABEL: name: load_1d
  ; GFX9-LABEL: name: load_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: load_1d
  ; GFX10NSA-LABEL: name: load_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

Show All 19 Linesdefine amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 17 Linesdefine amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 26 Linesdefine amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 17 Linesdefine amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 26 Linesdefine amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

Show All 19 Linesdefine amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 17 Linesdefine amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 26 Linesdefine amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 17 Linesdefine amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 26 Linesdefine amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 19 Linesdefine amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 29 Linesdefine amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

Show All 19 Linesdefine amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 17 Linesdefine amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 26 Linesdefine amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 19 Linesdefine amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 29 Linesdefine amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 19 Linesdefine amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 29 Linesdefine amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 17 Linesdefine amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 26 Linesdefine amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 19 Linesdefine amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 29 Linesdefine amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10NSA-LABEL: name: store_1d
  ; GFX10NSA-LABEL: name: store_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX10NSA:   S_ENDPGM 0
  ; GFX10NSA:   S_ENDPGM 0

main_body:
main_body:

  %s = extractelement <2 x i16> %coords, i32 0
  %s = extractelement <2 x i16> %coords, i32 0

  call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {

  ; GFX9-LABEL: name: store_2d
  ; GFX9-LABEL: name: store_2d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10NSA-LABEL: name: store_2d
  ; GFX10NSA-LABEL: name: store_2d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

Show All 14 Linesdefine amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 12 Linesdefine amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 21 Linesdefine amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 12 Linesdefine amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 21 Linesdefine amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10NSA-LABEL: name: store_1darray
  ; GFX10NSA-LABEL: name: store_1darray

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

Show All 14 Linesdefine amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 12 Linesdefine amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 21 Linesdefine amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 12 Linesdefine amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 21 Linesdefine amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 14 Linesdefine amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 24 Linesdefine amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10NSA-LABEL: name: store_mip_1d
  ; GFX10NSA-LABEL: name: store_mip_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

Show All 14 Linesdefine amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 12 Linesdefine amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 21 Linesdefine amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 14 Linesdefine amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 24 Linesdefine amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 14 Linesdefine amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 24 Linesdefine amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 12 Linesdefine amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 21 Linesdefine amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX9:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 14 Linesdefine amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)

  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
  ; GFX10NSA:   [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)

Show All 24 Linesdefine amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: getresinfo_1d
  ; GFX10NSA-LABEL: name: getresinfo_1d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: getresinfo_2d
  ; GFX10NSA-LABEL: name: getresinfo_2d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.3d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.3d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: getresinfo_3d
  ; GFX10NSA-LABEL: name: getresinfo_3d

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.3d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.3d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.cube), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.cube), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: getresinfo_cube
  ; GFX10NSA-LABEL: name: getresinfo_cube

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.cube), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.cube), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1darray), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1darray), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: getresinfo_1darray
  ; GFX10NSA-LABEL: name: getresinfo_1darray

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1darray), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1darray), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darray), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darray), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: getresinfo_2darray
  ; GFX10NSA-LABEL: name: getresinfo_2darray

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darray), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darray), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2dmsaa), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2dmsaa), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: getresinfo_2dmsaa
  ; GFX10NSA-LABEL: name: getresinfo_2dmsaa

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2dmsaa), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2dmsaa), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darraymsaa), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darraymsaa), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: getresinfo_2darraymsaa
  ; GFX10NSA-LABEL: name: getresinfo_2darraymsaa

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darraymsaa), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darraymsaa), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 8, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 4 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 8, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 4 from custom "ImageResource")

  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: load_1d_V1
  ; GFX10NSA-LABEL: name: load_1d_V1

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 8, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 4 from custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 8, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 4 from custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

main_body:
main_body:

Show All 9 Linesdefine amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 9, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 8 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 9, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 8 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  ; GFX10NSA-LABEL: name: load_1d_V2
  ; GFX10NSA-LABEL: name: load_1d_V2

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 9, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 8 from custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 9, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load 8 from custom "ImageResource")

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 11 Linesdefine amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[COPY8]](s32), 2, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 4 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[COPY8]](s32), 2, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 4 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10NSA-LABEL: name: store_1d_V1
  ; GFX10NSA-LABEL: name: store_1d_V1

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[COPY8]](s32), 2, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 4 into custom "ImageResource")
  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[COPY8]](s32), 2, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 4 into custom "ImageResource")

  ; GFX10NSA:   S_ENDPGM 0
  ; GFX10NSA:   S_ENDPGM 0

main_body:
main_body:

  %s = extractelement <2 x i16> %coords, i32 0
  %s = extractelement <2 x i16> %coords, i32 0

  call void @llvm.amdgcn.image.store.1d.f32.i16(float %vdata, i32 2, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  call void @llvm.amdgcn.image.store.1d.f32.i16(float %vdata, i32 2, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, <2 x i16> %coords) {
define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, <2 x i16> %coords) {

  ; GFX9-LABEL: name: store_1d_V2
  ; GFX9-LABEL: name: store_1d_V2

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX9:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<2 x s32>), 12, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 8 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<2 x s32>), 12, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 8 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10NSA-LABEL: name: store_1d_V2
  ; GFX10NSA-LABEL: name: store_1d_V2

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<2 x s32>), 12, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 8 into custom "ImageResource")
  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<2 x s32>), 12, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store 8 into custom "ImageResource")

  ; GFX10NSA:   S_ENDPGM 0
  ; GFX10NSA:   S_ENDPGM 0

main_body:
main_body:

  %s = extractelement <2 x i16> %coords, i32 0
  %s = extractelement <2 x i16> %coords, i32 0

  call void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float> %vdata, i32 12, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
  call void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float> %vdata, i32 12, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9-LABEL: name: load_1d_glc
  ; GFX9-LABEL: name: load_1d_glc

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 1, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 1, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: load_1d_glc
  ; GFX10NSA-LABEL: name: load_1d_glc

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 1, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 1, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: load_1d_slc
  ; GFX10NSA-LABEL: name: load_1d_slc

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 3, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 3, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: load_1d_glc_slc
  ; GFX10NSA-LABEL: name: load_1d_glc_slc

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 3, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 3, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 1, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 1, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10NSA-LABEL: name: store_1d_glc
  ; GFX10NSA-LABEL: name: store_1d_glc

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 1, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 1, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX10NSA:   S_ENDPGM 0
  ; GFX10NSA:   S_ENDPGM 0

main_body:
main_body:

  %s = extractelement <2 x i16> %coords, i32 0
  %s = extractelement <2 x i16> %coords, i32 0

  call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
  call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)

  ret void
  ret void

}
}




define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {

  ; GFX9-LABEL: name: store_1d_slc
  ; GFX9-LABEL: name: store_1d_slc

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10NSA-LABEL: name: store_1d_slc
  ; GFX10NSA-LABEL: name: store_1d_slc

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX10NSA:   S_ENDPGM 0
  ; GFX10NSA:   S_ENDPGM 0

main_body:
main_body:

  %s = extractelement <2 x i16> %coords, i32 0
  %s = extractelement <2 x i16> %coords, i32 0

  call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
  call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)

  ret void
  ret void

}
}




define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {

  ; GFX9-LABEL: name: store_1d_glc_slc
  ; GFX9-LABEL: name: store_1d_glc_slc

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 3, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 3, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10NSA-LABEL: name: store_1d_glc_slc
  ; GFX10NSA-LABEL: name: store_1d_glc_slc

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 3, 3 :: (dereferenceable store 16 into custom "ImageResource")
  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 3, 3 :: (dereferenceable store 16 into custom "ImageResource")

  ; GFX10NSA:   S_ENDPGM 0
  ; GFX10NSA:   S_ENDPGM 0

main_body:
main_body:

  %s = extractelement <2 x i16> %coords, i32 0
  %s = extractelement <2 x i16> %coords, i32 0

▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesdefine amdgpu_ps <4 x float> @load_1d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 1, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 1, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)

  ; GFX9:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GFX9:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: load_1d_tfe
  ; GFX10NSA-LABEL: name: load_1d_tfe

  ; GFX10NSA: bb.1.main_body:
  ; GFX10NSA: bb.1.main_body:

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 1, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 1, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)

  ; GFX10NSA:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GFX10NSA:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

Show All 18 Linesdefine amdgpu_ps <4 x float> @load_2d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @load_2d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coords) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

Show All 24 Linesdefine amdgpu_ps <4 x float> @load_3d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

Show All 19 Linesdefine amdgpu_ps <4 x float> @load_3d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

Show All 31 Linesdefine amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

Show All 21 Linesdefine amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)

  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10NSA:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)

  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)

▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=UNPACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=UNPACKED %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=PACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=PACKED %s




define amdgpu_ps half @image_load_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
define amdgpu_ps half @image_load_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED-LABEL: name: image_load_f16
  ; UNPACKED-LABEL: name: image_load_f16

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s16) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s16) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; UNPACKED:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AMDGPU_INTRIN_IMAGE_LOAD]](s16)
  ; UNPACKED:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AMDGPU_INTRIN_IMAGE_LOAD]](s16)

  ; UNPACKED:   $vgpr0 = COPY [[ANYEXT]](s32)
  ; UNPACKED:   $vgpr0 = COPY [[ANYEXT]](s32)

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: image_load_f16
  ; PACKED-LABEL: name: image_load_f16

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s16) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s16) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; PACKED:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AMDGPU_INTRIN_IMAGE_LOAD]](s16)
  ; PACKED:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AMDGPU_INTRIN_IMAGE_LOAD]](s16)

  ; PACKED:   $vgpr0 = COPY [[ANYEXT]](s32)
  ; PACKED:   $vgpr0 = COPY [[ANYEXT]](s32)

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %tex = call half @llvm.amdgcn.image.load.2d.f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call half @llvm.amdgcn.image.load.2d.f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret half %tex
  ret half %tex

}
}




define amdgpu_ps <2 x half> @image_load_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
define amdgpu_ps <2 x half> @image_load_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED-LABEL: name: image_load_v2f16
  ; UNPACKED-LABEL: name: image_load_v2f16

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)

  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]

Show All 9 Linesdefine amdgpu_ps <2 x half> @image_load_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; PACKED:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %tex = call <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret <2 x half> %tex
  ret <2 x half> %tex

}
}




define amdgpu_ps <3 x half> @image_load_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
define amdgpu_ps <3 x half> @image_load_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED-LABEL: name: image_load_v3f16
  ; UNPACKED-LABEL: name: image_load_v3f16

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF

  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF2]](<4 x s16>)
  ; UNPACKED:   [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF2]](<4 x s16>)

Show All 24 Linesdefine amdgpu_ps <3 x half> @image_load_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)

  ; PACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s16>)
  ; PACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s16>)

  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)

  ; PACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; PACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

Show All 32 Linesdefine amdgpu_ps <4 x half> @image_load_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)

  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]

Show All 17 Linesdefine amdgpu_ps <4 x half> @image_load_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s16>)
  ; PACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s16>)

  ; PACKED:   $vgpr0 = COPY [[UV]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[UV]](<2 x s16>)

  ; PACKED:   $vgpr1 = COPY [[UV1]](<2 x s16>)
  ; PACKED:   $vgpr1 = COPY [[UV1]](<2 x s16>)

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret <4 x half> %tex
  ret <4 x half> %tex

}
}




define amdgpu_ps half @image_load_tfe_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
define amdgpu_ps half @image_load_tfe_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED-LABEL: name: image_load_tfe_f16
  ; UNPACKED-LABEL: name: image_load_tfe_f16

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   $vgpr0 = COPY [[COPY10]](s32)
  ; UNPACKED:   $vgpr0 = COPY [[COPY10]](s32)

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: image_load_tfe_f16
  ; PACKED-LABEL: name: image_load_tfe_f16

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; PACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; PACKED:   $vgpr0 = COPY [[COPY10]](s32)
  ; PACKED:   $vgpr0 = COPY [[COPY10]](s32)

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

Show All 11 Linesdefine amdgpu_ps <2 x half> @image_load_tfe_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)

Show All 11 Linesdefine amdgpu_ps <2 x half> @image_load_tfe_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)

  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

Show All 11 Linesdefine amdgpu_ps <3 x half> @image_load_tfe_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF

  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; UNPACKED:   G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; UNPACKED:   [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

Show All 26 Linesdefine amdgpu_ps <3 x half> @image_load_tfe_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)

  ; PACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)
  ; PACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)

  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

Show All 39 Linesdefine amdgpu_ps <4 x half> @image_load_tfe_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)

  ; UNPACKED:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; UNPACKED:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

Show All 19 Linesdefine amdgpu_ps <4 x half> @image_load_tfe_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)

  ; PACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)
  ; PACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)

  ; PACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)

▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesdefine amdgpu_ps <2 x half> @image_load_v2f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)

  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]

  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)

  ; UNPACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
  ; UNPACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: image_load_v2f16_dmask_1000
  ; PACKED-LABEL: name: image_load_v2f16_dmask_1000

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; PACKED:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %tex = call <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret <2 x half> %tex
  ret <2 x half> %tex

}
}




▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesdefine amdgpu_ps <3 x half> @image_load_v3f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF1]](<4 x s16>)
  ; UNPACKED:   [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF1]](<4 x s16>)

  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)

Show All 22 Linesdefine amdgpu_ps <3 x half> @image_load_v3f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)

  ; PACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; PACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; PACKED:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; PACKED:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

Show All 31 Linesdefine amdgpu_ps <3 x half> @image_load_v3f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF1]](<4 x s16>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF1]](<4 x s16>)

  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

Show All 19 Linesdefine amdgpu_ps <3 x half> @image_load_v3f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)

  ; PACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; PACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; PACKED:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; PACKED:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Linesdefine amdgpu_ps <4 x half> @image_load_v4f16_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)

  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]

Show All 16 Linesdefine amdgpu_ps <4 x half> @image_load_v4f16_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)

  ; PACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s16>)
  ; PACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s16>)

  ; PACKED:   $vgpr0 = COPY [[UV]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[UV]](<2 x s16>)

  ; PACKED:   $vgpr1 = COPY [[UV1]](<2 x s16>)
  ; PACKED:   $vgpr1 = COPY [[UV1]](<2 x s16>)

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret <4 x half> %tex
  ret <4 x half> %tex

}
}




define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED-LABEL: name: image_load_v4f16_dmask_1100
  ; UNPACKED-LABEL: name: image_load_v4f16_dmask_1100

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)

  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]

Show All 14 Linesdefine amdgpu_ps <4 x half> @image_load_v4f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)

  ; PACKED:   $vgpr1 = COPY [[DEF]](<2 x s16>)
  ; PACKED:   $vgpr1 = COPY [[DEF]](<2 x s16>)

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret <4 x half> %tex
  ret <4 x half> %tex

}
}




define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED-LABEL: name: image_load_v4f16_dmask_1000
  ; UNPACKED-LABEL: name: image_load_v4f16_dmask_1000

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)

Show All 10 Linesdefine amdgpu_ps <4 x half> @image_load_v4f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)

  ; PACKED:   $vgpr1 = COPY [[DEF]](<2 x s16>)
  ; PACKED:   $vgpr1 = COPY [[DEF]](<2 x s16>)

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret <4 x half> %tex
  ret <4 x half> %tex

▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Linesdefine amdgpu_ps half @image_load_tfe_f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   $vgpr0 = COPY [[COPY10]](s32)
  ; UNPACKED:   $vgpr0 = COPY [[COPY10]](s32)

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: image_load_tfe_f16_dmask_0000
  ; PACKED-LABEL: name: image_load_tfe_f16_dmask_0000

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; PACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; PACKED:   $vgpr0 = COPY [[COPY10]](s32)
  ; PACKED:   $vgpr0 = COPY [[COPY10]](s32)

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

Show All 11 Linesdefine amdgpu_ps <2 x half> @image_load_tfe_v2f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

Show All 10 Linesdefine amdgpu_ps <2 x half> @image_load_tfe_v2f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)

  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

Show All 11 Linesdefine amdgpu_ps <2 x half> @image_load_tfe_v2f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

Show All 10 Linesdefine amdgpu_ps <2 x half> @image_load_tfe_v2f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)

  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

Show All 11 Linesdefine amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; UNPACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

Show All 24 Linesdefine amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)

  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

Show All 38 Linesdefine amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

Show All 22 Linesdefine amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)

  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

Show All 38 Linesdefine amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

Show All 22 Linesdefine amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)

  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

Show All 38 Linesdefine amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; UNPACKED:   G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; UNPACKED:   G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

Show All 18 Linesdefine amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 6 from custom "ImageResource", align 8)

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)

  ; PACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)
  ; PACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)

  ; PACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)

Show All 13 Linesdefine amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; UNPACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; UNPACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

Show All 16 Linesdefine amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)

  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)

Show All 13 Linesdefine amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

Show All 13 Linesdefine amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)

  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)

Show All 13 Linesdefine amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]

Show All 13 Linesdefine amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")
  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 2 from custom "ImageResource")

  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)

  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)

Show All 19 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GCN %s




define amdgpu_ps float @image_load_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
define amdgpu_ps float @image_load_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN-LABEL: name: image_load_f32
  ; GCN-LABEL: name: image_load_f32

  ; GCN: bb.1 (%ir-block.0):
  ; GCN: bb.1 (%ir-block.0):

  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GCN:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GCN:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %tex = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret float %tex
  ret float %tex

}
}




define amdgpu_ps <2 x float> @image_load_v2f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
define amdgpu_ps <2 x float> @image_load_v2f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN-LABEL: name: image_load_v2f32
  ; GCN-LABEL: name: image_load_v2f32

  ; GCN: bb.1 (%ir-block.0):
  ; GCN: bb.1 (%ir-block.0):

  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
  ; GCN:   $vgpr1 = COPY [[UV1]](s32)

  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %tex = call <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret <2 x float> %tex
  ret <2 x float> %tex

}
}




define amdgpu_ps <3 x float> @image_load_v3f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
define amdgpu_ps <3 x float> @image_load_v3f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN-LABEL: name: image_load_v3f32
  ; GCN-LABEL: name: image_load_v3f32

  ; GCN: bb.1 (%ir-block.0):
  ; GCN: bb.1 (%ir-block.0):

  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 12 from custom "ImageResource", align 16)
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 12 from custom "ImageResource", align 16)

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
  ; GCN:   $vgpr1 = COPY [[UV1]](s32)

  ; GCN:   $vgpr2 = COPY [[UV2]](s32)
  ; GCN:   $vgpr2 = COPY [[UV2]](s32)

  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2

  %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret <3 x float> %tex
  ret <3 x float> %tex

}
}




define amdgpu_ps <4 x float> @image_load_v4f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
define amdgpu_ps <4 x float> @image_load_v4f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN-LABEL: name: image_load_v4f32
  ; GCN-LABEL: name: image_load_v4f32

  ; GCN: bb.1 (%ir-block.0):
  ; GCN: bb.1 (%ir-block.0):

  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
  ; GCN:   $vgpr1 = COPY [[UV1]](s32)

  ; GCN:   $vgpr2 = COPY [[UV2]](s32)
  ; GCN:   $vgpr2 = COPY [[UV2]](s32)

  ; GCN:   $vgpr3 = COPY [[UV3]](s32)
  ; GCN:   $vgpr3 = COPY [[UV3]](s32)

  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  %tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret <4 x float> %tex
  ret <4 x float> %tex

}
}




define amdgpu_ps float @image_load_tfe_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
define amdgpu_ps float @image_load_tfe_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN-LABEL: name: image_load_tfe_f32
  ; GCN-LABEL: name: image_load_tfe_f32

  ; GCN: bb.1 (%ir-block.0):
  ; GCN: bb.1 (%ir-block.0):

  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %res = call { float, i32 } @llvm.amdgcn.image.load.2d.sl_f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
  %res = call { float, i32 } @llvm.amdgcn.image.load.2d.sl_f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)

Show All 10 Linesdefine amdgpu_ps <2 x float> @image_load_tfe_v2f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; GCN:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
  ; GCN:   $vgpr1 = COPY [[UV1]](s32)

  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

Show All 11 Linesdefine amdgpu_ps <3 x float> @image_load_tfe_v3f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 12 from custom "ImageResource", align 16)
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 12 from custom "ImageResource", align 16)

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GCN:   G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
  ; GCN:   $vgpr1 = COPY [[UV1]](s32)

  ; GCN:   $vgpr2 = COPY [[UV2]](s32)
  ; GCN:   $vgpr2 = COPY [[UV2]](s32)

Show All 12 Linesdefine amdgpu_ps <4 x float> @image_load_tfe_v4f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)

  ; GCN:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
  ; GCN:   $vgpr1 = COPY [[UV1]](s32)

  ; GCN:   $vgpr2 = COPY [[UV2]](s32)
  ; GCN:   $vgpr2 = COPY [[UV2]](s32)

Show All 34 Linesdefine amdgpu_ps <2 x float> @image_load_v2f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GCN:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GCN:   $vgpr1 = COPY [[DEF]](s32)
  ; GCN:   $vgpr1 = COPY [[DEF]](s32)

  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %tex = call <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret <2 x float> %tex
  ret <2 x float> %tex

Show All 29 Linesdefine amdgpu_ps <3 x float> @image_load_v3f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
  ; GCN:   $vgpr1 = COPY [[UV1]](s32)

  ; GCN:   $vgpr2 = COPY [[DEF]](s32)
  ; GCN:   $vgpr2 = COPY [[DEF]](s32)

  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2

  %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret <3 x float> %tex
  ret <3 x float> %tex

}
}




define amdgpu_ps <3 x float> @image_load_v3f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
define amdgpu_ps <3 x float> @image_load_v3f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN-LABEL: name: image_load_v3f32_dmask_1000
  ; GCN-LABEL: name: image_load_v3f32_dmask_1000

  ; GCN: bb.1 (%ir-block.0):
  ; GCN: bb.1 (%ir-block.0):

  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GCN:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GCN:   $vgpr1 = COPY [[DEF]](s32)
  ; GCN:   $vgpr1 = COPY [[DEF]](s32)

  ; GCN:   $vgpr2 = COPY [[DEF]](s32)
  ; GCN:   $vgpr2 = COPY [[DEF]](s32)

  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2

  %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

Show All 31 Linesdefine amdgpu_ps <4 x float> @image_load_v4f32_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 12 from custom "ImageResource", align 16)
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 12 from custom "ImageResource", align 16)

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
  ; GCN:   $vgpr1 = COPY [[UV1]](s32)

  ; GCN:   $vgpr2 = COPY [[UV2]](s32)
  ; GCN:   $vgpr2 = COPY [[UV2]](s32)

  ; GCN:   $vgpr3 = COPY [[DEF]](s32)
  ; GCN:   $vgpr3 = COPY [[DEF]](s32)

Show All 9 Linesdefine amdgpu_ps <4 x float> @image_load_v4f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
  ; GCN:   $vgpr1 = COPY [[UV1]](s32)

  ; GCN:   $vgpr2 = COPY [[DEF]](s32)
  ; GCN:   $vgpr2 = COPY [[DEF]](s32)

  ; GCN:   $vgpr3 = COPY [[DEF]](s32)
  ; GCN:   $vgpr3 = COPY [[DEF]](s32)

Show All 9 Linesdefine amdgpu_ps <4 x float> @image_load_v4f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GCN:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GCN:   $vgpr1 = COPY [[DEF]](s32)
  ; GCN:   $vgpr1 = COPY [[DEF]](s32)

  ; GCN:   $vgpr2 = COPY [[DEF]](s32)
  ; GCN:   $vgpr2 = COPY [[DEF]](s32)

  ; GCN:   $vgpr3 = COPY [[DEF]](s32)
  ; GCN:   $vgpr3 = COPY [[DEF]](s32)

  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

Show All 33 Linesdefine amdgpu_ps float @image_load_tfe_f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %res = call { float, i32 } @llvm.amdgcn.image.load.2d.sl_f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
  %res = call { float, i32 } @llvm.amdgcn.image.load.2d.sl_f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)

Show All 10 Linesdefine amdgpu_ps <2 x float> @image_load_tfe_v2f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)
  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)

Show All 12 Linesdefine amdgpu_ps <2 x float> @image_load_tfe_v2f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)
  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)

Show All 12 Linesdefine amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
  ; GCN:   $vgpr1 = COPY [[UV1]](s32)

Show All 13 Linesdefine amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)
  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)

Show All 13 Linesdefine amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)
  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 12 from custom "ImageResource", align 16)
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 12 from custom "ImageResource", align 16)

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
  ; GCN:   $vgpr1 = COPY [[UV1]](s32)

Show All 14 Linesdefine amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 8 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)

  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
  ; GCN:   $vgpr1 = COPY [[UV1]](s32)

Show All 14 Linesdefine amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)
  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)

Show All 14 Linesdefine amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {

  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GCN:   $vgpr0 = COPY [[UV]](s32)
  ; GCN:   $vgpr0 = COPY [[UV]](s32)

  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)
  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)

Show All 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s




define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %fragid) {

  ; GFX6-LABEL: name: load_2darraymsaa
  ; GFX6-LABEL: name: load_2darraymsaa

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR1]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR1]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
  ; GFX6:   $vgpr0 = COPY [[UV]](s32)

  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: load_2darraymsaa
  ; GFX10NSA-LABEL: name: load_2darraymsaa

  ; GFX10NSA: bb.1 (%ir-block.0):
  ; GFX10NSA: bb.1 (%ir-block.0):

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)

  ret <4 x float> %v
  ret <4 x float> %v

}
}




define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %t, i32 %slice, i32 %fragid) {

  ; GFX6-LABEL: name: load_2darraymsaa_tfe
  ; GFX6-LABEL: name: load_2darraymsaa_tfe

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX6:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)

  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX6:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)

  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32)
  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32)

  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR1]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR1]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)

  ; GFX6:   G_STORE [[UV4]](s32), [[MV]](p1) :: (store 4 into %ir.out, addrspace 1)
  ; GFX6:   G_STORE [[UV4]](s32), [[MV]](p1) :: (store 4 into %ir.out, addrspace 1)

  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
  ; GFX6:   $vgpr0 = COPY [[UV]](s32)

  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10NSA-LABEL: name: load_2darraymsaa_tfe
  ; GFX10NSA-LABEL: name: load_2darraymsaa_tfe

  ; GFX10NSA: bb.1 (%ir-block.0):
  ; GFX10NSA: bb.1 (%ir-block.0):

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10NSA:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)

  ; GFX10NSA:   G_STORE [[UV4]](s32), [[MV]](p1) :: (store 4 into %ir.out, addrspace 1)
  ; GFX10NSA:   G_STORE [[UV4]](s32), [[MV]](p1) :: (store 4 into %ir.out, addrspace 1)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

Show All 11 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s




define amdgpu_ps float @image_load_3d_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) {
define amdgpu_ps float @image_load_3d_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) {

  ; GFX6-LABEL: name: image_load_3d_f32
  ; GFX6-LABEL: name: image_load_3d_f32

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32)
  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32)

  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[BUILD_VECTOR1]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[BUILD_VECTOR1]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GFX6:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX6:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: image_load_3d_f32
  ; GFX10NSA-LABEL: name: image_load_3d_f32

  ; GFX10NSA: bb.1 (%ir-block.0):
  ; GFX10NSA: bb.1 (%ir-block.0):

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %tex = call float @llvm.amdgcn.image.load.3d.f32.i32(i32 1, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)
  %tex = call float @llvm.amdgcn.image.load.3d.f32.i32(i32 1, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)

  ret float %tex
  ret float %tex

}
}




define amdgpu_ps float @image_load_3d_tfe_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) {
define amdgpu_ps float @image_load_3d_tfe_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) {

  ; GFX6-LABEL: name: image_load_3d_tfe_f32
  ; GFX6-LABEL: name: image_load_3d_tfe_f32

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX6:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GFX6:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32)
  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32)

  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[BUILD_VECTOR1]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[BUILD_VECTOR1]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GFX6:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GFX6:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
  ; GFX6:   $vgpr0 = COPY [[UV]](s32)

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX10NSA-LABEL: name: image_load_3d_tfe_f32
  ; GFX10NSA-LABEL: name: image_load_3d_tfe_f32

  ; GFX10NSA: bb.1 (%ir-block.0):
  ; GFX10NSA: bb.1 (%ir-block.0):

  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")
  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load 4 from custom "ImageResource")

  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)

  ; GFX10NSA:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
  ; GFX10NSA:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)

  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call { float, i32 } @llvm.amdgcn.image.load.3d.sl_f32i32s.i32(i32 1, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 1, i32 0)
  %val = call { float, i32 } @llvm.amdgcn.image.load.3d.sl_f32i32s.i32(i32 1, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 1, i32 0)

  %tex = extractvalue { float, i32 } %val, 0
  %tex = extractvalue { float, i32 } %val, 0

Show All 9 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s




define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {
define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {

  ; GFX9-LABEL: name: sample_1d
  ; GFX9-LABEL: name: sample_1d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY12]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY12]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_1d
  ; GFX10-LABEL: name: sample_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY12]](s32)
  ; GFX10:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY12]](s32)

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

main_body:
main_body:

  %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f16(i32 15, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
  %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f16(i32 15, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)

  ret <4 x float> %v
  ret <4 x float> %v

}
}




define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {

  ; GFX9-LABEL: name: sample_2d
  ; GFX9-LABEL: name: sample_2d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_2d
  ; GFX10-LABEL: name: sample_2d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %r) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 9 Linesdefine amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %r) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %face) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 9 Linesdefine amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %face) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %slice) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_1darray
  ; GFX10-LABEL: name: sample_1darray

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %slice) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 9 Linesdefine amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %slice) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_c_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_c_1d
  ; GFX10-LABEL: name: sample_c_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_c_2d
  ; GFX10-LABEL: name: sample_c_2d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_cl_1d
  ; GFX10-LABEL: name: sample_cl_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 9 Linesdefine amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_c_cl_1d
  ; GFX10-LABEL: name: sample_c_cl_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

Show All 10 Linesdefine amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_b_1d
  ; GFX10-LABEL: name: sample_b_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %t) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_b_2d
  ; GFX10-LABEL: name: sample_b_2d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_c_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_c_b_1d
  ; GFX10-LABEL: name: sample_c_b_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %t) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_c_b_2d
  ; GFX10-LABEL: name: sample_c_b_2d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_b_cl_1d
  ; GFX10-LABEL: name: sample_b_cl_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %t, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

Show All 10 Linesdefine amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %t, half %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_c_b_cl_1d
  ; GFX10-LABEL: name: sample_c_b_cl_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %t, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[DEF]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %t, half %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[DEF]](s32)

Show All 16 Linesdefine amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)

Show All 10 Linesdefine amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)

  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 12 Linesdefine amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 17 Linesdefine amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, half %s, half %t, half %r) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

Show All 19 Linesdefine amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, half %s, half %t, half %r) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

Show All 24 Linesdefine amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

Show All 16 Linesdefine amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)

  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 18 Linesdefine amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s, half %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)

Show All 16 Linesdefine amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)

  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 20 Linesdefine amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

Show All 12 Linesdefine amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

Show All 17 Linesdefine amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)

  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)

  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 16 Linesdefine amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)

  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 21 Linesdefine amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)

Show All 10 Linesdefine amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)

  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 12 Linesdefine amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 17 Linesdefine amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

Show All 16 Linesdefine amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)

  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 18 Linesdefine amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s, half %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)

Show All 16 Linesdefine amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)

  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 20 Linesdefine amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

Show All 12 Linesdefine amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

Show All 17 Linesdefine amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)

  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)

  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 16 Linesdefine amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)

  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

Show All 21 Linesdefine amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %lod) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_l_1d
  ; GFX10-LABEL: name: sample_l_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %lod) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 9 Linesdefine amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %lod) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %lod) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_c_l_1d
  ; GFX10-LABEL: name: sample_c_l_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %lod) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)

Show All 10 Linesdefine amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %lod) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY12]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY12]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_lz_1d
  ; GFX10-LABEL: name: sample_lz_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY12]](s32)
  ; GFX10:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY12]](s32)

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

main_body:
main_body:

  %v = call <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f16(i32 15, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
  %v = call <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f16(i32 15, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)

  ret <4 x float> %v
  ret <4 x float> %v

}
}




define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {

  ; GFX9-LABEL: name: sample_lz_2d
  ; GFX9-LABEL: name: sample_lz_2d

  ; GFX9: bb.1.main_body:
  ; GFX9: bb.1.main_body:

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_lz_2d
  ; GFX10-LABEL: name: sample_lz_2d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)

Show All 11 Linesdefine amdgpu_ps <4 x float> @sample_c_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_c_lz_1d
  ; GFX10-LABEL: name: sample_c_lz_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
  ; GFX9:   $vgpr0 = COPY [[UV]](s32)

  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)

  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)

  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)

  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX10-LABEL: name: sample_c_lz_2d
  ; GFX10-LABEL: name: sample_c_lz_2d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)

Show All 13 Linesdefine amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)

Show All 18 Linesdefine amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; GFX9:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX9:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX9:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX9:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX9:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)

Show All 15 Linesdefine amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)

▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s




define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {

  ; GFX10-LABEL: name: sample_d_1d
  ; GFX10-LABEL: name: sample_d_1d

  ; GFX10: bb.1.main_body:
  ; GFX10: bb.1.main_body:

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY16]](s32), [[COPY17]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY16]](s32), [[COPY17]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

Show All 14 Linesdefine amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

Show All 19 Linesdefine amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

Show All 14 Linesdefine amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY17]](s32), [[COPY18]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY17]](s32), [[COPY18]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

Show All 14 Linesdefine amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY15]](s32), [[COPY16]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY15]](s32), [[COPY16]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

Show All 14 Linesdefine amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY16]](s32), [[COPY17]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY16]](s32), [[COPY17]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

Show All 14 Linesdefine amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

Show All 14 Linesdefine amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY17]](s32), [[COPY18]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY17]](s32), [[COPY18]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
  ; GFX10:   $vgpr0 = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

Show All 14 Linesdefine amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY15]](s32), [[COPY16]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY15]](s32), [[COPY16]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)

Show All 14 Linesdefine amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)

  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")
  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load 16 from custom "ImageResource")

Show All 15 Linesdefine amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)

Show All 12 Linesdefine amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12

  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3

  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4

  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5

  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10:   [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6

  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX10:   [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7

  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
  ; GFX10:   [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)

  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
  ; GFX10:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)

  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
  ; GFX10:   [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)

  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
  ; GFX10:   [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)

  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
  ; GFX10:   [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)

  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
  ; GFX10:   [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)

  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
  ; GFX10:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)

Show All 35 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
Show All 10 Linesdefine amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, half %data) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; UNPACKED:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)
  ; UNPACKED:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 2 into custom "ImageResource")
  ; UNPACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 2 into custom "ImageResource")

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; GFX81-LABEL: name: image_store_f16
  ; GFX81-LABEL: name: image_store_f16

  ; GFX81: bb.1 (%ir-block.0):
  ; GFX81: bb.1 (%ir-block.0):

  ; GFX81:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX81:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX81:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX81:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX81:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX81:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX81:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX81:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX81:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX81:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX81:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX81:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX81:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX81:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX81:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX81:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX81:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX81:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX81:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX81:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX81:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX81:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX81:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX81:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX81:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX81:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)
  ; GFX81:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)

  ; GFX81:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX81:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX81:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX81:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 2 into custom "ImageResource")
  ; GFX81:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 2 into custom "ImageResource")

  ; GFX81:   S_ENDPGM 0
  ; GFX81:   S_ENDPGM 0

  ; GFX9-LABEL: name: image_store_f16
  ; GFX9-LABEL: name: image_store_f16

  ; GFX9: bb.1 (%ir-block.0):
  ; GFX9: bb.1 (%ir-block.0):

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)
  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 2 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 2 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10-LABEL: name: image_store_f16
  ; GFX10-LABEL: name: image_store_f16

  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10: bb.1 (%ir-block.0):

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2

  ; GFX10:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)
  ; GFX10:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 2 into custom "ImageResource")
  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 2 into custom "ImageResource")

  ; GFX10:   S_ENDPGM 0
  ; GFX10:   S_ENDPGM 0

  call void @llvm.amdgcn.image.store.2d.f16.i32(half %data, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  call void @llvm.amdgcn.image.store.2d.f16.i32(half %data, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @image_store_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <2 x half> %in) {
define amdgpu_ps void @image_store_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <2 x half> %in) {

  ; UNPACKED-LABEL: name: image_store_v2f16
  ; UNPACKED-LABEL: name: image_store_v2f16

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)
  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; UNPACKED:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; UNPACKED:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)

  ; UNPACKED:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; UNPACKED:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; UNPACKED:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY11]](s32), [[COPY12]](s32)
  ; UNPACKED:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY11]](s32), [[COPY12]](s32)

  ; UNPACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<2 x s32>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 4 into custom "ImageResource")
  ; UNPACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<2 x s32>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 4 into custom "ImageResource")

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; GFX81-LABEL: name: image_store_v2f16
  ; GFX81-LABEL: name: image_store_v2f16

  ; GFX81: bb.1 (%ir-block.0):
  ; GFX81: bb.1 (%ir-block.0):

  ; GFX81:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX81:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX81:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX81:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX81:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX81:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX81:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX81:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX81:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX81:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX81:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX81:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX81:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX81:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX81:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX81:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX81:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX81:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX81:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX81:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX81:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX81:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX81:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX81:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; GFX81:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX81:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX81:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX81:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX81:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)
  ; GFX81:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)

  ; GFX81:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX81:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX81:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[DEF]](s32)
  ; GFX81:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[DEF]](s32)

  ; GFX81:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<2 x s32>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 4 into custom "ImageResource")
  ; GFX81:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<2 x s32>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 4 into custom "ImageResource")

  ; GFX81:   S_ENDPGM 0
  ; GFX81:   S_ENDPGM 0

  ; GFX9-LABEL: name: image_store_v2f16
  ; GFX9-LABEL: name: image_store_v2f16

  ; GFX9: bb.1 (%ir-block.0):
  ; GFX9: bb.1 (%ir-block.0):

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[COPY10]](<2 x s16>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 4 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[COPY10]](<2 x s16>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 4 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10-LABEL: name: image_store_v2f16
  ; GFX10-LABEL: name: image_store_v2f16

  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10: bb.1 (%ir-block.0):

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[COPY10]](<2 x s16>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 4 into custom "ImageResource")
  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[COPY10]](<2 x s16>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 4 into custom "ImageResource")

  ; GFX10:   S_ENDPGM 0
  ; GFX10:   S_ENDPGM 0

  call void @llvm.amdgcn.image.store.2d.v2f16.i32(<2 x half> %in, i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  call void @llvm.amdgcn.image.store.2d.v2f16.i32(<2 x half> %in, i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <3 x half> %in) {
define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <3 x half> %in) {

  ; UNPACKED-LABEL: name: image_store_v3f16
  ; UNPACKED-LABEL: name: image_store_v3f16

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; UNPACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; UNPACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)
  ; UNPACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)

  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[CONCAT_VECTORS]](<6 x s16>)
  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[CONCAT_VECTORS]](<6 x s16>)

  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s96)
  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s96)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; UNPACKED:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
  ; UNPACKED:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)

  ; UNPACKED:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
  ; UNPACKED:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

Show All 9 Linesdefine amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <3 x half> %in) {

  ; GFX81:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX81:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX81:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX81:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX81:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX81:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX81:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX81:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX81:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX81:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX81:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX81:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX81:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX81:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX81:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX81:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX81:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX81:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX81:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX81:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX81:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX81:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; GFX81:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX81:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
  ; GFX81:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3

  ; GFX81:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX81:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; GFX81:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; GFX81:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)
  ; GFX81:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)

  ; GFX81:   [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[CONCAT_VECTORS]](<6 x s16>)
  ; GFX81:   [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[CONCAT_VECTORS]](<6 x s16>)

  ; GFX81:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s96)
  ; GFX81:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s96)

  ; GFX81:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX81:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX81:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
  ; GFX81:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)

  ; GFX81:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
  ; GFX81:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)

  ; GFX81:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX81:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

Show All 23 Linesdefine amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <3 x half> %in) {

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; GFX9:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)

  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[CONCAT_VECTORS]](<6 x s16>)
  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[CONCAT_VECTORS]](<6 x s16>)

  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s96)
  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s96)

  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)

  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)

  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

Show All 13 Linesdefine amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <3 x half> %in) {

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX10:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
  ; GFX10:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
  ; GFX10:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)

  ; GFX10:   [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[CONCAT_VECTORS]](<6 x s16>)
  ; GFX10:   [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[CONCAT_VECTORS]](<6 x s16>)

  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s96)
  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s96)

  ; GFX10:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; GFX10:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; GFX10:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
  ; GFX10:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)

  ; GFX10:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
  ; GFX10:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)

  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)

Show All 18 Linesdefine amdgpu_ps void @image_store_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <4 x half> %in) {

  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3

  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)
  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)

  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

  ; UNPACKED:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
  ; UNPACKED:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)

  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY11]](<2 x s16>)
  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY11]](<2 x s16>)

  ; UNPACKED:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
  ; UNPACKED:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)

  ; UNPACKED:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
  ; UNPACKED:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)

  ; UNPACKED:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
  ; UNPACKED:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)

  ; UNPACKED:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
  ; UNPACKED:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)

  ; UNPACKED:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
  ; UNPACKED:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)

  ; UNPACKED:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
  ; UNPACKED:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)

  ; UNPACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<4 x s32>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 8 into custom "ImageResource")
  ; UNPACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<4 x s32>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 8 into custom "ImageResource")

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; GFX81-LABEL: name: image_store_v4f16
  ; GFX81-LABEL: name: image_store_v4f16

  ; GFX81: bb.1 (%ir-block.0):
  ; GFX81: bb.1 (%ir-block.0):

  ; GFX81:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX81:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX81:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX81:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX81:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX81:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX81:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX81:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX81:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX81:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX81:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX81:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX81:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX81:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX81:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX81:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX81:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX81:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX81:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX81:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX81:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX81:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX81:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX81:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; GFX81:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX81:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
  ; GFX81:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3

  ; GFX81:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX81:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>)
  ; GFX81:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>)

  ; GFX81:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX81:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX81:   [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[CONCAT_VECTORS]](<4 x s16>)
  ; GFX81:   [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[CONCAT_VECTORS]](<4 x s16>)

  ; GFX81:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](<2 x s32>)
  ; GFX81:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](<2 x s32>)

  ; GFX81:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX81:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

  ; GFX81:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[DEF]](s32), [[DEF]](s32)
  ; GFX81:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[DEF]](s32), [[DEF]](s32)

  ; GFX81:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<4 x s32>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 8 into custom "ImageResource")
  ; GFX81:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<4 x s32>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 8 into custom "ImageResource")

  ; GFX81:   S_ENDPGM 0
  ; GFX81:   S_ENDPGM 0

  ; GFX9-LABEL: name: image_store_v4f16
  ; GFX9-LABEL: name: image_store_v4f16

  ; GFX9: bb.1 (%ir-block.0):
  ; GFX9: bb.1 (%ir-block.0):

  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX9:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; GFX9:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX9:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
  ; GFX9:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3

  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>)
  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>)

  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[CONCAT_VECTORS]](<4 x s16>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 8 into custom "ImageResource")
  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[CONCAT_VECTORS]](<4 x s16>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 8 into custom "ImageResource")

  ; GFX9:   S_ENDPGM 0
  ; GFX9:   S_ENDPGM 0

  ; GFX10-LABEL: name: image_store_v4f16
  ; GFX10-LABEL: name: image_store_v4f16

  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10: bb.1 (%ir-block.0):

  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2

  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3

  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4

  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5

  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6

  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7

  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8

  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0

  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1

  ; GFX10:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
  ; GFX10:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2

  ; GFX10:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
  ; GFX10:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3

  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>)
  ; GFX10:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>)

  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)

  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[CONCAT_VECTORS]](<4 x s16>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 8 into custom "ImageResource")
  ; GFX10:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[CONCAT_VECTORS]](<4 x s16>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 8 into custom "ImageResource")

  ; GFX10:   S_ENDPGM 0
  ; GFX10:   S_ENDPGM 0

  call void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half> %in, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  call void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half> %in, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)

  ret void
  ret void

}
}




declare void @llvm.amdgcn.image.store.2d.f16.i32(half, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
declare void @llvm.amdgcn.image.store.2d.f16.i32(half, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0

declare void @llvm.amdgcn.image.store.2d.v2f16.i32(<2 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
declare void @llvm.amdgcn.image.store.2d.v2f16.i32(<2 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0

declare void @llvm.amdgcn.image.store.2d.v3f16.i32(<3 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
declare void @llvm.amdgcn.image.store.2d.v3f16.i32(<3 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0

declare void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
declare void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0




attributes #0 = { nounwind writeonly }
attributes #0 = { nounwind writeonly }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps float @raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[BUFFER_ATOMIC_ADD_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_ADD_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_OFFEN_RTN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_OFFEN_RTN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i32 %ret to float
  %cast = bitcast i32 %ret to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @raw_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[BUFFER_ATOMIC_ADD_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_ADD_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_OFFEN_RTN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_OFFEN_RTN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i32 %ret to float
  %cast = bitcast i32 %ret to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps <2 x float> @raw_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i64 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x float> @raw_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i64 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[BUFFER_ATOMIC_ADD_X2_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_ADD_X2_OFFEN_RTN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 8 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_ADD_X2_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_ADD_X2_OFFEN_RTN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 8 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_OFFEN_RTN]].sub0
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_OFFEN_RTN]].sub0

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_OFFEN_RTN]].sub1
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_OFFEN_RTN]].sub1

  ; CHECK:   $vgpr0 = COPY [[COPY8]]
  ; CHECK:   $vgpr0 = COPY [[COPY8]]

  ; CHECK:   $vgpr1 = COPY [[COPY9]]
  ; CHECK:   $vgpr1 = COPY [[COPY9]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %ret = call i64 @llvm.amdgcn.raw.buffer.atomic.add.i64(i64 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i64 @llvm.amdgcn.raw.buffer.atomic.add.i64(i64 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i64 %ret to <2 x float>
  %cast = bitcast i64 %ret to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}




define amdgpu_ps void @raw_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i64 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i64 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[BUFFER_ATOMIC_ADD_X2_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_ADD_X2_OFFEN_RTN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 8 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_ADD_X2_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_ADD_X2_OFFEN_RTN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 8 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call i64 @llvm.amdgcn.raw.buffer.atomic.add.i64(i64 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i64 @llvm.amdgcn.raw.buffer.atomic.add.i64(i64 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; All operands need regbank legalization
; All operands need regbank legalization

define amdgpu_ps float @raw_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps float @raw_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec

Show All 30 Linesdefine amdgpu_ps void @raw_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec

Show All 26 Linesdefine amdgpu_ps float @raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095(i32 %val, <4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095
  ; CHECK-LABEL: name: raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[BUFFER_ATOMIC_ADD_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_ADD_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_OFFEN_RTN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_OFFEN_RTN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %voffset = add i32 %voffset.base, 4095
  %voffset = add i32 %voffset.base, 4095

  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i32 %ret to float
  %cast = bitcast i32 %ret to float

  ret float %cast
  ret float %cast

}
}




; Natural mapping + slc
; Natural mapping + slc

define amdgpu_ps float @raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(i32 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(i32 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
  ; CHECK-LABEL: name: raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[BUFFER_ATOMIC_ADD_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_ADD_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_OFFEN_RTN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_OFFEN_RTN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)
  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)

  %cast = bitcast i32 %ret to float
  %cast = bitcast i32 %ret to float

  ret float %cast
  ret float %cast

}
}




declare i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32 immarg) #0
declare i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32 immarg) #0

declare i64 @llvm.amdgcn.raw.buffer.atomic.add.i64(i64, <4 x i32>, i32, i32, i32 immarg) #0
declare i64 @llvm.amdgcn.raw.buffer.atomic.add.i64(i64, <4 x i32>, i32, i32, i32 immarg) #0




attributes #0 = { nounwind }
attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN]].sub0
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN]].sub0

  ; CHECK:   $vgpr0 = COPY [[COPY8]]
  ; CHECK:   $vgpr0 = COPY [[COPY8]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i32 %ret to float
  %cast = bitcast i32 %ret to float

  ret float %cast
  ret float %cast

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps void @raw_buffer_atomic_cmpswap_i32_noret__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_atomic_cmpswap_i32_noret__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_cmpswap_i32_noret__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_cmpswap_i32_noret__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN]].sub0
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN]].sub0

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; All operands need regbank legalization
; All operands need regbank legalization

define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, i32 inreg %cmp, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, i32 inreg %cmp, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 34 Linesdefine amdgpu_ps void @raw_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, i32 inreg %cmp, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 30 Linesdefine amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 4095, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 4095, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN]].sub0
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN]].sub0

  ; CHECK:   $vgpr0 = COPY [[COPY8]]
  ; CHECK:   $vgpr0 = COPY [[COPY8]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %voffset = add i32 %voffset.base, 4095
  %voffset = add i32 %voffset.base, 4095

  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i32 %ret to float
  %cast = bitcast i32 %ret to float

Show All 21 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   BUFFER_ATOMIC_ADD_F32_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_ADD_F32_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_plus4095__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_plus4095__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_plus4095__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_plus4095__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   BUFFER_ATOMIC_ADD_F32_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_ADD_F32_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 4095
  %voffset.add = add i32 %voffset, 4095

  %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_4095__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_4095__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_4095__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_4095__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   BUFFER_ATOMIC_ADD_F32_OFFSET [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_ADD_F32_OFFSET [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
  %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; Natural mapping, no voffset
; Natural mapping, no voffset

define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   BUFFER_ATOMIC_ADD_F32_OFFSET [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_ADD_F32_OFFSET [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)
  %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; All operands need regbank legalization
; All operands need regbank legalization

define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset(float inreg %val, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset(float inreg %val, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec

Show All 28 Linesdefine amdgpu_ps void @raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__0_voffset__vgpr_soffset(float inreg %val, <4 x i32> %rsrc, i32 %soffset) {

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

Show All 25 Linesdefine amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095(float %val, <4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095
  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   BUFFER_ATOMIC_ADD_F32_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_ADD_F32_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset = add i32 %voffset.base, 4095
  %voffset = add i32 %voffset.base, 4095

  %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; Natural mapping + slc
; Natural mapping + slc

define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
  ; CHECK-LABEL: name: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   BUFFER_ATOMIC_ADD_F32_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_ADD_F32_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)
  %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   BUFFER_ATOMIC_PK_ADD_F16_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_PK_ADD_F16_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   BUFFER_ATOMIC_PK_ADD_F16_OFFSET [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_PK_ADD_F16_OFFSET [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)
  %ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)

  ret void
  ret void

}
}




declare float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i32 immarg) #0
declare float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i32 immarg) #0

declare <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i32 immarg) #0
declare <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i32 immarg) #0




attributes #0 = { nounwind }
attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s




; Natural mapping
; Natural mapping

define amdgpu_ps half @raw_buffer_load_format_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @raw_buffer_load_format_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; PACKED-LABEL: name: raw_buffer_load_format_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: raw_buffer_load_format_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_OFFEN]]
  ; PACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_OFFEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; UNPACKED-LABEL: name: raw_buffer_load_format_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: raw_buffer_load_format_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]
  ; UNPACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call half @llvm.amdgcn.raw.buffer.load.format.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call half @llvm.amdgcn.raw.buffer.load.format.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret half %val
  ret half %val

}
}




define amdgpu_ps <2 x half> @raw_buffer_load_format_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x half> @raw_buffer_load_format_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; PACKED-LABEL: name: raw_buffer_load_format_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: raw_buffer_load_format_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_XY_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_XY_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_XY_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_XY_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_OFFEN]]
  ; PACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_OFFEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; UNPACKED-LABEL: name: raw_buffer_load_format_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: raw_buffer_load_format_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN]].sub0
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN]].sub0

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN]].sub1
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN]].sub1

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY6]], [[COPY8]], implicit $exec
  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY6]], [[COPY8]], implicit $exec

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY7]], [[COPY9]], implicit $exec
  ; UNPACKED:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY7]], [[COPY9]], implicit $exec

Show All 16 Lines
define amdgpu_ps <4 x half> @raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <4 x half> @raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; PACKED-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub0
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub0

  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub1
  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub1

  ; PACKED:   $vgpr0 = COPY [[COPY6]]
  ; PACKED:   $vgpr0 = COPY [[COPY6]]

  ; PACKED:   $vgpr1 = COPY [[COPY7]]
  ; PACKED:   $vgpr1 = COPY [[COPY7]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  ; UNPACKED-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub0
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub0

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub1
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub1

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub2
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub2

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub3
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY6]], [[COPY10]], implicit $exec
  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY6]], [[COPY10]], implicit $exec

Show All 22 Linesdefine amdgpu_ps half @raw_buffer_load_format_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; PACKED-LABEL: name: raw_buffer_load_format_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset
  ; PACKED-LABEL: name: raw_buffer_load_format_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; PACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

Show All 21 Linesdefine amdgpu_ps half @raw_buffer_load_format_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; UNPACKED-LABEL: name: raw_buffer_load_format_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset
  ; UNPACKED-LABEL: name: raw_buffer_load_format_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; UNPACKED: bb.2:
  ; UNPACKED: bb.2:

  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

Show All 25 Lines
define amdgpu_ps <4 x half> @raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps <4 x half> @raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; PACKED-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095
  ; PACKED-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource" + 4095, align 1, addrspace 4)
  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource" + 4095, align 1, addrspace 4)

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub0
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub0

  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub1
  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub1

  ; PACKED:   $vgpr0 = COPY [[COPY6]]
  ; PACKED:   $vgpr0 = COPY [[COPY6]]

  ; PACKED:   $vgpr1 = COPY [[COPY7]]
  ; PACKED:   $vgpr1 = COPY [[COPY7]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  ; UNPACKED-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095
  ; UNPACKED-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource" + 4095, align 1, addrspace 4)
  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource" + 4095, align 1, addrspace 4)

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub0
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub0

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub1
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub1

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub2
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub2

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub3
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY6]], [[COPY10]], implicit $exec
  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY6]], [[COPY10]], implicit $exec

Show All 27 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps float @raw_buffer_load_format_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_format_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_format_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_format_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps <2 x float> @raw_buffer_load_format_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x float> @raw_buffer_load_format_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_format_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_format_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_FORMAT_XY_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_XY_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_FORMAT_XY_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_XY_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XY_OFFEN]].sub0
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XY_OFFEN]].sub0

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XY_OFFEN]].sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XY_OFFEN]].sub1

  ; CHECK:   $vgpr0 = COPY [[COPY6]]
  ; CHECK:   $vgpr0 = COPY [[COPY6]]

  ; CHECK:   $vgpr1 = COPY [[COPY7]]
  ; CHECK:   $vgpr1 = COPY [[COPY7]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %val = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret <2 x float> %val
  ret <2 x float> %val

}
}




define amdgpu_ps <3 x float> @raw_buffer_load_format_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <3 x float> @raw_buffer_load_format_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_format_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_format_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_FORMAT_XYZ_OFFEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_FORMAT_XYZ_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_FORMAT_XYZ_OFFEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_FORMAT_XYZ_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub0
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub0

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub2
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub2

  ; CHECK:   $vgpr0 = COPY [[COPY6]]
  ; CHECK:   $vgpr0 = COPY [[COPY6]]

  ; CHECK:   $vgpr1 = COPY [[COPY7]]
  ; CHECK:   $vgpr1 = COPY [[COPY7]]

  ; CHECK:   $vgpr2 = COPY [[COPY8]]
  ; CHECK:   $vgpr2 = COPY [[COPY8]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2

  %val = call <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret <3 x float> %val
  ret <3 x float> %val

}
}




define amdgpu_ps <4 x float> @raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <4 x float> @raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_FORMAT_XYZW_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_FORMAT_XYZW_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub0
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub0

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub2
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub2

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub3
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub3

  ; CHECK:   $vgpr0 = COPY [[COPY6]]
  ; CHECK:   $vgpr0 = COPY [[COPY6]]

  ; CHECK:   $vgpr1 = COPY [[COPY7]]
  ; CHECK:   $vgpr1 = COPY [[COPY7]]

  ; CHECK:   $vgpr2 = COPY [[COPY8]]
  ; CHECK:   $vgpr2 = COPY [[COPY8]]

  ; CHECK:   $vgpr3 = COPY [[COPY9]]
  ; CHECK:   $vgpr3 = COPY [[COPY9]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  %val = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret <4 x float> %val
  ret <4 x float> %val

}
}




; Waterfall for rsrc and soffset, copy for voffset
; Waterfall for rsrc and soffset, copy for voffset

define amdgpu_ps float @raw_buffer_load_format_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps float @raw_buffer_load_format_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_format_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_format_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

Show All 25 Lines
define amdgpu_ps <4 x float> @raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps <4 x float> @raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095
  ; CHECK-LABEL: name: raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_FORMAT_XYZW_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_FORMAT_XYZW_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub0
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub0

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub2
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub2

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub3
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub3

  ; CHECK:   $vgpr0 = COPY [[COPY6]]
  ; CHECK:   $vgpr0 = COPY [[COPY6]]

  ; CHECK:   $vgpr1 = COPY [[COPY7]]
  ; CHECK:   $vgpr1 = COPY [[COPY7]]

  ; CHECK:   $vgpr2 = COPY [[COPY8]]
  ; CHECK:   $vgpr2 = COPY [[COPY8]]

Show All 13 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s

; FIXME: Test with SI when argument lowering not broken for f16
; FIXME: Test with SI when argument lowering not broken for f16




; Natural mapping
; Natural mapping

define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




; Copies for VGPR arguments
; Copies for VGPR arguments

define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




; Waterfall for rsrc
; Waterfall for rsrc

define amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 23 Linesdefine amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 25 Lines
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 1)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 1)

  ret float %val
  ret float %val

}
}




; Natural mapping + slc
; Natural mapping + slc

define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)

  ret float %val
  ret float %val

}
}




; Natural mapping + dlc
; Natural mapping + dlc

define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 4)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 4)

  ret float %val
  ret float %val

}
}




; Natural mapping + slc + dlc
; Natural mapping + slc + dlc

define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_dlc
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_dlc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 1, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 1, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 6)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 6)

  ret float %val
  ret float %val

}
}




; Natural mapping + glc + dlc
; Natural mapping + glc + dlc

define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_dlc
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_dlc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 1, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 1, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 5)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 5)

  ret float %val
  ret float %val

}
}




; Natural mapping + glc + slc + dlc
; Natural mapping + glc + slc + dlc

define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_slc_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_slc_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_slc_dlc
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_slc_dlc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 1, 1, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 1, 1, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 7)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 7)

  ret float %val
  ret float %val

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps <2 x float> @raw_buffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x float> @raw_buffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1

  ; CHECK:   $vgpr0 = COPY [[COPY6]]
  ; CHECK:   $vgpr0 = COPY [[COPY6]]

  ; CHECK:   $vgpr1 = COPY [[COPY7]]
  ; CHECK:   $vgpr1 = COPY [[COPY7]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %val = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret <2 x float> %val
  ret <2 x float> %val

}
}




define amdgpu_ps <3 x float> @raw_buffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <3 x float> @raw_buffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORDX3_OFFEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORDX3_OFFEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFEN]].sub0
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFEN]].sub0

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFEN]].sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFEN]].sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFEN]].sub2
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFEN]].sub2

  ; CHECK:   $vgpr0 = COPY [[COPY6]]
  ; CHECK:   $vgpr0 = COPY [[COPY6]]

  ; CHECK:   $vgpr1 = COPY [[COPY7]]
  ; CHECK:   $vgpr1 = COPY [[COPY7]]

  ; CHECK:   $vgpr2 = COPY [[COPY8]]
  ; CHECK:   $vgpr2 = COPY [[COPY8]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2

  %val = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret <3 x float> %val
  ret <3 x float> %val

}
}




define amdgpu_ps <4 x float> @raw_buffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <4 x float> @raw_buffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3

  ; CHECK:   $vgpr0 = COPY [[COPY6]]
  ; CHECK:   $vgpr0 = COPY [[COPY6]]

  ; CHECK:   $vgpr1 = COPY [[COPY7]]
  ; CHECK:   $vgpr1 = COPY [[COPY7]]

  ; CHECK:   $vgpr2 = COPY [[COPY8]]
  ; CHECK:   $vgpr2 = COPY [[COPY8]]

  ; CHECK:   $vgpr3 = COPY [[COPY9]]
  ; CHECK:   $vgpr3 = COPY [[COPY9]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  %val = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret <4 x float> %val
  ret <4 x float> %val

}
}




define amdgpu_ps half @raw_buffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @raw_buffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_USHORT_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_USHORT_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_USHORT_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_USHORT_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret half %val
  ret half %val

}
}




define amdgpu_ps <2 x half> @raw_buffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x half> @raw_buffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret <2 x half> %val
  ret <2 x half> %val

}
}




; FIXME: Crashes
; FIXME: Crashes

; define amdgpu_ps <3 x half> @raw_buffer_load_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
; define amdgpu_ps <3 x half> @raw_buffer_load_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

;   %val = call <3 x half> @llvm.amdgcn.raw.buffer.load.v3f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
;   %val = call <3 x half> @llvm.amdgcn.raw.buffer.load.v3f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

;   ret <3 x half> %val
;   ret <3 x half> %val

; }
; }




define amdgpu_ps <4 x half> @raw_buffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <4 x half> @raw_buffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1

  ; CHECK:   $vgpr0 = COPY [[COPY6]]
  ; CHECK:   $vgpr0 = COPY [[COPY6]]

  ; CHECK:   $vgpr1 = COPY [[COPY7]]
  ; CHECK:   $vgpr1 = COPY [[COPY7]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %val = call <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret <4 x half> %val
  ret <4 x half> %val

}
}




define amdgpu_ps float @raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext
  ; CHECK-LABEL: name: raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "BufferResource", addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "BufferResource", addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  %zext = zext i8 %val to i32
  %zext = zext i8 %val to i32

  %cast = bitcast i32 %zext to float
  %cast = bitcast i32 %zext to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext
  ; CHECK-LABEL: name: raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "BufferResource", addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "BufferResource", addrspace 4)

  ; CHECK:   [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_UBYTE_OFFEN]], 0, 8, implicit $exec
  ; CHECK:   [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_UBYTE_OFFEN]], 0, 8, implicit $exec

  ; CHECK:   $vgpr0 = COPY [[V_BFE_I32_e64_]]
  ; CHECK:   $vgpr0 = COPY [[V_BFE_I32_e64_]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  %zext = sext i8 %val to i32
  %zext = sext i8 %val to i32

  %cast = bitcast i32 %zext to float
  %cast = bitcast i32 %zext to float

  ret float %cast
  ret float %cast

}
}




; Waterfall for rsrc
; Waterfall for rsrc

define amdgpu_ps half @raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 23 Linesdefine amdgpu_ps float @raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 23 Lines
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE]], [[COPY4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE]], [[COPY4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE]], [[COPY4]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE]], [[COPY4]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY5]], [[REG_SEQUENCE]], [[COPY4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4096, align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY5]], [[REG_SEQUENCE]], [[COPY4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4096, align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4096, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4096, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 16, align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 16, align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %voffset = add i32 %voffset.base, 16
  %voffset = add i32 %voffset.base, 16

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %voffset = add i32 %voffset.base, 4095
  %voffset = add i32 %voffset.base, 4095

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   %10:vgpr_32, dead %15:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
  ; CHECK:   %10:vgpr_32, dead %15:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %10, [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4096, align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %10, [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4096, align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %voffset = add i32 %voffset.base, 4096
  %voffset = add i32 %voffset.base, 4096

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095(<4 x i32> inreg %rsrc, i32 %voffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095(<4 x i32> inreg %rsrc, i32 %voffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096(<4 x i32> inreg %rsrc, i32 %voffset) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096(<4 x i32> inreg %rsrc, i32 %voffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %soffset = add i32 %soffset.base, 16
  %soffset = add i32 %soffset.base, 16

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095

  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %soffset = add i32 %soffset.base, 4095
  %soffset = add i32 %soffset.base, 4095

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc

  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %soffset = add i32 %soffset.base, 4096
  %soffset = add i32 %soffset.base, 4096

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




; An add of the offset is necessary, with a waterfall loop. Make sure the add is done outside of the waterfall loop.
; An add of the offset is necessary, with a waterfall loop. Make sure the add is done outside of the waterfall loop.

define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset.base) {
define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000

  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc

  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec

Show All 26 Linesdefine amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add5000(<4 x i32> %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add5000
  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add5000

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   %13:vgpr_32, dead %35:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
  ; CHECK:   %13:vgpr_32, dead %35:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 36 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16
  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16
  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16
  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource" + 4095, align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource" + 4095, align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16
  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   BUFFER_STORE_FORMAT_D16_X_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource" + 4095, align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_X_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource" + 4095, align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16
  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY7]], [[COPY4]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY7]], [[COPY4]], implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16
  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> inreg %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> inreg %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16
  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY5]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY5]], implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16
  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; Make sure unpack code is emitted outside of loop
; Make sure unpack code is emitted outside of loop

define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16
  ; UNPACKED-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY5]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY5]], implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; UNPACKED:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; UNPACKED:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

Show All 22 Linesdefine amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; PACKED-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16
  ; PACKED-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec

  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec

  ; PACKED:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 20 Lines
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095
  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095

  ; UNPACKED:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY6]], [[COPY4]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY6]], [[COPY4]], implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095
  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
  ; PACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095

  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096
  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; UNPACKED:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY6]], [[COPY4]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY6]], [[COPY4]], implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096
  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; PACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16
  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY7]], [[COPY4]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY7]], [[COPY4]], implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 16, align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 16, align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16
  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 16, align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 16, align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 16
  %voffset.add = add i32 %voffset, 16

  call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095
  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY7]], [[COPY4]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY7]], [[COPY4]], implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095
  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 4095
  %voffset.add = add i32 %voffset, 4095

  call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096
  ; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   %11:vgpr_32, dead %24:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
  ; UNPACKED:   %11:vgpr_32, dead %24:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec

  ; UNPACKED:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096
  ; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; PACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; PACKED:   %11:vgpr_32, dead %15:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
  ; PACKED:   %11:vgpr_32, dead %15:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec

  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 4096
  %voffset.add = add i32 %voffset, 4096

  call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}







; Check what happens with offset add inside a waterfall loop
; Check what happens with offset add inside a waterfall loop

define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16_add_4096(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16_add_4096(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16_add_4096
  ; UNPACKED-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16_add_4096

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   %13:vgpr_32, dead %49:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec
  ; UNPACKED:   %13:vgpr_32, dead %49:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec

  ; UNPACKED:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY4]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY4]], implicit $exec

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY10]], [[COPY5]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY10]], [[COPY5]], implicit $exec

Show All 25 Linesdefine amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16_add_4096(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; PACKED-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16_add_4096
  ; PACKED-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16_add_4096

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; PACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; PACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; PACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; PACKED:   %13:vgpr_32, dead %33:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec
  ; PACKED:   %13:vgpr_32, dead %33:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec

  ; PACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 27 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s | FileCheck %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck %s




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32
  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f32(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f32(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f32
  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32
  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32(<4 x i32> inreg %rsrc, <3 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32(<4 x i32> inreg %rsrc, <3 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32
  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2

  ; CHECK:   BUFFER_STORE_FORMAT_XYZ_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_XYZ_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32(<4 x i32> inreg %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32(<4 x i32> inreg %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32
  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_FORMAT_XYZW_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_XYZW_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32(<4 x i32> %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32(<4 x i32> %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32
  ; CHECK-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr7
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr7

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr8
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr8

  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 20 Lines
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4095(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4095(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4095
  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095

  ; CHECK:   BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4096(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4096(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4096
  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_16(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_16(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_16
  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource" + 16, align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource" + 16, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 16
  %voffset.add = add i32 %voffset, 16

  call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4095(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4095(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4095
  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 4095
  %voffset.add = add i32 %voffset, 4095

  call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4096(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4096(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4096
  ; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   %13:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec
  ; CHECK:   %13:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec

  ; CHECK:   BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], %13, [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource" + 4096, align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], %13, [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource" + 4096, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 4096
  %voffset.add = add i32 %voffset, 4096

  call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}







; Check what happens with offset add inside a waterfall loop
; Check what happens with offset add inside a waterfall loop

define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32_add_4096(<4 x i32> %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32_add_4096(<4 x i32> %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32_add_4096
  ; CHECK-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32_add_4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr7
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr7

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr8
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr8

  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   %15:vgpr_32, dead %35:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY8]], [[COPY10]], 0, implicit $exec
  ; CHECK:   %15:vgpr_32, dead %35:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY8]], [[COPY10]], 0, implicit $exec

  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 28 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s

; FIXME: Test with SI when argument lowering not broken for f16
; FIXME: Test with SI when argument lowering not broken for f16




; Natural mapping
; Natural mapping

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; Copies for VGPR arguments
; Copies for VGPR arguments

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float inreg %val, i32 inreg %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float inreg %val, i32 inreg %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr8
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr8

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY7]], [[COPY8]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY7]], [[COPY8]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; Waterfall for rsrc
; Waterfall for rsrc

define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 22 Linesdefine amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec

  ; CHECK:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]], [[COPY6]], implicit $exec
  ; CHECK:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]], [[COPY6]], implicit $exec

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[V_READFIRSTLANE_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[V_READFIRSTLANE_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec
  ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec

  ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
  ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc

Show All 12 Linesdefine amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, float %val, i32 %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 23 Lines
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 1)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 1)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 3)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 3)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_dlc
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_dlc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 4)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 4)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc_dlc
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc_dlc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 1, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 1, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 6)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 6)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_dlc
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_dlc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 5)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 5)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc_dlc
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc_dlc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 7)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 7)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32(<4 x i32> inreg %rsrc, <3 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32(<4 x i32> inreg %rsrc, <3 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2

  ; CHECK:   BUFFER_STORE_DWORDX3_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORDX3_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32(<4 x i32> inreg %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32(<4 x i32> inreg %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORDX4_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORDX4_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i8(<4 x i32> inreg %rsrc, i32 %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i8(<4 x i32> inreg %rsrc, i32 %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i8
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i8

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_BYTE_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 1 into custom "BufferResource", addrspace 4)
  ; CHECK:   BUFFER_STORE_BYTE_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 1 into custom "BufferResource", addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %val.trunc = trunc i32 %val to i8
  %val.trunc = trunc i32 %val to i8

  call void @llvm.amdgcn.raw.buffer.store.i8(i8 %val.trunc, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.i8(i8 %val.trunc, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i16(<4 x i32> inreg %rsrc, i32 %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i16(<4 x i32> inreg %rsrc, i32 %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i16
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %val.trunc = trunc i32 %val to i16
  %val.trunc = trunc i32 %val to i16

  call void @llvm.amdgcn.raw.buffer.store.i16(i16 %val.trunc, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.i16(i16 %val.trunc, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> inreg %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> inreg %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16
  ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 20 Lines
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4095(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4095(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4095
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4096(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4096(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4096
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4096, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4096, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_16(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_16(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_16
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 16, align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 16, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 16
  %voffset.add = add i32 %voffset, 16

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4095(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4095(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4095
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 4095
  %voffset.add = add i32 %voffset, 4095

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4096(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4096(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4096
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   %11:vgpr_32, dead %15:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
  ; CHECK:   %11:vgpr_32, dead %15:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 4096
  %voffset.add = add i32 %voffset, 4096

  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_16
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 16, align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 16, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 16
  %voffset.add = add i32 %voffset, 16

  call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4095
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 4095
  %voffset.add = add i32 %voffset, 4095

  call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4096
  ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   %11:vgpr_32, dead %15:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
  ; CHECK:   %11:vgpr_32, dead %15:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec

  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 4096
  %voffset.add = add i32 %voffset, 4096

  call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
  call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; An add of the offset is necessary, with a waterfall loop. Make sure the add is done outside of the waterfall loop.
; An add of the offset is necessary, with a waterfall loop. Make sure the add is done outside of the waterfall loop.

define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_offset_add_5000(<4 x i32> %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_offset_add_5000(<4 x i32> %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_offset_add_5000
  ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_offset_add_5000

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   %13:vgpr_32, dead %33:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
  ; CHECK:   %13:vgpr_32, dead %33:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 26 Linesdefine amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr_soffset_offset(<4 x i32> %rsrc, float %val, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr_soffset_offset
  ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr_soffset_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

Show All 33 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s




define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]
  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN]]
  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret half %val
  ret half %val

}
}




define amdgpu_ps <2 x half> @raw_tbuffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x half> @raw_tbuffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: raw_tbuffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN]].sub0
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN]].sub0

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN]].sub1
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN]].sub1

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY6]], [[COPY8]], implicit $exec
  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY6]], [[COPY8]], implicit $exec

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY7]], [[COPY9]], implicit $exec
  ; UNPACKED:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY7]], [[COPY9]], implicit $exec

  ; UNPACKED:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]

  ; UNPACKED:   [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY10]], [[V_AND_B32_e64_1]], implicit $exec
  ; UNPACKED:   [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY10]], [[V_AND_B32_e64_1]], implicit $exec

  ; UNPACKED:   [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_AND_B32_e64_]], [[V_LSHLREV_B32_e64_]], implicit $exec
  ; UNPACKED:   [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_AND_B32_e64_]], [[V_LSHLREV_B32_e64_]], implicit $exec

  ; UNPACKED:   $vgpr0 = COPY [[V_OR_B32_e64_]]
  ; UNPACKED:   $vgpr0 = COPY [[V_OR_B32_e64_]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: raw_tbuffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: raw_tbuffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_XY_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_XY_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_XY_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_XY_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_OFFEN]]
  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_OFFEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret <2 x half> %val
  ret <2 x half> %val

}
}




; FIXME: Crashes
; FIXME: Crashes

; define amdgpu_ps <3 x half> @raw_tbuffer_load_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
; define amdgpu_ps <3 x half> @raw_tbuffer_load_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

;   %val = call <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
;   %val = call <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

;   ret <3 x half> %val
;   ret <3 x half> %val

; }
; }




define amdgpu_ps <4 x half> @raw_tbuffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <4 x half> @raw_tbuffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: raw_tbuffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub0
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub0

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub1
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub1

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub2
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub2

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub3
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY6]], [[COPY10]], implicit $exec
  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY6]], [[COPY10]], implicit $exec

Show All 15 Linesdefine amdgpu_ps <4 x half> @raw_tbuffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  ; PACKED-LABEL: name: raw_tbuffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: raw_tbuffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub0
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub0

  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub1
  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub1

  ; PACKED:   $vgpr0 = COPY [[COPY6]]
  ; PACKED:   $vgpr0 = COPY [[COPY6]]

  ; PACKED:   $vgpr1 = COPY [[COPY7]]
  ; PACKED:   $vgpr1 = COPY [[COPY7]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %val = call <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret <4 x half> %val
  ret <4 x half> %val

}
}




define amdgpu_ps half @raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps half @raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset
  ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; UNPACKED: bb.2:
  ; UNPACKED: bb.2:

  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

Show All 21 Linesdefine amdgpu_ps half @raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; PACKED-LABEL: name: raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset
  ; PACKED-LABEL: name: raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; PACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

Show All 25 Lines
define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
  ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]
  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
  ; PACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN]]
  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1)
  %val = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1)

  ret half %val
  ret half %val

}
}




define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
  ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]
  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
  ; PACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN]]
  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2)
  %val = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2)

  ret half %val
  ret half %val

}
}




define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc
  ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]
  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc
  ; PACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN]]
  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3)
  %val = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3)

  ret half %val
  ret half %val

}
}




define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc
  ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]
  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc
  ; PACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN]]
  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4)
  %val = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4)

  ret half %val
  ret half %val

}
}




declare half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0
declare half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0

declare <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0
declare <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0

declare <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0
declare <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0

declare <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0
declare <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0




attributes #0 = { nounwind readonly }
attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps <2 x float> @raw_tbuffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x float> @raw_tbuffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_tbuffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XY_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_XY_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XY_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_XY_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_OFFEN]].sub0
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_OFFEN]].sub0

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_OFFEN]].sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_OFFEN]].sub1

  ; CHECK:   $vgpr0 = COPY [[COPY6]]
  ; CHECK:   $vgpr0 = COPY [[COPY6]]

  ; CHECK:   $vgpr1 = COPY [[COPY7]]
  ; CHECK:   $vgpr1 = COPY [[COPY7]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %val = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret <2 x float> %val
  ret <2 x float> %val

}
}




define amdgpu_ps <3 x float> @raw_tbuffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <3 x float> @raw_tbuffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_tbuffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN:%[0-9]+]]:vreg_96 = TBUFFER_LOAD_FORMAT_XYZ_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN:%[0-9]+]]:vreg_96 = TBUFFER_LOAD_FORMAT_XYZ_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub0
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub0

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub2
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub2

  ; CHECK:   $vgpr0 = COPY [[COPY6]]
  ; CHECK:   $vgpr0 = COPY [[COPY6]]

  ; CHECK:   $vgpr1 = COPY [[COPY7]]
  ; CHECK:   $vgpr1 = COPY [[COPY7]]

  ; CHECK:   $vgpr2 = COPY [[COPY8]]
  ; CHECK:   $vgpr2 = COPY [[COPY8]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2

  %val = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret <3 x float> %val
  ret <3 x float> %val

}
}




define amdgpu_ps <4 x float> @raw_tbuffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <4 x float> @raw_tbuffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_tbuffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub0
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub0

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub2
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub2

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub3
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub3

  ; CHECK:   $vgpr0 = COPY [[COPY6]]
  ; CHECK:   $vgpr0 = COPY [[COPY6]]

  ; CHECK:   $vgpr1 = COPY [[COPY7]]
  ; CHECK:   $vgpr1 = COPY [[COPY7]]

  ; CHECK:   $vgpr2 = COPY [[COPY8]]
  ; CHECK:   $vgpr2 = COPY [[COPY8]]

  ; CHECK:   $vgpr3 = COPY [[COPY9]]
  ; CHECK:   $vgpr3 = COPY [[COPY9]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  %val = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret <4 x float> %val
  ret <4 x float> %val

}
}




define amdgpu_ps float @raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps float @raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

Show All 25 Lines
define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1)
  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2)
  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc
  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3)
  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc
  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]
  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4)
  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4)

  ret float %val
  ret float %val

}
}




declare float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0
declare float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0

declare <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0
declare <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0

declare <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0
declare <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0

declare <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0
declare <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0




attributes #0 = { nounwind readonly }
attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s




define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(half %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(half %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_store_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: raw_tbuffer_store_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY7]], [[COPY]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY7]], [[COPY]], implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1

  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_tbuffer_store_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: raw_tbuffer_store_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   TBUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   TBUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret void
  ret void

}
}




; FIXME: Crashes
; FIXME: Crashes

; define amdgpu_ps void @raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<3 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
; define amdgpu_ps void @raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<3 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

;   call void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
;   call void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

;   ret void
;   ret void

; }
; }




define amdgpu_ps void @raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY]], implicit $exec

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY1]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY1]], implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY1]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY1]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3

  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; PACKED:   TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret void
  ret void

}
}




; Waterfall for rsrc
; Waterfall for rsrc

define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset(half %val, <4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset(half %val, <4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; UNPACKED: bb.2:
  ; UNPACKED: bb.2:

  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 17 Linesdefine amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset(half %val, <4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 23 Linesdefine amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soffset(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset) {

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; UNPACKED:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; UNPACKED: bb.2:
  ; UNPACKED: bb.2:

  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 20 Linesdefine amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soffset(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset) {

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; PACKED:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 26 Linesdefine amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset(half %val, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; UNPACKED: bb.2:
  ; UNPACKED: bb.2:

  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec

  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec

Show All 21 Linesdefine amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset(half %val, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec

  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec

Show All 25 Linesdefine amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc(half %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
  ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
  ; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1)
  call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(half %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(half %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
  ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
  ; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2)
  call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc(half %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc(half %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc
  ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc
  ; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3)
  call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc(half %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc(half %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc
  ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc
  ; PACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4)
  call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4)

  ret void
  ret void

}
}




declare void @llvm.amdgcn.raw.tbuffer.store.f16(half, <4 x i32>, i32, i32, i32 immarg, i32 immarg)
declare void @llvm.amdgcn.raw.tbuffer.store.f16(half, <4 x i32>, i32, i32, i32 immarg, i32 immarg)

declare void @llvm.amdgcn.raw.tbuffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32 immarg, i32 immarg)
declare void @llvm.amdgcn.raw.tbuffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32 immarg, i32 immarg)

declare void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half>, <4 x i32>, i32, i32, i32 immarg, i32 immarg)
declare void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half>, <4 x i32>, i32, i32, i32 immarg, i32 immarg)

declare void @llvm.amdgcn.raw.tbuffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32 immarg, i32 immarg)
declare void @llvm.amdgcn.raw.tbuffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32 immarg, i32 immarg)

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s




define amdgpu_ps void @raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i8 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i8 %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 1 into custom "BufferResource", addrspace 4)
  ; UNPACKED:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 1 into custom "BufferResource", addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 1 into custom "BufferResource", addrspace 4)
  ; PACKED:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 1 into custom "BufferResource", addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.i8(i8 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.i8(i8 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)

  ret void
  ret void

}
}




; Waterfall for rsrc
; Waterfall for rsrc

define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset(i8 %val, <4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset(i8 %val, <4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; UNPACKED: bb.2:
  ; UNPACKED: bb.2:

  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 17 Linesdefine amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset(i8 %val, <4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 23 Linesdefine amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffset(i8 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset) {

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; UNPACKED:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; UNPACKED: bb.2:
  ; UNPACKED: bb.2:

  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 20 Linesdefine amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffset(i8 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset) {

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; PACKED:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 26 Linesdefine amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i8 %val, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; UNPACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; UNPACKED: bb.2:
  ; UNPACKED: bb.2:

  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec

  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec

Show All 21 Linesdefine amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i8 %val, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; PACKED:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec

  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret void
  ret void

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps void @raw_tbuffer_store_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x float> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x float> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_tbuffer_store_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   TBUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret void
  ret void

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps void @raw_tbuffer_store_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<3 x float> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<3 x float> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_tbuffer_store_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3

  ; CHECK:   TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact [[REG_SEQUENCE]], [[COPY7]], [[REG_SEQUENCE1]], [[COPY8]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact [[REG_SEQUENCE]], [[COPY7]], [[REG_SEQUENCE1]], [[COPY8]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret void
  ret void

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps void @raw_tbuffer_store_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x float> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x float> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_tbuffer_store_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact [[REG_SEQUENCE]], [[COPY8]], [[REG_SEQUENCE1]], [[COPY9]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact [[REG_SEQUENCE]], [[COPY8]], [[REG_SEQUENCE1]], [[COPY9]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret void
  ret void

}
}




; Copies for VGPR arguments
; Copies for VGPR arguments

define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr7
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr7

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)

  ret void
  ret void

}
}




; Waterfall for rsrc
; Waterfall for rsrc

define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 23 Linesdefine amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__vgpr_soffset(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset) {

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 26 Linesdefine amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset(float %val, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec

Show All 26 Linesdefine amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1)

  ret void
  ret void

}
}




; Natural mapping + slc
; Natural mapping + slc

define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2)

  ret void
  ret void

}
}




; Natural mapping + glc + slc
; Natural mapping + glc + slc

define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3)

  ret void
  ret void

}
}




; Natural mapping + dlc
; Natural mapping + dlc

define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4)

  ret void
  ret void

}
}










define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 0, i32 %soffset, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 0, i32 %soffset, i32 94, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 4095, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 4095, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 94, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 4096, i32 %soffset, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 4096, i32 %soffset, i32 94, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16(float %val, <4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16(float %val, <4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 16, align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 16, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset = add i32 %voffset.base, 16
  %voffset = add i32 %voffset.base, 16

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095(float %val, <4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095(float %val, <4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset = add i32 %voffset.base, 4095
  %voffset = add i32 %voffset.base, 4095

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096(float %val, <4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096(float %val, <4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
  ; CHECK:   [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource" + 4096, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset = add i32 %voffset.base, 4096
  %voffset = add i32 %voffset.base, 4096

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095(float %val, <4 x i32> inreg %rsrc, i32 %voffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095(float %val, <4 x i32> inreg %rsrc, i32 %voffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 94, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096(float %val, <4 x i32> inreg %rsrc, i32 %voffset) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096(float %val, <4 x i32> inreg %rsrc, i32 %voffset) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 94, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def $scc
  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def $scc

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %soffset = add i32 %soffset.base, 16
  %soffset = add i32 %soffset.base, 16

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095

  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def $scc
  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def $scc

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %soffset = add i32 %soffset.base, 4095
  %soffset = add i32 %soffset.base, 4095

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def $scc
  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def $scc

  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %soffset = add i32 %soffset.base, 4096
  %soffset = add i32 %soffset.base, 4096

  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)
  call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0)

  ret void
  ret void

}
}




; An add of the offset is necessary, with a waterfall loop. Make sure the add is done outside of the waterfall loop.
; An add of the offset is necessary, with a waterfall loop. Make sure the add is done outside of the waterfall loop.

define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000(float %val, <4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset.base) {
define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000(float %val, <4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000
  ; CHECK-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000

  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def $scc
  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def $scc

  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec

Show All 26 Linesdefine amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add5000(float %val, <4 x i32> %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
  ; CHECK:   [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec

  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 28 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs -simplify-mir -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs -simplify-mir -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX6 %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -verify-machineinstrs -simplify-mir -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX7 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -verify-machineinstrs -simplify-mir -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX7 %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs -simplify-mir -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs -simplify-mir -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s




; FIXME: Merge with regbankselect, which mostly overlaps when all types supported.
; FIXME: Merge with regbankselect, which mostly overlaps when all types supported.




; Natural mapping
; Natural mapping

define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_i32
  ; GFX6-LABEL: name: s_buffer_load_i32

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 4)
  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 4)

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]

  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec

  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0

  ; GFX7-LABEL: name: s_buffer_load_i32
  ; GFX7-LABEL: name: s_buffer_load_i32

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 4)
  ; GFX7:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 4)

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]

  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec

  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0

  ; GFX8-LABEL: name: s_buffer_load_i32
  ; GFX8-LABEL: name: s_buffer_load_i32

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 4)
  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 4)

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]

  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec

  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0

  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret i32 %val
  ret i32 %val

}
}




define amdgpu_ps i32 @s_buffer_load_i32_glc(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps i32 @s_buffer_load_i32_glc(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_i32_glc
  ; GFX6-LABEL: name: s_buffer_load_i32_glc

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1, 0 :: (dereferenceable invariant load 4)
  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1, 0 :: (dereferenceable invariant load 4)

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]

  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec

  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0

  ; GFX7-LABEL: name: s_buffer_load_i32_glc
  ; GFX7-LABEL: name: s_buffer_load_i32_glc

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1, 0 :: (dereferenceable invariant load 4)
  ; GFX7:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1, 0 :: (dereferenceable invariant load 4)

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]

  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec

  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0

  ; GFX8-LABEL: name: s_buffer_load_i32_glc
  ; GFX8-LABEL: name: s_buffer_load_i32_glc

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1, 0 :: (dereferenceable invariant load 4)
  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1, 0 :: (dereferenceable invariant load 4)

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]

  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec

  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0

  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 %soffset, i32 1)
  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 %soffset, i32 1)

  ret i32 %val
  ret i32 %val

}
}




define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_v2i32
  ; GFX6-LABEL: name: s_buffer_load_v2i32

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 8, align 4)
  ; GFX6:   [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 8, align 4)

  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0
  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0

  ; GFX6:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1

  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec

  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]

  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec

  ; GFX6:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
  ; GFX6:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1

  ; GFX7-LABEL: name: s_buffer_load_v2i32
  ; GFX7-LABEL: name: s_buffer_load_v2i32

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 8, align 4)
  ; GFX7:   [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 8, align 4)

  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0
  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0

  ; GFX7:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1

  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec

  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]

  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec

  ; GFX7:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
  ; GFX7:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1

  ; GFX8-LABEL: name: s_buffer_load_v2i32
  ; GFX8-LABEL: name: s_buffer_load_v2i32

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 8, align 4)
  ; GFX8:   [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 8, align 4)

  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0
  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0

  ; GFX8:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1

  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec

  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]

  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec

  ; GFX8:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
  ; GFX8:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1

  %val = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret <2 x i32> %val
  ret <2 x i32> %val

}
}




define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_v3i32
  ; GFX6-LABEL: name: s_buffer_load_v3i32

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 12, align 4)
  ; GFX6:   [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 12, align 4)

  ; GFX6:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
  ; GFX6:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF

  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11
  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11

  ; GFX6:   [[COPY5:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = COPY [[REG_SEQUENCE1]]
  ; GFX6:   [[COPY5:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = COPY [[REG_SEQUENCE1]]

  ; GFX6:   [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[COPY5]].sub0_sub1_sub2
  ; GFX6:   [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[COPY5]].sub0_sub1_sub2

  ; GFX6:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub0
  ; GFX6:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub0

  ; GFX6:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub1
  ; GFX6:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub1

  ; GFX6:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub2
  ; GFX6:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub2

Show All 9 Linesdefine amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2

  ; GFX7-LABEL: name: s_buffer_load_v3i32
  ; GFX7-LABEL: name: s_buffer_load_v3i32

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 12, align 4)
  ; GFX7:   [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 12, align 4)

  ; GFX7:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
  ; GFX7:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF

  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11
  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11

  ; GFX7:   [[COPY5:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = COPY [[REG_SEQUENCE1]]
  ; GFX7:   [[COPY5:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = COPY [[REG_SEQUENCE1]]

  ; GFX7:   [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[COPY5]].sub0_sub1_sub2
  ; GFX7:   [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[COPY5]].sub0_sub1_sub2

  ; GFX7:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub0
  ; GFX7:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub0

  ; GFX7:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub1
  ; GFX7:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub1

  ; GFX7:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub2
  ; GFX7:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub2

Show All 9 Linesdefine amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2

  ; GFX8-LABEL: name: s_buffer_load_v3i32
  ; GFX8-LABEL: name: s_buffer_load_v3i32

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 12, align 4)
  ; GFX8:   [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 12, align 4)

  ; GFX8:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
  ; GFX8:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF

  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11
  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11

  ; GFX8:   [[COPY5:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = COPY [[REG_SEQUENCE1]]
  ; GFX8:   [[COPY5:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = COPY [[REG_SEQUENCE1]]

  ; GFX8:   [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[COPY5]].sub0_sub1_sub2
  ; GFX8:   [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[COPY5]].sub0_sub1_sub2

  ; GFX8:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub0
  ; GFX8:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub0

  ; GFX8:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub1
  ; GFX8:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub1

  ; GFX8:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub2
  ; GFX8:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub2

Show All 14 Lines
define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_v8i32
  ; GFX6-LABEL: name: s_buffer_load_v8i32

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 32, align 4)
  ; GFX6:   [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 32, align 4)

  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0
  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0

  ; GFX6:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1

  ; GFX6:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2
  ; GFX6:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2

  ; GFX6:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3
  ; GFX6:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3

  ; GFX6:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4
  ; GFX6:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4

  ; GFX6:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5
  ; GFX6:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5

  ; GFX6:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6
  ; GFX6:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6

Show All 25 Linesdefine amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7

  ; GFX7-LABEL: name: s_buffer_load_v8i32
  ; GFX7-LABEL: name: s_buffer_load_v8i32

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 32, align 4)
  ; GFX7:   [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 32, align 4)

  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0
  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0

  ; GFX7:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1

  ; GFX7:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2
  ; GFX7:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2

  ; GFX7:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3
  ; GFX7:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3

  ; GFX7:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4
  ; GFX7:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4

  ; GFX7:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5
  ; GFX7:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5

  ; GFX7:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6
  ; GFX7:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6

Show All 25 Linesdefine amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7

  ; GFX8-LABEL: name: s_buffer_load_v8i32
  ; GFX8-LABEL: name: s_buffer_load_v8i32

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 32, align 4)
  ; GFX8:   [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 32, align 4)

  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0
  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0

  ; GFX8:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1

  ; GFX8:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2
  ; GFX8:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2

  ; GFX8:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3
  ; GFX8:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3

  ; GFX8:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4
  ; GFX8:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4

  ; GFX8:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5
  ; GFX8:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5

  ; GFX8:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6
  ; GFX8:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6

Show All 30 Lines
define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_v16i32
  ; GFX6-LABEL: name: s_buffer_load_v16i32

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 64, align 4)
  ; GFX6:   [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 64, align 4)

  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0
  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0

  ; GFX6:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1

  ; GFX6:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2
  ; GFX6:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2

  ; GFX6:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3
  ; GFX6:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3

  ; GFX6:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4
  ; GFX6:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4

  ; GFX6:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5
  ; GFX6:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5

  ; GFX6:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6
  ; GFX6:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6

▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesdefine amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15

  ; GFX7-LABEL: name: s_buffer_load_v16i32
  ; GFX7-LABEL: name: s_buffer_load_v16i32

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 64, align 4)
  ; GFX7:   [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 64, align 4)

  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0
  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0

  ; GFX7:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1

  ; GFX7:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2
  ; GFX7:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2

  ; GFX7:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3
  ; GFX7:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3

  ; GFX7:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4
  ; GFX7:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4

  ; GFX7:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5
  ; GFX7:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5

  ; GFX7:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6
  ; GFX7:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6

▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesdefine amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15

  ; GFX8-LABEL: name: s_buffer_load_v16i32
  ; GFX8-LABEL: name: s_buffer_load_v16i32

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 64, align 4)
  ; GFX8:   [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 64, align 4)

  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0
  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0

  ; GFX8:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1

  ; GFX8:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2
  ; GFX8:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2

  ; GFX8:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3
  ; GFX8:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3

  ; GFX8:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4
  ; GFX8:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4

  ; GFX8:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5
  ; GFX8:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5

  ; GFX8:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6
  ; GFX8:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6

▲ Show 20 Lines • Show All 930 Lines • ▼ Show 20 Lines
define amdgpu_ps float @s_buffer_load_f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_offset
  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_offset

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset
  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_offset
  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_offset

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps <2 x float> @s_buffer_load_v2f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps <2 x float> @s_buffer_load_v2f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_v2f32_vgpr_offset
  ; GFX6-LABEL: name: s_buffer_load_v2f32_vgpr_offset

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 8, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 8, align 4)

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0

  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1

  ; GFX6:   $vgpr0 = COPY [[COPY5]]
  ; GFX6:   $vgpr0 = COPY [[COPY5]]

  ; GFX6:   $vgpr1 = COPY [[COPY6]]
  ; GFX6:   $vgpr1 = COPY [[COPY6]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  ; GFX7-LABEL: name: s_buffer_load_v2f32_vgpr_offset
  ; GFX7-LABEL: name: s_buffer_load_v2f32_vgpr_offset

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 8, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 8, align 4)

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0

  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1

  ; GFX7:   $vgpr0 = COPY [[COPY5]]
  ; GFX7:   $vgpr0 = COPY [[COPY5]]

  ; GFX7:   $vgpr1 = COPY [[COPY6]]
  ; GFX7:   $vgpr1 = COPY [[COPY6]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  ; GFX8-LABEL: name: s_buffer_load_v2f32_vgpr_offset
  ; GFX8-LABEL: name: s_buffer_load_v2f32_vgpr_offset

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 8, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 8, align 4)

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0

  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1

  ; GFX8:   $vgpr0 = COPY [[COPY5]]
  ; GFX8:   $vgpr0 = COPY [[COPY5]]

  ; GFX8:   $vgpr1 = COPY [[COPY6]]
  ; GFX8:   $vgpr1 = COPY [[COPY6]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %val = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret <2 x float> %val
  ret <2 x float> %val

}
}




define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_v3f32_vgpr_offset
  ; GFX6-LABEL: name: s_buffer_load_v3f32_vgpr_offset

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
  ; GFX6:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF

  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_128 = COPY [[DEF]]
  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_128 = COPY [[DEF]]

  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_128 = COPY [[DEF]]
  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_128 = COPY [[DEF]]

  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[COPY5]], %subreg.sub4_sub5_sub6_sub7, [[COPY6]], %subreg.sub8_sub9_sub10_sub11
  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[COPY5]], %subreg.sub4_sub5_sub6_sub7, [[COPY6]], %subreg.sub8_sub9_sub10_sub11

  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2

  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0

  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1

  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2
  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2

  ; GFX6:   $vgpr0 = COPY [[COPY8]]
  ; GFX6:   $vgpr0 = COPY [[COPY8]]

  ; GFX6:   $vgpr1 = COPY [[COPY9]]
  ; GFX6:   $vgpr1 = COPY [[COPY9]]

  ; GFX6:   $vgpr2 = COPY [[COPY10]]
  ; GFX6:   $vgpr2 = COPY [[COPY10]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2

  ; GFX7-LABEL: name: s_buffer_load_v3f32_vgpr_offset
  ; GFX7-LABEL: name: s_buffer_load_v3f32_vgpr_offset

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
  ; GFX7:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF

  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_128 = COPY [[DEF]]
  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_128 = COPY [[DEF]]

  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_128 = COPY [[DEF]]
  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_128 = COPY [[DEF]]

  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[COPY5]], %subreg.sub4_sub5_sub6_sub7, [[COPY6]], %subreg.sub8_sub9_sub10_sub11
  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[COPY5]], %subreg.sub4_sub5_sub6_sub7, [[COPY6]], %subreg.sub8_sub9_sub10_sub11

  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2

  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0

  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1

  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2
  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2

  ; GFX7:   $vgpr0 = COPY [[COPY8]]
  ; GFX7:   $vgpr0 = COPY [[COPY8]]

  ; GFX7:   $vgpr1 = COPY [[COPY9]]
  ; GFX7:   $vgpr1 = COPY [[COPY9]]

  ; GFX7:   $vgpr2 = COPY [[COPY10]]
  ; GFX7:   $vgpr2 = COPY [[COPY10]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2

  ; GFX8-LABEL: name: s_buffer_load_v3f32_vgpr_offset
  ; GFX8-LABEL: name: s_buffer_load_v3f32_vgpr_offset

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
  ; GFX8:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF

  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_128 = COPY [[DEF]]
  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_128 = COPY [[DEF]]

  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_128 = COPY [[DEF]]
  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_128 = COPY [[DEF]]

  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[COPY5]], %subreg.sub4_sub5_sub6_sub7, [[COPY6]], %subreg.sub8_sub9_sub10_sub11
  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[COPY5]], %subreg.sub4_sub5_sub6_sub7, [[COPY6]], %subreg.sub8_sub9_sub10_sub11

  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2

  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0

Show All 10 Lines
define amdgpu_ps <4 x float> @s_buffer_load_v4f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps <4 x float> @s_buffer_load_v4f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_v4f32_vgpr_offset
  ; GFX6-LABEL: name: s_buffer_load_v4f32_vgpr_offset

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0

  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1

  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2

  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3
  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3

  ; GFX6:   $vgpr0 = COPY [[COPY5]]
  ; GFX6:   $vgpr0 = COPY [[COPY5]]

  ; GFX6:   $vgpr1 = COPY [[COPY6]]
  ; GFX6:   $vgpr1 = COPY [[COPY6]]

  ; GFX6:   $vgpr2 = COPY [[COPY7]]
  ; GFX6:   $vgpr2 = COPY [[COPY7]]

  ; GFX6:   $vgpr3 = COPY [[COPY8]]
  ; GFX6:   $vgpr3 = COPY [[COPY8]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX7-LABEL: name: s_buffer_load_v4f32_vgpr_offset
  ; GFX7-LABEL: name: s_buffer_load_v4f32_vgpr_offset

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0

  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1

  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2

  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3
  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3

  ; GFX7:   $vgpr0 = COPY [[COPY5]]
  ; GFX7:   $vgpr0 = COPY [[COPY5]]

  ; GFX7:   $vgpr1 = COPY [[COPY6]]
  ; GFX7:   $vgpr1 = COPY [[COPY6]]

  ; GFX7:   $vgpr2 = COPY [[COPY7]]
  ; GFX7:   $vgpr2 = COPY [[COPY7]]

  ; GFX7:   $vgpr3 = COPY [[COPY8]]
  ; GFX7:   $vgpr3 = COPY [[COPY8]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GFX8-LABEL: name: s_buffer_load_v4f32_vgpr_offset
  ; GFX8-LABEL: name: s_buffer_load_v4f32_vgpr_offset

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0

  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1

  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2

  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3
  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3

  ; GFX8:   $vgpr0 = COPY [[COPY5]]
  ; GFX8:   $vgpr0 = COPY [[COPY5]]

  ; GFX8:   $vgpr1 = COPY [[COPY6]]
  ; GFX8:   $vgpr1 = COPY [[COPY6]]

  ; GFX8:   $vgpr2 = COPY [[COPY7]]
  ; GFX8:   $vgpr2 = COPY [[COPY7]]

  ; GFX8:   $vgpr3 = COPY [[COPY8]]
  ; GFX8:   $vgpr3 = COPY [[COPY8]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  %val = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret <4 x float> %val
  ret <4 x float> %val

}
}




define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset
  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2

  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3

Show All 12 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset
  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2

  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3

Show All 12 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset
  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2

  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3

Show All 17 Lines
define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_v16f32_vgpr_offset
  ; GFX6-LABEL: name: s_buffer_load_v16f32_vgpr_offset

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)

  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

Show All 30 Linesdefine amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15

  ; GFX7-LABEL: name: s_buffer_load_v16f32_vgpr_offset
  ; GFX7-LABEL: name: s_buffer_load_v16f32_vgpr_offset

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)

  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

Show All 30 Linesdefine amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15

  ; GFX8-LABEL: name: s_buffer_load_v16f32_vgpr_offset
  ; GFX8-LABEL: name: s_buffer_load_v16f32_vgpr_offset

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)

  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

Show All 35 Lines
define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4092(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4092(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092
  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092
  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092
  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %soffset = add i32 %soffset.base, 4092
  %soffset = add i32 %soffset.base, 4092

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4095(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4095(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095
  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095
  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095
  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %soffset = add i32 %soffset.base, 4095
  %soffset = add i32 %soffset.base, 4095

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4096(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4096(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096
  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096
  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096
  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1

  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %soffset = add i32 %soffset.base, 4096
  %soffset = add i32 %soffset.base, 4096

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




; Make sure the base offset is added to each split load.
; Make sure the base offset is added to each split load.

define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064
  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2

  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3

Show All 12 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064
  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2

  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3

Show All 12 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064
  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2

  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3

Show All 19 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068
  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2

  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3

Show All 12 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068
  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2

  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3

Show All 12 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068
  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2

  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3

Show All 18 Lines
define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX6-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032
  ; GFX6-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)

  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

Show All 30 Linesdefine amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15

  ; GFX7-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032
  ; GFX7-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)

  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

Show All 30 Linesdefine amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15

  ; GFX8-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032
  ; GFX8-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)

  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

Show All 36 Lines
define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX6-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036
  ; GFX6-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4036
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4036

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)

  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)

  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

Show All 30 Linesdefine amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15

  ; GFX7-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036
  ; GFX7-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4036
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4036

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)

  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)

  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

Show All 30 Linesdefine amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15

  ; GFX8-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036
  ; GFX8-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)

  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)

  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0

  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1

Show All 37 Lines
define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %soffset) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %soffset) {

  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_rsrc
  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_rsrc

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX6: bb.2:
  ; GFX6: bb.2:

  ; GFX6:   successors: %bb.3, %bb.2
  ; GFX6:   successors: %bb.3, %bb.2

  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec

Show All 17 Linesdefine amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %soffset) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc
  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX7: bb.2:
  ; GFX7: bb.2:

  ; GFX7:   successors: %bb.3, %bb.2
  ; GFX7:   successors: %bb.3, %bb.2

  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec

Show All 17 Linesdefine amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %soffset) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_rsrc
  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_rsrc

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX8: bb.2:
  ; GFX8: bb.2:

  ; GFX8:   successors: %bb.3, %bb.2
  ; GFX8:   successors: %bb.3, %bb.2

  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec

Show All 23 Lines
define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %rsrc, i32 inreg %soffset.base) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092
  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX6: bb.2:
  ; GFX6: bb.2:

  ; GFX6:   successors: %bb.3, %bb.2
  ; GFX6:   successors: %bb.3, %bb.2

  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 15 Linesdefine amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092
  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX7: bb.2:
  ; GFX7: bb.2:

  ; GFX7:   successors: %bb.3, %bb.2
  ; GFX7:   successors: %bb.3, %bb.2

  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 15 Linesdefine amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092
  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX8: bb.2:
  ; GFX8: bb.2:

  ; GFX8:   successors: %bb.3, %bb.2
  ; GFX8:   successors: %bb.3, %bb.2

  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 22 Lines
define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096
  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; GFX6:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
  ; GFX6:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]

  ; GFX6:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX6: bb.2:
  ; GFX6: bb.2:

Show All 19 Linesdefine amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096
  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; GFX7:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
  ; GFX7:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]

  ; GFX7:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX7: bb.2:
  ; GFX7: bb.2:

Show All 19 Linesdefine amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096
  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; GFX8:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
  ; GFX8:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]

  ; GFX8:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX8: bb.2:
  ; GFX8: bb.2:

▲ Show 20 Lines • Show All 241 Lines • ▼ Show 20 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %rsrc, i32 inreg %soffset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064
  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX6: bb.2:
  ; GFX6: bb.2:

  ; GFX6:   successors: %bb.3, %bb.2
  ; GFX6:   successors: %bb.3, %bb.2

  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 32 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064
  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX7: bb.2:
  ; GFX7: bb.2:

  ; GFX7:   successors: %bb.3, %bb.2
  ; GFX7:   successors: %bb.3, %bb.2

  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 32 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064
  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX8: bb.2:
  ; GFX8: bb.2:

  ; GFX8:   successors: %bb.3, %bb.2
  ; GFX8:   successors: %bb.3, %bb.2

  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

Show All 40 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %rsrc, i32 inreg %soffset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068
  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068

  ; GFX6:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
  ; GFX6:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]

  ; GFX6:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX6: bb.2:
  ; GFX6: bb.2:

Show All 36 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068
  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068

  ; GFX7:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
  ; GFX7:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]

  ; GFX7:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX7: bb.2:
  ; GFX7: bb.2:

Show All 36 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068
  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068

  ; GFX8:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
  ; GFX8:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]

  ; GFX8:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX8: bb.2:
  ; GFX8: bb.2:

▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096
  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; GFX6:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
  ; GFX6:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc

  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]

  ; GFX6:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX6: bb.2:
  ; GFX6: bb.2:

Show All 36 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096
  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; GFX7:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
  ; GFX7:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc

  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]

  ; GFX7:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX7: bb.2:
  ; GFX7: bb.2:

Show All 36 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096
  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096

  ; GFX8:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
  ; GFX8:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc

  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]

  ; GFX8:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX8: bb.2:
  ; GFX8: bb.2:

▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000(<4 x i32> %rsrc, i32 %offset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000(<4 x i32> %rsrc, i32 %offset.base) {

  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX6:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000

  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX6: bb.2:
  ; GFX6: bb.2:

  ; GFX6:   successors: %bb.3, %bb.2
  ; GFX6:   successors: %bb.3, %bb.2

  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

Show All 33 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000(<4 x i32> %rsrc, i32 %offset.base) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX7:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000

  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX7: bb.2:
  ; GFX7: bb.2:

  ; GFX7:   successors: %bb.3, %bb.2
  ; GFX7:   successors: %bb.3, %bb.2

  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

Show All 33 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000(<4 x i32> %rsrc, i32 %offset.base) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX8:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4064
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4064

  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX8: bb.2:
  ; GFX8: bb.2:

  ; GFX8:   successors: %bb.3, %bb.2
  ; GFX8:   successors: %bb.3, %bb.2

  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

Show All 39 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076(<4 x i32> %rsrc, i32 %offset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076(<4 x i32> %rsrc, i32 %offset.base) {

  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX6:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4076
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4076

  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX6: bb.2:
  ; GFX6: bb.2:

  ; GFX6:   successors: %bb.3, %bb.2
  ; GFX6:   successors: %bb.3, %bb.2

  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

Show All 33 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076(<4 x i32> %rsrc, i32 %offset.base) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX7:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4076
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4076

  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX7: bb.2:
  ; GFX7: bb.2:

  ; GFX7:   successors: %bb.3, %bb.2
  ; GFX7:   successors: %bb.3, %bb.2

  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

Show All 33 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076(<4 x i32> %rsrc, i32 %offset.base) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX8:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 12
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 12

  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX8: bb.2:
  ; GFX8: bb.2:

  ; GFX8:   successors: %bb.3, %bb.2
  ; GFX8:   successors: %bb.3, %bb.2

  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

Show All 39 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080(<4 x i32> %rsrc, i32 %offset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080(<4 x i32> %rsrc, i32 %offset.base) {

  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX6:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4080
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4080

  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX6: bb.2:
  ; GFX6: bb.2:

  ; GFX6:   successors: %bb.3, %bb.2
  ; GFX6:   successors: %bb.3, %bb.2

  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

Show All 33 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080(<4 x i32> %rsrc, i32 %offset.base) {

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX7:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4080
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4080

  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX7: bb.2:
  ; GFX7: bb.2:

  ; GFX7:   successors: %bb.3, %bb.2
  ; GFX7:   successors: %bb.3, %bb.2

  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

Show All 33 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080(<4 x i32> %rsrc, i32 %offset.base) {

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GFX8:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GFX8: bb.2:
  ; GFX8: bb.2:

  ; GFX8:   successors: %bb.3, %bb.2
  ; GFX8:   successors: %bb.3, %bb.2

  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec

  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec

▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Lines
define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {

  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr
  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr
  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr
  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %offset = add i32 %offset.v, %offset.s
  %offset = add i32 %offset.v, %offset.s

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {

  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr
  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr
  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr
  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %offset = add i32 %offset.s, %offset.v
  %offset = add i32 %offset.s, %offset.v

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr_imm(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr_imm(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {

  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm
  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; GFX6:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
  ; GFX6:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm
  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; GFX7:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
  ; GFX7:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm
  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; GFX8:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
  ; GFX8:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %offset.base = add i32 %offset.v, %offset.s
  %offset.base = add i32 %offset.v, %offset.s

  %offset = add i32 %offset.base, 1024
  %offset = add i32 %offset.base, 1024

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr_imm(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr_imm(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {

  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm
  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; GFX6:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY4]], 0, implicit $exec
  ; GFX6:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY4]], 0, implicit $exec

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm
  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; GFX7:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY4]], 0, implicit $exec
  ; GFX7:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY4]], 0, implicit $exec

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm
  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; GFX8:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY4]], 0, implicit $exec
  ; GFX8:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY4]], 0, implicit $exec

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %offset.base = add i32 %offset.s, %offset.v
  %offset.base = add i32 %offset.s, %offset.v

  %offset = add i32 %offset.base, 1024
  %offset = add i32 %offset.base, 1024

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)

  ret float %val
  ret float %val

}
}




; TODO: Ideally this would be reassociated to fold.
; TODO: Ideally this would be reassociated to fold.

define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_sgpr_vgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_sgpr_vgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {

  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr
  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024

  ; GFX6:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
  ; GFX6:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc

  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr
  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024

  ; GFX7:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
  ; GFX7:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc

  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr
  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024

  ; GFX8:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
  ; GFX8:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc

  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %offset.base = add i32 %offset.s, 1024
  %offset.base = add i32 %offset.s, 1024

  %offset = add i32 %offset.base, %offset.v
  %offset = add i32 %offset.base, %offset.v

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_vgpr_sgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_vgpr_sgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {

  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr
  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr

  ; GFX6: bb.1 (%ir-block.0):
  ; GFX6: bb.1 (%ir-block.0):

  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024

  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; GFX6:   %10:vgpr_32, dead %16:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
  ; GFX6:   %10:vgpr_32, dead %16:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec

  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %10, [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %10, [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr
  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr

  ; GFX7: bb.1 (%ir-block.0):
  ; GFX7: bb.1 (%ir-block.0):

  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024

  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; GFX7:   %10:vgpr_32, dead %16:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
  ; GFX7:   %10:vgpr_32, dead %16:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec

  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %10, [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %10, [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr
  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr

  ; GFX8: bb.1 (%ir-block.0):
  ; GFX8: bb.1 (%ir-block.0):

  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024

  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; GFX8:   %10:vgpr_32, dead %16:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
  ; GFX8:   %10:vgpr_32, dead %16:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec

  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %10, [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %10, [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]

  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %offset.base = add i32 %offset.v, 1024
  %offset.base = add i32 %offset.v, 1024

  %offset = add i32 %offset.base, %offset.s
  %offset = add i32 %offset.base, %offset.s

Show All 30 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps float @struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_ADD_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_ADD_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_BOTHEN_RTN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_BOTHEN_RTN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %ret = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i32 %ret to float
  %cast = bitcast i32 %ret to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @struct_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_ADD_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_ADD_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_BOTHEN_RTN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_BOTHEN_RTN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %ret = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i32 %ret to float
  %cast = bitcast i32 %ret to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps <2 x float> @struct_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i64 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x float> @struct_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i64 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 8 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 8 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN]].sub0
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN]].sub0

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN]].sub1
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN]].sub1

  ; CHECK:   $vgpr0 = COPY [[COPY9]]
  ; CHECK:   $vgpr0 = COPY [[COPY9]]

  ; CHECK:   $vgpr1 = COPY [[COPY10]]
  ; CHECK:   $vgpr1 = COPY [[COPY10]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %ret = call i64 @llvm.amdgcn.struct.buffer.atomic.add.i64(i64 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i64 @llvm.amdgcn.struct.buffer.atomic.add.i64(i64 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i64 %ret to <2 x float>
  %cast = bitcast i64 %ret to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}




define amdgpu_ps void @struct_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i64 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i64 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 8 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 8 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call i64 @llvm.amdgcn.struct.buffer.atomic.add.i64(i64 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i64 @llvm.amdgcn.struct.buffer.atomic.add.i64(i64 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; All register operands need legalization
; All register operands need legalization

define amdgpu_ps float @struct_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps float @struct_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 32 Linesdefine amdgpu_ps void @struct_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 29 Linesdefine amdgpu_ps float @struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(i32 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
  ; CHECK-LABEL: name: struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_ADD_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 1, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_ADD_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 1, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_BOTHEN_RTN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_BOTHEN_RTN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %ret = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 2)
  %ret = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 2)

  %cast = bitcast i32 %ret to float
  %cast = bitcast i32 %ret to float

  ret float %cast
  ret float %cast

}
}




declare i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg) #0
declare i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg) #0

declare i64 @llvm.amdgcn.struct.buffer.atomic.add.i64(i64, <4 x i32>, i32, i32, i32, i32 immarg) #0
declare i64 @llvm.amdgcn.struct.buffer.atomic.add.i64(i64, <4 x i32>, i32, i32, i32, i32 immarg) #0




attributes #0 = { nounwind }
attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s







; Natural mapping
; Natural mapping

define amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN]].sub0
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN]].sub0

  ; CHECK:   $vgpr0 = COPY [[COPY9]]
  ; CHECK:   $vgpr0 = COPY [[COPY9]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %ret = call i32 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i32 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i32 %ret to float
  %cast = bitcast i32 %ret to float

  ret float %cast
  ret float %cast

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps void @struct_buffer_atomic_cmpswap_noret_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_atomic_cmpswap_noret_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_cmpswap_noret_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_cmpswap_noret_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 0, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN]].sub0
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN]].sub0

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call i32 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i32 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; All operands need legalization
; All operands need legalization

define amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, i32 inreg %cmp, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, i32 inreg %cmp, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]

  ; CHECK:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; CHECK:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; CHECK:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
  ; CHECK:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]

  ; CHECK:   [[COPY13:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY13:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY14:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY14:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

Show All 36 Linesdefine amdgpu_ps void @struct_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, i32 inreg %cmp, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]

  ; CHECK:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; CHECK:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; CHECK:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
  ; CHECK:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]

  ; CHECK:   [[COPY13:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY13:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY14:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY14:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

Show All 32 Linesdefine amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 4095, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 4095, 1, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN]].sub0
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN]].sub0

  ; CHECK:   $vgpr0 = COPY [[COPY9]]
  ; CHECK:   $vgpr0 = COPY [[COPY9]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %voffset = add i32 %voffset.base, 4095
  %voffset = add i32 %voffset.base, 4095

  %ret = call i32 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %ret = call i32 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i32 %ret to float
  %cast = bitcast i32 %ret to float

  ret float %cast
  ret float %cast

}
}




declare i32 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i32(i32, i32, <4 x i32>, i32, i32, i32, i32 immarg) #0
declare i32 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i32(i32, i32, <4 x i32>, i32, i32, i32, i32 immarg) #0

declare i64 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i64(i64, i64, <4 x i32>, i32, i32, i32, i32 immarg) #0
declare i64 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i64(i64, i64, <4 x i32>, i32, i32, i32, i32 immarg) #0




attributes #0 = { nounwind }
attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   BUFFER_ATOMIC_ADD_F32_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_ADD_F32_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_plus4095__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_plus4095__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_plus4095__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_plus4095__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   BUFFER_ATOMIC_ADD_F32_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 4095, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_ADD_F32_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 4095, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %voffset.add = add i32 %voffset, 4095
  %voffset.add = add i32 %voffset, 4095

  %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0)
  %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__4095_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__4095_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__4095_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__4095_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   BUFFER_ATOMIC_ADD_F32_IDXEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_ADD_F32_IDXEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 4095, i32 %soffset, i32 0)
  %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 4095, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; Natural mapping, no voffset
; Natural mapping, no voffset

define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   BUFFER_ATOMIC_ADD_F32_IDXEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_ADD_F32_IDXEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 %soffset, i32 0)
  %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; All register operands need legalization
; All register operands need legalization

define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset(float inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset(float inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 30 Linesdefine amdgpu_ps void @struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__0_voffset__vgpr_soffset(float inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 %soffset) {

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec

Show All 27 Linesdefine amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   BUFFER_ATOMIC_ADD_F32_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_ADD_F32_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 2)
  %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 2)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset_slc
  ; CHECK-LABEL: name: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset_slc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   BUFFER_ATOMIC_ADD_F32_IDXEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_ADD_F32_IDXEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 %soffset, i32 2)
  %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 %soffset, i32 2)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   BUFFER_ATOMIC_PK_ADD_F16_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_PK_ADD_F16_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %ret = call <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   BUFFER_ATOMIC_PK_ADD_F16_IDXEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_ATOMIC_PK_ADD_F16_IDXEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %ret = call <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 %soffset, i32 0)
  %ret = call <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 %soffset, i32 0)

  ret void
  ret void

}
}




declare float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i32, i32 immarg) #0
declare float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i32, i32 immarg) #0

declare <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32 immarg) #0
declare <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32 immarg) #0




attributes #0 = { nounwind }
attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s




define amdgpu_ps half @struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN]]
  ; UNPACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_BOTHEN]]
  ; PACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_BOTHEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call half @llvm.amdgcn.struct.buffer.load.format.f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call half @llvm.amdgcn.struct.buffer.load.format.f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret half %val
  ret half %val

}
}




define amdgpu_ps <2 x half> @struct_buffer_load_format_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x half> @struct_buffer_load_format_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: struct_buffer_load_format_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: struct_buffer_load_format_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN]].sub0
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN]].sub0

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN]].sub1
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN]].sub1

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY7]], [[COPY9]], implicit $exec
  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY7]], [[COPY9]], implicit $exec

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY8]], [[COPY10]], implicit $exec
  ; UNPACKED:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY8]], [[COPY10]], implicit $exec

  ; UNPACKED:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
  ; UNPACKED:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]

  ; UNPACKED:   [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY11]], [[V_AND_B32_e64_1]], implicit $exec
  ; UNPACKED:   [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY11]], [[V_AND_B32_e64_1]], implicit $exec

  ; UNPACKED:   [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_AND_B32_e64_]], [[V_LSHLREV_B32_e64_]], implicit $exec
  ; UNPACKED:   [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_AND_B32_e64_]], [[V_LSHLREV_B32_e64_]], implicit $exec

  ; UNPACKED:   $vgpr0 = COPY [[V_OR_B32_e64_]]
  ; UNPACKED:   $vgpr0 = COPY [[V_OR_B32_e64_]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: struct_buffer_load_format_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: struct_buffer_load_format_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_XY_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_XY_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_XY_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_XY_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_BOTHEN]]
  ; PACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_BOTHEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call <2 x half> @llvm.amdgcn.struct.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call <2 x half> @llvm.amdgcn.struct.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret <2 x half> %val
  ret <2 x half> %val

}
}




; FIXME: Crashes
; FIXME: Crashes

; define amdgpu_ps <3 x half> @struct_buffer_load_format_v3f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
; define amdgpu_ps <3 x half> @struct_buffer_load_format_v3f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

;   %val = call <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
;   %val = call <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

;   ret <3 x half> %val
;   ret <3 x half> %val

; }
; }




define amdgpu_ps <4 x half> @struct_buffer_load_format_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <4 x half> @struct_buffer_load_format_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: struct_buffer_load_format_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: struct_buffer_load_format_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub0
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub0

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub1
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub1

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub2
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub2

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub3
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535

  ; UNPACKED:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

Show All 16 Linesdefine amdgpu_ps <4 x half> @struct_buffer_load_format_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  ; PACKED-LABEL: name: struct_buffer_load_format_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: struct_buffer_load_format_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub0
  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub0

  ; PACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub1
  ; PACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub1

  ; PACKED:   $vgpr0 = COPY [[COPY7]]
  ; PACKED:   $vgpr0 = COPY [[COPY7]]

  ; PACKED:   $vgpr1 = COPY [[COPY8]]
  ; PACKED:   $vgpr1 = COPY [[COPY8]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %val = call <4 x half> @llvm.amdgcn.struct.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call <4 x half> @llvm.amdgcn.struct.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret <4 x half> %val
  ret <4 x half> %val

}
}




; Waterfall for rsrc and soffset, copy for voffset
; Waterfall for rsrc and soffset, copy for voffset

define amdgpu_ps <4 x half> @struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps <4 x half> @struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; UNPACKED-LABEL: name: struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
  ; UNPACKED-LABEL: name: struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; UNPACKED: bb.2:
  ; UNPACKED: bb.2:

  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec

▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesdefine amdgpu_ps <4 x half> @struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; PACKED-LABEL: name: struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
  ; PACKED-LABEL: name: struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; PACKED:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; PACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; PACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; PACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec

Show All 30 Lines
define amdgpu_ps half @struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffsset_add_4095(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps half @struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffsset_add_4095(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset.base, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffsset_add_4095
  ; UNPACKED-LABEL: name: struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffsset_add_4095

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource" + 4095, align 1, addrspace 4)
  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource" + 4095, align 1, addrspace 4)

  ; UNPACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN]]
  ; UNPACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffsset_add_4095
  ; PACKED-LABEL: name: struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffsset_add_4095

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource" + 4095, align 1, addrspace 4)
  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource" + 4095, align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_BOTHEN]]
  ; PACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_BOTHEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %voffset = add i32 %voffset.base, 4095
  %voffset = add i32 %voffset.base, 4095

  %val = call half @llvm.amdgcn.struct.buffer.load.format.f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call half @llvm.amdgcn.struct.buffer.load.format.f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret half %val
  ret half %val

}
}




define amdgpu_ps half @struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN]]
  ; UNPACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; PACKED-LABEL: name: struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[BUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_BOTHEN]]
  ; PACKED:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_BOTHEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call i16 @llvm.amdgcn.struct.buffer.load.format.i16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call i16 @llvm.amdgcn.struct.buffer.load.format.i16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  %fval = bitcast i16 %val to half
  %fval = bitcast i16 %val to half

  ret half %fval
  ret half %fval

}
}




declare half @llvm.amdgcn.struct.buffer.load.format.f16(<4 x i32>, i32, i32, i32, i32 immarg) #0
declare half @llvm.amdgcn.struct.buffer.load.format.f16(<4 x i32>, i32, i32, i32, i32 immarg) #0

declare <2 x half> @llvm.amdgcn.struct.buffer.load.format.v2f16(<4 x i32>, i32, i32, i32, i32 immarg) #0
declare <2 x half> @llvm.amdgcn.struct.buffer.load.format.v2f16(<4 x i32>, i32, i32, i32, i32 immarg) #0

declare <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32>, i32, i32, i32, i32 immarg) #0
declare <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32>, i32, i32, i32, i32 immarg) #0

declare <4 x half> @llvm.amdgcn.struct.buffer.load.format.v4f16(<4 x i32>, i32, i32, i32, i32 immarg) #0
declare <4 x half> @llvm.amdgcn.struct.buffer.load.format.v4f16(<4 x i32>, i32, i32, i32, i32 immarg) #0

declare i16 @llvm.amdgcn.struct.buffer.load.format.i16(<4 x i32>, i32, i32, i32, i32 immarg) #0
declare i16 @llvm.amdgcn.struct.buffer.load.format.i16(<4 x i32>, i32, i32, i32, i32 immarg) #0




attributes #0 = { nounwind readonly }
attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s

; XUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; XUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




define amdgpu_ps float @struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps <2 x float> @struct_buffer_load_format_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x float> @struct_buffer_load_format_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_format_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_format_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_FORMAT_XY_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_XY_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_FORMAT_XY_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_XY_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XY_BOTHEN]].sub0
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XY_BOTHEN]].sub0

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XY_BOTHEN]].sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XY_BOTHEN]].sub1

  ; CHECK:   $vgpr0 = COPY [[COPY7]]
  ; CHECK:   $vgpr0 = COPY [[COPY7]]

  ; CHECK:   $vgpr1 = COPY [[COPY8]]
  ; CHECK:   $vgpr1 = COPY [[COPY8]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %val = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret <2 x float> %val
  ret <2 x float> %val

}
}




define amdgpu_ps <3 x float> @struct_buffer_load_format_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <3 x float> @struct_buffer_load_format_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_format_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_format_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_FORMAT_XYZ_BOTHEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_FORMAT_XYZ_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_FORMAT_XYZ_BOTHEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_FORMAT_XYZ_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub0
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub0

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub1

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub2
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub2

  ; CHECK:   $vgpr0 = COPY [[COPY7]]
  ; CHECK:   $vgpr0 = COPY [[COPY7]]

  ; CHECK:   $vgpr1 = COPY [[COPY8]]
  ; CHECK:   $vgpr1 = COPY [[COPY8]]

  ; CHECK:   $vgpr2 = COPY [[COPY9]]
  ; CHECK:   $vgpr2 = COPY [[COPY9]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2

  %val = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret <3 x float> %val
  ret <3 x float> %val

}
}




define amdgpu_ps <4 x float> @struct_buffer_load_format_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <4 x float> @struct_buffer_load_format_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_format_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_format_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub0
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub0

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub1

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub2
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub2

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub3
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub3

  ; CHECK:   $vgpr0 = COPY [[COPY7]]
  ; CHECK:   $vgpr0 = COPY [[COPY7]]

  ; CHECK:   $vgpr1 = COPY [[COPY8]]
  ; CHECK:   $vgpr1 = COPY [[COPY8]]

Show All 9 Linesdefine amdgpu_ps <4 x float> @struct_buffer_load_format_v4f32__vpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_format_v4f32__vpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_format_v4f32__vpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec

Show All 34 Lines
define amdgpu_ps float @struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffsset_add_4095(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffsset_add_4095(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffsset_add_4095
  ; CHECK-LABEL: name: struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffsset_add_4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %voffset = add i32 %voffset.base, 4095
  %voffset = add i32 %voffset.base, 4095

  %val = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @struct_buffer_load_format_i32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load_format_i32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_format_i32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_format_i32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  %fval = bitcast i32 %val to float
  %fval = bitcast i32 %val to float

  ret float %fval
  ret float %fval

}
}




declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32 immarg) #0
declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32 immarg) #0

declare <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32>, i32, i32, i32, i32 immarg) #0
declare <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32>, i32, i32, i32, i32 immarg) #0

declare <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32, i32 immarg) #0
declare <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32, i32 immarg) #0

declare <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32, i32 immarg) #0
declare <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32, i32 immarg) #0

declare i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32>, i32, i32, i32, i32 immarg) #0
declare i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32>, i32, i32, i32, i32 immarg) #0




attributes #0 = { nounwind readonly }
attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps <2 x float> @struct_buffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x float> @struct_buffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_DWORDX2_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORDX2_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_BOTHEN]].sub0
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_BOTHEN]].sub0

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_BOTHEN]].sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_BOTHEN]].sub1

  ; CHECK:   $vgpr0 = COPY [[COPY7]]
  ; CHECK:   $vgpr0 = COPY [[COPY7]]

  ; CHECK:   $vgpr1 = COPY [[COPY8]]
  ; CHECK:   $vgpr1 = COPY [[COPY8]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %val = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret <2 x float> %val
  ret <2 x float> %val

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps <3 x float> @struct_buffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <3 x float> @struct_buffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_DWORDX3_BOTHEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORDX3_BOTHEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_BOTHEN]].sub0
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_BOTHEN]].sub0

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_BOTHEN]].sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_BOTHEN]].sub1

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_BOTHEN]].sub2
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_BOTHEN]].sub2

  ; CHECK:   $vgpr0 = COPY [[COPY7]]
  ; CHECK:   $vgpr0 = COPY [[COPY7]]

  ; CHECK:   $vgpr1 = COPY [[COPY8]]
  ; CHECK:   $vgpr1 = COPY [[COPY8]]

  ; CHECK:   $vgpr2 = COPY [[COPY9]]
  ; CHECK:   $vgpr2 = COPY [[COPY9]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2

  %val = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret <3 x float> %val
  ret <3 x float> %val

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps <4 x float> @struct_buffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <4 x float> @struct_buffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_DWORDX4_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORDX4_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_BOTHEN]].sub0
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_BOTHEN]].sub0

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_BOTHEN]].sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_BOTHEN]].sub1

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_BOTHEN]].sub2
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_BOTHEN]].sub2

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_BOTHEN]].sub3
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_BOTHEN]].sub3

  ; CHECK:   $vgpr0 = COPY [[COPY7]]
  ; CHECK:   $vgpr0 = COPY [[COPY7]]

  ; CHECK:   $vgpr1 = COPY [[COPY8]]
  ; CHECK:   $vgpr1 = COPY [[COPY8]]

  ; CHECK:   $vgpr2 = COPY [[COPY9]]
  ; CHECK:   $vgpr2 = COPY [[COPY9]]

  ; CHECK:   $vgpr3 = COPY [[COPY10]]
  ; CHECK:   $vgpr3 = COPY [[COPY10]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  %val = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret <4 x float> %val
  ret <4 x float> %val

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0
  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095
  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %voffset = add i32 %voffset.base, 4095
  %voffset = add i32 %voffset.base, 4095

  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_soffset_64(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset) {
define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_soffset_64(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset) {

  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_soffset_64
  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_soffset_64

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 64
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 64

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 64, i32 0)
  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 64, i32 0)

  ret float %val
  ret float %val

}
}




; Need to legalize all reg operands
; Need to legalize all reg operands

define amdgpu_ps float @struct_buffer_load_f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps float @struct_buffer_load_f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec

Show All 27 Lines
define amdgpu_ps float @struct_buffer_load_i8_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load_i8_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_i8_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_i8_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_UBYTE_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "BufferResource", addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_UBYTE_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "BufferResource", addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  %ext = zext i8 %val to i32
  %ext = zext i8 %val to i32

  %cast = bitcast i32 %ext to float
  %cast = bitcast i32 %ext to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @struct_buffer_load_i8_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load_i8_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_i8_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_i8_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_UBYTE_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "BufferResource", addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_UBYTE_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "BufferResource", addrspace 4)

  ; CHECK:   [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_UBYTE_BOTHEN]], 0, 8, implicit $exec
  ; CHECK:   [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_UBYTE_BOTHEN]], 0, 8, implicit $exec

  ; CHECK:   $vgpr0 = COPY [[V_BFE_I32_e64_]]
  ; CHECK:   $vgpr0 = COPY [[V_BFE_I32_e64_]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  %ext = sext i8 %val to i32
  %ext = sext i8 %val to i32

  %cast = bitcast i32 %ext to float
  %cast = bitcast i32 %ext to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @struct_buffer_load_i16_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load_i16_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_i16_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_i16_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_USHORT_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_USHORT_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_USHORT_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_USHORT_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  %ext = zext i16 %val to i32
  %ext = zext i16 %val to i32

  %cast = bitcast i32 %ext to float
  %cast = bitcast i32 %ext to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @struct_buffer_load_i16_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load_i16_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_i16_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_i16_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_USHORT_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_USHORT_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_USHORT_BOTHEN]], 0, 16, implicit $exec
  ; CHECK:   [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_USHORT_BOTHEN]], 0, 16, implicit $exec

  ; CHECK:   $vgpr0 = COPY [[V_BFE_I32_e64_]]
  ; CHECK:   $vgpr0 = COPY [[V_BFE_I32_e64_]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  %ext = sext i16 %val to i32
  %ext = sext i16 %val to i32

  %cast = bitcast i32 %ext to float
  %cast = bitcast i32 %ext to float

  ret float %cast
  ret float %cast

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps half @struct_buffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @struct_buffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_USHORT_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_USHORT_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_USHORT_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_USHORT_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret half %val
  ret half %val

}
}




; Natural mapping
; Natural mapping

define amdgpu_ps <2 x half> @struct_buffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x half> @struct_buffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret <2 x half> %val
  ret <2 x half> %val

}
}




; FIXME: Crashes
; FIXME: Crashes

; define amdgpu_ps <3 x half> @struct_buffer_load_v3f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
; define amdgpu_ps <3 x half> @struct_buffer_load_v3f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

;   %val = call <3 x half> @llvm.amdgcn.struct.buffer.load.v3f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
;   %val = call <3 x half> @llvm.amdgcn.struct.buffer.load.v3f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

;   ret <3 x half> %val
;   ret <3 x half> %val

; }
; }




; Natural mapping
; Natural mapping

define amdgpu_ps <4 x half> @struct_buffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <4 x half> @struct_buffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_DWORDX2_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORDX2_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_BOTHEN]].sub0
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_BOTHEN]].sub0

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_BOTHEN]].sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_BOTHEN]].sub1

  ; CHECK:   $vgpr0 = COPY [[COPY7]]
  ; CHECK:   $vgpr0 = COPY [[COPY7]]

  ; CHECK:   $vgpr1 = COPY [[COPY8]]
  ; CHECK:   $vgpr1 = COPY [[COPY8]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %val = call <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret <4 x half> %val
  ret <4 x half> %val

}
}




; Natural mapping + glc
; Natural mapping + glc

define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc
  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 1)
  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 1)

  ret float %val
  ret float %val

}
}




Show All 12 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s




define amdgpu_ps void @struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(half %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(half %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; PACKED:   BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_format_v2f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_format_v2f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: struct_buffer_store_format_v2f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: struct_buffer_store_format_v2f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY]], implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1

  ; UNPACKED:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact [[REG_SEQUENCE1]], [[REG_SEQUENCE2]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact [[REG_SEQUENCE1]], [[REG_SEQUENCE2]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: struct_buffer_store_format_v2f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: struct_buffer_store_format_v2f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; FIXME:
; FIXME:

; define amdgpu_ps void @struct_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
; define amdgpu_ps void @struct_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

;   call void @llvm.amdgcn.struct.buffer.store.format.v3f16(<3 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
;   call void @llvm.amdgcn.struct.buffer.store.format.v3f16(<3 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

;   ret void
;   ret void

; }
; }




define amdgpu_ps void @struct_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: struct_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: struct_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY]], implicit $exec

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY10]], [[COPY1]], implicit $exec
  ; UNPACKED:   [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY10]], [[COPY1]], implicit $exec

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY1]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY1]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3

  ; UNPACKED:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact [[REG_SEQUENCE1]], [[REG_SEQUENCE2]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact [[REG_SEQUENCE1]], [[REG_SEQUENCE2]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: struct_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: struct_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1

  ; PACKED:   BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.format.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.format.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(half inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps void @struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(half inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; UNPACKED-LABEL: name: struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
  ; UNPACKED-LABEL: name: struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; UNPACKED:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; UNPACKED:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; UNPACKED:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; UNPACKED:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; UNPACKED: bb.2:
  ; UNPACKED: bb.2:

  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 24 Linesdefine amdgpu_ps void @struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(half inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; PACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; PACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; PACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; PACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; PACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; PACKED:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 28 Linesdefine amdgpu_ps void @struct_buffer_store_format_i16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(i16 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; UNPACKED-LABEL: name: struct_buffer_store_format_i16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: struct_buffer_store_format_i16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   S_ENDPGM 0
  ; UNPACKED:   S_ENDPGM 0

  ; PACKED-LABEL: name: struct_buffer_store_format_i16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: struct_buffer_store_format_i16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; PACKED:   BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   S_ENDPGM 0
  ; PACKED:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.format.i16(i16 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.format.i16(i16 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




declare void @llvm.amdgcn.struct.buffer.store.format.f16(half, <4 x i32>, i32, i32, i32, i32 immarg)
declare void @llvm.amdgcn.struct.buffer.store.format.f16(half, <4 x i32>, i32, i32, i32, i32 immarg)

declare void @llvm.amdgcn.struct.buffer.store.format.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32 immarg)
declare void @llvm.amdgcn.struct.buffer.store.format.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32 immarg)

declare void @llvm.amdgcn.struct.buffer.store.format.v3f16(<3 x half>, <4 x i32>, i32, i32, i32, i32 immarg)
declare void @llvm.amdgcn.struct.buffer.store.format.v3f16(<3 x half>, <4 x i32>, i32, i32, i32, i32 immarg)

declare void @llvm.amdgcn.struct.buffer.store.format.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32 immarg)
declare void @llvm.amdgcn.struct.buffer.store.format.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32 immarg)

declare void @llvm.amdgcn.struct.buffer.store.format.i16(i16, <4 x i32>, i32, i32, i32, i32 immarg)
declare void @llvm.amdgcn.struct.buffer.store.format.i16(i16, <4 x i32>, i32, i32, i32, i32 immarg)

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s | FileCheck %s




define amdgpu_ps void @struct_buffer_store_format_f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_format_f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_format_f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_format_f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_FORMAT_X_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_X_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_format_v2f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<2 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_format_v2f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<2 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_format_v2f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_format_v2f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_FORMAT_XY_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_XY_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_format_v3f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_format_v3f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_format_v3f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_format_v3f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.format.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.format.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_format_v4f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_format_v4f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_format_v4f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_format_v4f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY10]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY10]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_format_f32__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(float inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps void @struct_buffer_store_format_f32__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(float inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_format_f32__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_format_f32__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 28 Linesdefine amdgpu_ps void @struct_buffer_store_format_i32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_format_i32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_format_i32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_FORMAT_X_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_FORMAT_X_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.format.i32(i32 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.format.i32(i32 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




declare void @llvm.amdgcn.struct.buffer.store.format.f32(float, <4 x i32>, i32, i32, i32, i32 immarg)
declare void @llvm.amdgcn.struct.buffer.store.format.f32(float, <4 x i32>, i32, i32, i32, i32 immarg)

declare void @llvm.amdgcn.struct.buffer.store.format.v2f32(<2 x float>, <4 x i32>, i32, i32, i32, i32 immarg)
declare void @llvm.amdgcn.struct.buffer.store.format.v2f32(<2 x float>, <4 x i32>, i32, i32, i32, i32 immarg)

declare void @llvm.amdgcn.struct.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i32, i32 immarg)
declare void @llvm.amdgcn.struct.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i32, i32 immarg)

declare void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32 immarg)
declare void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32 immarg)

declare void @llvm.amdgcn.struct.buffer.store.format.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare void @llvm.amdgcn.struct.buffer.store.format.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps void @struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_DWORD_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_v2f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<2 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_v2f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<2 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_v2f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_v2f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_DWORDX2_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORDX2_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_v3f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_v3f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_v3f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_v3f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_DWORDX3_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORDX3_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_v4f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_v4f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_v4f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_v4f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5

  ; CHECK:   [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_DWORDX4_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY10]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORDX4_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY10]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_v4f32_vgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x float> inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps void @struct_buffer_store_v4f32_vgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x float> inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_v4f32_vgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_v4f32_vgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr7
  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr7

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3

  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE]]
  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE]]

  ; CHECK:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
  ; CHECK:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]

  ; CHECK:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
  ; CHECK:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]

  ; CHECK:   [[COPY14:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
  ; CHECK:   [[COPY14:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1

  ; CHECK:   [[COPY15:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
  ; CHECK:   [[COPY15:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 28 Linesdefine amdgpu_ps void @struct_buffer_store_i8_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_i8_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_i8_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_BYTE_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 1 into custom "BufferResource", addrspace 4)
  ; CHECK:   BUFFER_STORE_BYTE_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 1 into custom "BufferResource", addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %val.trunc = trunc i32 %val to i8
  %val.trunc = trunc i32 %val to i8

  call void @llvm.amdgcn.struct.buffer.store.i8(i8 %val.trunc, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.i8(i8 %val.trunc, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_i16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_i16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_i16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_i16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_SHORT_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_SHORT_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  %val.trunc = trunc i32 %val to i16
  %val.trunc = trunc i32 %val to i16

  call void @llvm.amdgcn.struct.buffer.store.i16(i16 %val.trunc, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.i16(i16 %val.trunc, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc
  ; CHECK-LABEL: name: struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_DWORD_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 1)
  call void @llvm.amdgcn.struct.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 1)

  ret void
  ret void

}
}




define amdgpu_ps void @struct_buffer_store_v2f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_v2f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_v2f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_v2f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_DWORD_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORD_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; FIXME:
; FIXME:

; define amdgpu_ps void @struct_buffer_store_v3f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
; define amdgpu_ps void @struct_buffer_store_v3f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

;   call void @llvm.amdgcn.struct.buffer.store.v3f16(<3 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
;   call void @llvm.amdgcn.struct.buffer.store.v3f16(<3 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

;   ret void
;   ret void

; }
; }




define amdgpu_ps void @struct_buffer_store_v4f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store_v4f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store_v4f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store_v4f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1

  ; CHECK:   BUFFER_STORE_DWORDX2_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   BUFFER_STORE_DWORDX2_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




declare void @llvm.amdgcn.struct.buffer.store.i8(i8, <4 x i32>, i32, i32, i32, i32 immarg)
declare void @llvm.amdgcn.struct.buffer.store.i8(i8, <4 x i32>, i32, i32, i32, i32 immarg)

Show All 11 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=PACKED %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=UNPACKED %s




define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; PACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]]
  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; UNPACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN]]
  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret half %val
  ret half %val

}
}




define amdgpu_ps <2 x half> @struct_tbuffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x half> @struct_tbuffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; PACKED-LABEL: name: struct_tbuffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: struct_tbuffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN]]
  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; UNPACKED-LABEL: name: struct_tbuffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: struct_tbuffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN]].sub0
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN]].sub0

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN]].sub1
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN]].sub1

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY7]], [[COPY9]], implicit $exec
  ; UNPACKED:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY7]], [[COPY9]], implicit $exec

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

Show All 17 Lines
define amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; PACKED-LABEL: name: struct_tbuffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; PACKED-LABEL: name: struct_tbuffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub0
  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub0

  ; PACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub1
  ; PACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub1

  ; PACKED:   $vgpr0 = COPY [[COPY7]]
  ; PACKED:   $vgpr0 = COPY [[COPY7]]

  ; PACKED:   $vgpr1 = COPY [[COPY8]]
  ; PACKED:   $vgpr1 = COPY [[COPY8]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  ; UNPACKED-LABEL: name: struct_tbuffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; UNPACKED-LABEL: name: struct_tbuffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub0
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub0

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub1
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub1

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub2
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub2

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub3
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535

  ; UNPACKED:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

Show All 21 Lines
define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; PACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0
  ; PACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; PACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1

  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]]
  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; UNPACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0
  ; UNPACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; UNPACKED:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1

  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)
  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource", align 1, addrspace 4)

  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN]]
  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32> %rsrc, i32 0, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32> %rsrc, i32 0, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret half %val
  ret half %val

}
}




define amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; PACKED-LABEL: name: struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
  ; PACKED-LABEL: name: struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   successors: %bb.2(0x80000000)
  ; PACKED:   successors: %bb.2(0x80000000)

  ; PACKED:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; PACKED:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; PACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; PACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; PACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; PACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; PACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; PACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; PACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; PACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; PACKED:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; PACKED:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; PACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; PACKED: bb.2:
  ; PACKED: bb.2:

  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; PACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
  ; PACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec

Show All 26 Linesdefine amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; UNPACKED-LABEL: name: struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
  ; UNPACKED-LABEL: name: struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   successors: %bb.2(0x80000000)
  ; UNPACKED:   successors: %bb.2(0x80000000)

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; UNPACKED:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; UNPACKED:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; UNPACKED:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; UNPACKED:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; UNPACKED:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; UNPACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; UNPACKED:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; UNPACKED:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; UNPACKED:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; UNPACKED:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; UNPACKED: bb.2:
  ; UNPACKED: bb.2:

  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; UNPACKED:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
  ; UNPACKED:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec

▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset.base, i32 inreg %soffset) {

  ; PACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095
  ; PACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095

  ; PACKED: bb.1 (%ir-block.0):
  ; PACKED: bb.1 (%ir-block.0):

  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; PACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; PACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; PACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; PACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; PACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; PACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; PACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; PACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; PACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource" + 4095, align 1, addrspace 4)
  ; PACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource" + 4095, align 1, addrspace 4)

  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]]
  ; PACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]]

  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; UNPACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095
  ; UNPACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095

  ; UNPACKED: bb.1 (%ir-block.0):
  ; UNPACKED: bb.1 (%ir-block.0):

  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; UNPACKED:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; UNPACKED:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; UNPACKED:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; UNPACKED:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; UNPACKED:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; UNPACKED:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; UNPACKED:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; UNPACKED:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; UNPACKED:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource" + 4095, align 1, addrspace 4)
  ; UNPACKED:   [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "BufferResource" + 4095, align 1, addrspace 4)

  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN]]
  ; UNPACKED:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN]]

  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %voffset = add i32 %voffset.base, 4095
  %voffset = add i32 %voffset.base, 4095

  %val = call half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret half %val
  ret half %val

}
}




declare half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0
declare half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0

declare <2 x half> @llvm.amdgcn.struct.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0
declare <2 x half> @llvm.amdgcn.struct.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0

declare <3 x half> @llvm.amdgcn.struct.tbuffer.load.v3f16(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0
declare <3 x half> @llvm.amdgcn.struct.tbuffer.load.v3f16(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0

declare <4 x half> @llvm.amdgcn.struct.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0
declare <4 x half> @llvm.amdgcn.struct.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0




attributes #0 = { nounwind readonly }
attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps <2 x float> @struct_tbuffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <2 x float> @struct_tbuffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_tbuffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_tbuffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XY_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_XY_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XY_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_XY_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_BOTHEN]].sub0
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_BOTHEN]].sub0

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_BOTHEN]].sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_BOTHEN]].sub1

  ; CHECK:   $vgpr0 = COPY [[COPY7]]
  ; CHECK:   $vgpr0 = COPY [[COPY7]]

  ; CHECK:   $vgpr1 = COPY [[COPY8]]
  ; CHECK:   $vgpr1 = COPY [[COPY8]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %val = call <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret <2 x float> %val
  ret <2 x float> %val

}
}




define amdgpu_ps <3 x float> @struct_tbuffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <3 x float> @struct_tbuffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_tbuffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_tbuffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN:%[0-9]+]]:vreg_96 = TBUFFER_LOAD_FORMAT_XYZ_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN:%[0-9]+]]:vreg_96 = TBUFFER_LOAD_FORMAT_XYZ_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub0
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub0

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub1

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub2
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub2

  ; CHECK:   $vgpr0 = COPY [[COPY7]]
  ; CHECK:   $vgpr0 = COPY [[COPY7]]

  ; CHECK:   $vgpr1 = COPY [[COPY8]]
  ; CHECK:   $vgpr1 = COPY [[COPY8]]

  ; CHECK:   $vgpr2 = COPY [[COPY9]]
  ; CHECK:   $vgpr2 = COPY [[COPY9]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2

  %val = call <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret <3 x float> %val
  ret <3 x float> %val

}
}




define amdgpu_ps <4 x float> @struct_tbuffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps <4 x float> @struct_tbuffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_tbuffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_tbuffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub0
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub0

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub1
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub1

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub2
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub2

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub3
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub3

  ; CHECK:   $vgpr0 = COPY [[COPY7]]
  ; CHECK:   $vgpr0 = COPY [[COPY7]]

  ; CHECK:   $vgpr1 = COPY [[COPY8]]
  ; CHECK:   $vgpr1 = COPY [[COPY8]]

  ; CHECK:   $vgpr2 = COPY [[COPY9]]
  ; CHECK:   $vgpr2 = COPY [[COPY9]]

  ; CHECK:   $vgpr3 = COPY [[COPY10]]
  ; CHECK:   $vgpr3 = COPY [[COPY10]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  %val = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret <4 x float> %val
  ret <4 x float> %val

}
}




define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0
  ; CHECK-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps <4 x float> @struct_tbuffer_load_v4f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
define amdgpu_ps <4 x float> @struct_tbuffer_load_v4f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: struct_tbuffer_load_v4f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: struct_tbuffer_load_v4f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec

Show All 34 Lines
define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset.base, i32 inreg %soffset) {
define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095
  ; CHECK-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1

  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4095, align 1, addrspace 4)
  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "BufferResource" + 4095, align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]]
  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %voffset = add i32 %voffset.base, 4095
  %voffset = add i32 %voffset.base, 4095

  %val = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)
  %val = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0)

  ret float %val
  ret float %val

}
}




declare float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0
declare float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0

declare <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0
declare <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0

declare <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0
declare <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0

declare <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0
declare <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #0




attributes #0 = { nounwind readonly }
attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
Show First 20 Lines • Show All 479 Lines • ▼ Show 20 Lines; GFX9-NEXT:    ; return to shader part epilog

  ret half %cast
  ret half %cast

}
}




define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) {
define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) {

; GFX6-LABEL: v_lshr_v2i16:
; GFX6-LABEL: v_lshr_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    s_mov_b32 s4, 0xffff
; GFX6-NEXT:    s_mov_b32 s4, 0xffff

; GFX6-NEXT:    v_and_b32_e32 v2, s4, v2
; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1

; GFX6-NEXT:    v_lshrrev_b32_e32 v0, v2, v0

; GFX6-NEXT:    v_and_b32_e32 v2, s4, v3

; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v0, v1, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v3, v2

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_lshr_v2i16:
; GFX8-LABEL: v_lshr_v2i16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_lshrrev_b16_e32 v2, v1, v0
; GFX8-NEXT:    v_lshrrev_b16_e32 v2, v1, v0

; GFX8-NEXT:    v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT:    v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1

; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0

; GFX8-NEXT:    s_setpc_b64 s[30:31]
; GFX8-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX9-LABEL: v_lshr_v2i16:
; GFX9-LABEL: v_lshr_v2i16:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX9-NEXT:    v_pk_lshrrev_b16 v0, v1, v0
; GFX9-NEXT:    v_pk_lshrrev_b16 v0, v1, v0

; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %result = lshr <2 x i16> %value, %amount
  %result = lshr <2 x i16> %value, %amount

  ret <2 x i16> %result
  ret <2 x i16> %result

}
}




define <2 x i16> @v_lshr_v2i16_15(<2 x i16> %value) {
define <2 x i16> @v_lshr_v2i16_15(<2 x i16> %value) {

; GFX6-LABEL: v_lshr_v2i16_15:
; GFX6-LABEL: v_lshr_v2i16_15:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    s_mov_b32 s4, 0xffff
; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v0

; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 15, v1

; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 31, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 15, v0
; GFX6-NEXT:    v_mov_b32_e32 v0, v2

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 15, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_lshr_v2i16_15:
; GFX8-LABEL: v_lshr_v2i16_15:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_mov_b32_e32 v2, 15
; GFX8-NEXT:    v_mov_b32_e32 v2, 15

; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 15, v0
; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 15, v0

; GFX8-NEXT:    v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT:    v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1

; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0

; GFX8-NEXT:    s_setpc_b64 s[30:31]
; GFX8-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX9-LABEL: v_lshr_v2i16_15:
; GFX9-LABEL: v_lshr_v2i16_15:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX9-NEXT:    v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1]
; GFX9-NEXT:    v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1]

; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %result = lshr <2 x i16> %value, <i16 15, i16 15>
  %result = lshr <2 x i16> %value, <i16 15, i16 15>

  ret <2 x i16> %result
  ret <2 x i16> %result

}
}




define amdgpu_ps i32 @s_lshr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {
define amdgpu_ps i32 @s_lshr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {

; GFX6-LABEL: s_lshr_v2i16:
; GFX6-LABEL: s_lshr_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_mov_b32 s4, 0xffff
; GFX6-NEXT:    s_mov_b32 s4, 0xffff

; GFX6-NEXT:    s_and_b32 s2, s2, s4
; GFX6-NEXT:    s_lshr_b32 s2, s0, 16

; GFX6-NEXT:    s_and_b32 s0, s0, s4
; GFX6-NEXT:    s_lshr_b32 s3, s1, 16

; GFX6-NEXT:    s_lshr_b32 s0, s0, s2

; GFX6-NEXT:    s_and_b32 s2, s3, s4

; GFX6-NEXT:    s_and_b32 s1, s1, s4
; GFX6-NEXT:    s_and_b32 s1, s1, s4

; GFX6-NEXT:    s_lshr_b32 s1, s1, s2
; GFX6-NEXT:    s_and_b32 s0, s0, s4

; GFX6-NEXT:    s_lshr_b32 s0, s0, s1

; GFX6-NEXT:    s_lshr_b32 s1, s2, s3

; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
; GFX6-NEXT:    s_lshl_b32 s1, s1, 16

; GFX6-NEXT:    s_or_b32 s0, s0, s1
; GFX6-NEXT:    s_or_b32 s0, s0, s1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: s_lshr_v2i16:
; GFX8-LABEL: s_lshr_v2i16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_mov_b32 s3, 0xffff
; GFX8-NEXT:    s_mov_b32 s3, 0xffff

; GFX8-NEXT:    s_lshr_b32 s2, s0, 16
; GFX8-NEXT:    s_lshr_b32 s2, s0, 16

Show All 21 Lines; GFX9-NEXT:    ; return to shader part epilog

  %result = lshr <2 x i16> %value, %amount
  %result = lshr <2 x i16> %value, %amount

  %cast = bitcast <2 x i16> %result to i32
  %cast = bitcast <2 x i16> %result to i32

  ret i32 %cast
  ret i32 %cast

}
}




define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {
define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {

; GFX6-LABEL: lshr_v2i16_sv:
; GFX6-LABEL: lshr_v2i16_sv:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    s_mov_b32 s2, 0xffff
; GFX6-NEXT:    s_mov_b32 s2, 0xffff

; GFX6-NEXT:    v_lshr_b32_e32 v1, s1, v1

; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0
; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0

; GFX6-NEXT:    s_and_b32 s0, s0, s2
; GFX6-NEXT:    s_and_b32 s0, s0, s2

; GFX6-NEXT:    v_lshr_b32_e32 v0, s0, v0
; GFX6-NEXT:    v_lshr_b32_e32 v0, s0, v0

; GFX6-NEXT:    v_and_b32_e32 v1, s2, v1

; GFX6-NEXT:    s_and_b32 s0, s1, s2

; GFX6-NEXT:    v_lshr_b32_e32 v1, s0, v1

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: lshr_v2i16_sv:
; GFX8-LABEL: lshr_v2i16_sv:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_lshr_b32 s1, s0, 16
; GFX8-NEXT:    s_lshr_b32 s1, s0, 16

; GFX8-NEXT:    v_mov_b32_e32 v2, s1
; GFX8-NEXT:    v_mov_b32_e32 v2, s1

Show All 9 Lines; GFX9-NEXT:    ; return to shader part epilog

  %result = lshr <2 x i16> %value, %amount
  %result = lshr <2 x i16> %value, %amount

  %cast = bitcast <2 x i16> %result to float
  %cast = bitcast <2 x i16> %result to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {
define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {

; GFX6-LABEL: lshr_v2i16_vs:
; GFX6-LABEL: lshr_v2i16_vs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    s_mov_b32 s2, 0xffff
; GFX6-NEXT:    s_mov_b32 s2, 0xffff

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, s1, v1

; GFX6-NEXT:    s_and_b32 s0, s0, s2
; GFX6-NEXT:    s_and_b32 s0, s0, s2

; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0
; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v0, s0, v0
; GFX6-NEXT:    v_lshrrev_b32_e32 v0, s0, v0

; GFX6-NEXT:    s_and_b32 s0, s1, s2

; GFX6-NEXT:    v_and_b32_e32 v1, s2, v1

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, s0, v1

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: lshr_v2i16_vs:
; GFX8-LABEL: lshr_v2i16_vs:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_lshr_b32 s1, s0, 16
; GFX8-NEXT:    s_lshr_b32 s1, s0, 16

; GFX8-NEXT:    v_mov_b32_e32 v2, s1
; GFX8-NEXT:    v_mov_b32_e32 v2, s1

▲ Show 20 Lines • Show All 571 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
Show First 20 Lines • Show All 279 Lines • ▼ Show 20 Lines; GCN-NEXT:    ; return to shader part epilog

  %zext = zext i16 %or to i32
  %zext = zext i16 %or to i32

  %cast.zext = bitcast i32 %zext to float
  %cast.zext = bitcast i32 %zext to float

  ret float %cast.zext
  ret float %cast.zext

}
}




define amdgpu_ps i32 @s_orn2_v2i16(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {
define amdgpu_ps i32 @s_orn2_v2i16(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {

; GFX6-LABEL: s_orn2_v2i16:
; GFX6-LABEL: s_orn2_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_mov_b32 s1, 0xffff
; GFX6-NEXT:    s_xor_b32 s0, s3, -1

; GFX6-NEXT:    s_and_b32 s2, s2, s1
; GFX6-NEXT:    s_or_b32 s0, s2, s0

; GFX6-NEXT:    s_lshl_b32 s0, s3, 16

; GFX6-NEXT:    s_or_b32 s0, s0, s2

; GFX6-NEXT:    s_lshl_b32 s2, s5, 16

; GFX6-NEXT:    s_and_b32 s1, s4, s1

; GFX6-NEXT:    s_or_b32 s1, s2, s1

; GFX6-NEXT:    s_xor_b32 s1, s1, -1

; GFX6-NEXT:    s_or_b32 s0, s0, s1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX9-LABEL: s_orn2_v2i16:
; GFX9-LABEL: s_orn2_v2i16:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_orn2_b32 s0, s2, s3
; GFX9-NEXT:    s_orn2_b32 s0, s2, s3

; GFX9-NEXT:    ; return to shader part epilog
; GFX9-NEXT:    ; return to shader part epilog

  %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
  %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>

  %or = or <2 x i16> %src0, %not.src1
  %or = or <2 x i16> %src0, %not.src1

  %cast = bitcast <2 x i16> %or to i32
  %cast = bitcast <2 x i16> %or to i32

  ret i32 %cast
  ret i32 %cast

}
}




define amdgpu_ps i32 @s_orn2_v2i16_commute(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {
define amdgpu_ps i32 @s_orn2_v2i16_commute(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {

; GFX6-LABEL: s_orn2_v2i16_commute:
; GFX6-LABEL: s_orn2_v2i16_commute:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_mov_b32 s1, 0xffff
; GFX6-NEXT:    s_xor_b32 s0, s3, -1

; GFX6-NEXT:    s_and_b32 s2, s2, s1

; GFX6-NEXT:    s_lshl_b32 s0, s3, 16

; GFX6-NEXT:    s_or_b32 s0, s0, s2
; GFX6-NEXT:    s_or_b32 s0, s0, s2

; GFX6-NEXT:    s_lshl_b32 s2, s5, 16

; GFX6-NEXT:    s_and_b32 s1, s4, s1

; GFX6-NEXT:    s_or_b32 s1, s2, s1

; GFX6-NEXT:    s_xor_b32 s1, s1, -1

; GFX6-NEXT:    s_or_b32 s0, s1, s0

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX9-LABEL: s_orn2_v2i16_commute:
; GFX9-LABEL: s_orn2_v2i16_commute:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_orn2_b32 s0, s2, s3
; GFX9-NEXT:    s_orn2_b32 s0, s2, s3

; GFX9-NEXT:    ; return to shader part epilog
; GFX9-NEXT:    ; return to shader part epilog

  %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
  %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>

  %or = or <2 x i16> %not.src1, %src0
  %or = or <2 x i16> %not.src1, %src0

  %cast = bitcast <2 x i16> %or to i32
  %cast = bitcast <2 x i16> %or to i32

  ret i32 %cast
  ret i32 %cast

}
}




define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {
define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {

; GFX6-LABEL: s_orn2_v2i16_multi_use:
; GFX6-LABEL: s_orn2_v2i16_multi_use:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_mov_b32 s1, 0xffff
; GFX6-NEXT:    s_xor_b32 s1, s3, -1

; GFX6-NEXT:    s_and_b32 s2, s2, s1
; GFX6-NEXT:    s_or_b32 s0, s2, s1

; GFX6-NEXT:    s_lshl_b32 s0, s3, 16

; GFX6-NEXT:    s_or_b32 s0, s0, s2

; GFX6-NEXT:    s_lshl_b32 s2, s5, 16

; GFX6-NEXT:    s_and_b32 s1, s4, s1

; GFX6-NEXT:    s_or_b32 s1, s2, s1

; GFX6-NEXT:    s_xor_b32 s1, s1, -1

; GFX6-NEXT:    s_or_b32 s0, s0, s1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX9-LABEL: s_orn2_v2i16_multi_use:
; GFX9-LABEL: s_orn2_v2i16_multi_use:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_xor_b32 s1, s3, -1
; GFX9-NEXT:    s_xor_b32 s1, s3, -1

; GFX9-NEXT:    s_orn2_b32 s0, s2, s3
; GFX9-NEXT:    s_orn2_b32 s0, s2, s3

; GFX9-NEXT:    ; return to shader part epilog
; GFX9-NEXT:    ; return to shader part epilog

  %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
  %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>

  %or = or <2 x i16> %src0, %not.src1
  %or = or <2 x i16> %src0, %not.src1




  %cast.0 = bitcast <2 x i16> %or to i32
  %cast.0 = bitcast <2 x i16> %or to i32

  %cast.1 = bitcast <2 x i16> %not.src1 to i32
  %cast.1 = bitcast <2 x i16> %not.src1 to i32

  %insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
  %insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0

  %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
  %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1

  ret { i32, i32 } %insert.1
  ret { i32, i32 } %insert.1

}
}




define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_foldable_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1, <2 x i16> inreg %src2) {
define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_foldable_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1, <2 x i16> inreg %src2) {

; GFX6-LABEL: s_orn2_v2i16_multi_foldable_use:
; GFX6-LABEL: s_orn2_v2i16_multi_foldable_use:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_mov_b32 s1, 0xffff
; GFX6-NEXT:    s_xor_b32 s1, s4, -1

; GFX6-NEXT:    s_lshl_b32 s0, s3, 16
; GFX6-NEXT:    s_or_b32 s0, s2, s1

; GFX6-NEXT:    s_and_b32 s2, s2, s1

; GFX6-NEXT:    s_or_b32 s0, s0, s2

; GFX6-NEXT:    s_and_b32 s3, s4, s1

; GFX6-NEXT:    s_lshl_b32 s2, s5, 16

; GFX6-NEXT:    s_or_b32 s2, s2, s3

; GFX6-NEXT:    s_lshl_b32 s3, s7, 16

; GFX6-NEXT:    s_and_b32 s1, s6, s1

; GFX6-NEXT:    s_or_b32 s1, s3, s1
; GFX6-NEXT:    s_or_b32 s1, s3, s1

; GFX6-NEXT:    s_xor_b32 s1, s1, -1

; GFX6-NEXT:    s_or_b32 s0, s0, s1

; GFX6-NEXT:    s_or_b32 s1, s2, s1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX9-LABEL: s_orn2_v2i16_multi_foldable_use:
; GFX9-LABEL: s_orn2_v2i16_multi_foldable_use:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_orn2_b32 s0, s2, s4
; GFX9-NEXT:    s_orn2_b32 s0, s2, s4

; GFX9-NEXT:    s_orn2_b32 s1, s3, s4
; GFX9-NEXT:    s_orn2_b32 s1, s3, s4

; GFX9-NEXT:    ; return to shader part epilog
; GFX9-NEXT:    ; return to shader part epilog

  %not.src2 = xor <2 x i16> %src2, <i16 -1, i16 -1>
  %not.src2 = xor <2 x i16> %src2, <i16 -1, i16 -1>

  %or0 = or <2 x i16> %src0, %not.src2
  %or0 = or <2 x i16> %src0, %not.src2

  %or1 = or <2 x i16> %src1, %not.src2
  %or1 = or <2 x i16> %src1, %not.src2




  %cast.0 = bitcast <2 x i16> %or0 to i32
  %cast.0 = bitcast <2 x i16> %or0 to i32

  %cast.1 = bitcast <2 x i16> %or1 to i32
  %cast.1 = bitcast <2 x i16> %or1 to i32

  %insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
  %insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0

  %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
  %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1

  ret { i32, i32 } %insert.1
  ret { i32, i32 } %insert.1

}
}




define <2 x i16> @v_orn2_v2i16(<2 x i16> %src0, <2 x i16> %src1) {
define <2 x i16> @v_orn2_v2i16(<2 x i16> %src0, <2 x i16> %src1) {

; GFX6-LABEL: v_orn2_v2i16:
; GFX6-LABEL: v_orn2_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_mov_b32_e32 v4, 0xffff

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_and_b32_e32 v0, v0, v4

; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v3

; GFX6-NEXT:    v_and_b32_e32 v2, v2, v4

; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2

; GFX6-NEXT:    v_xor_b32_e32 v1, -1, v1
; GFX6-NEXT:    v_xor_b32_e32 v1, -1, v1

; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX9-LABEL: v_orn2_v2i16:
; GFX9-LABEL: v_orn2_v2i16:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

▲ Show 20 Lines • Show All 236 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
Show All 9 Linesdefine amdgpu_ps void @load_1d_vgpr_vaddr__sgpr_srsrc(<8 x i32> inreg %rsrc, i32 %s) {

  ; FAST:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; FAST:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; FAST:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; FAST:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; FAST:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; FAST:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; FAST:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; FAST:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; FAST:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; FAST:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; FAST:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; FAST:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; FAST:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
  ; FAST:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8

  ; FAST:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
  ; FAST:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9

  ; FAST:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; FAST:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY8]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; FAST:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY8]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; FAST:   [[COPY9:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
  ; FAST:   [[COPY9:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)

  ; FAST:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[COPY9]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
  ; FAST:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[COPY9]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)

  ; FAST:   S_ENDPGM 0
  ; FAST:   S_ENDPGM 0

  ; GREEDY-LABEL: name: load_1d_vgpr_vaddr__sgpr_srsrc
  ; GREEDY-LABEL: name: load_1d_vgpr_vaddr__sgpr_srsrc

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; GREEDY:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
  ; GREEDY:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8

  ; GREEDY:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
  ; GREEDY:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9

  ; GREEDY:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY8]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; GREEDY:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY8]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; GREEDY:   [[COPY9:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
  ; GREEDY:   [[COPY9:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)

  ; GREEDY:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[COPY9]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
  ; GREEDY:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[COPY9]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)

  ; GREEDY:   S_ENDPGM 0
  ; GREEDY:   S_ENDPGM 0

  %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)

  store <4 x float> %v, <4 x float> addrspace(1)* undef
  store <4 x float> %v, <4 x float> addrspace(1)* undef

  ret void
  ret void

}
}




; Copy needed for VGPR argument
; Copy needed for VGPR argument

define amdgpu_ps void @load_1d_sgpr_vaddr__sgpr_srsrc(<8 x i32> inreg %rsrc, i32 inreg %s) {
define amdgpu_ps void @load_1d_sgpr_vaddr__sgpr_srsrc(<8 x i32> inreg %rsrc, i32 inreg %s) {

  ; FAST-LABEL: name: load_1d_sgpr_vaddr__sgpr_srsrc
  ; FAST-LABEL: name: load_1d_sgpr_vaddr__sgpr_srsrc

  ; FAST: bb.1 (%ir-block.0):
  ; FAST: bb.1 (%ir-block.0):

  ; FAST:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10
  ; FAST:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10

  ; FAST:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; FAST:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; FAST:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; FAST:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; FAST:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; FAST:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; FAST:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; FAST:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; FAST:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; FAST:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; FAST:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; FAST:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; FAST:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
  ; FAST:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8

  ; FAST:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
  ; FAST:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9

  ; FAST:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr10

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr10

  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; FAST:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY8]](s32)
  ; FAST:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY8]](s32)

  ; FAST:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; FAST:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; FAST:   [[COPY10:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
  ; FAST:   [[COPY10:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)

  ; FAST:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[COPY10]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
  ; FAST:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[COPY10]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)

  ; FAST:   S_ENDPGM 0
  ; FAST:   S_ENDPGM 0

  ; GREEDY-LABEL: name: load_1d_sgpr_vaddr__sgpr_srsrc
  ; GREEDY-LABEL: name: load_1d_sgpr_vaddr__sgpr_srsrc

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; GREEDY:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
  ; GREEDY:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8

  ; GREEDY:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
  ; GREEDY:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9

  ; GREEDY:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr10

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr10

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY8]](s32)
  ; GREEDY:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY8]](s32)

  ; GREEDY:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; GREEDY:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; GREEDY:   [[COPY10:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
  ; GREEDY:   [[COPY10:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)

  ; GREEDY:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[COPY10]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
  ; GREEDY:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[COPY10]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)

  ; GREEDY:   S_ENDPGM 0
  ; GREEDY:   S_ENDPGM 0

  %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)

  store <4 x float> %v, <4 x float> addrspace(1)* undef
  store <4 x float> %v, <4 x float> addrspace(1)* undef

Show All 9 Linesdefine amdgpu_ps void @load_1d_vgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 %s) {

  ; FAST:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; FAST:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; FAST:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; FAST:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; FAST:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; FAST:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; FAST:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; FAST:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; FAST:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; FAST:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; FAST:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
  ; FAST:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5

  ; FAST:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
  ; FAST:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6

  ; FAST:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7
  ; FAST:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7

  ; FAST:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr8

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr8

  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; FAST:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; FAST:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; FAST:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; FAST:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; FAST:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
  ; FAST:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)

  ; FAST:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; FAST:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; FAST: bb.2:
  ; FAST: bb.2:

  ; FAST:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; FAST:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; FAST:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF2]], %bb.1, %19, %bb.2
  ; FAST:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF2]], %bb.1, %19, %bb.2

Show All 36 Linesdefine amdgpu_ps void @load_1d_vgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 %s) {

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6

  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7
  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7

  ; GREEDY:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr8

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr8

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; GREEDY:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GREEDY: bb.2:
  ; GREEDY: bb.2:

  ; GREEDY:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; GREEDY:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; GREEDY:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF2]], %bb.1, %19, %bb.2
  ; GREEDY:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF2]], %bb.1, %19, %bb.2

▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesdefine amdgpu_ps void @load_1d_sgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 inreg %s) {

  ; FAST:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; FAST:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; FAST:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; FAST:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; FAST:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; FAST:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; FAST:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; FAST:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; FAST:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; FAST:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; FAST:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
  ; FAST:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5

  ; FAST:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
  ; FAST:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6

  ; FAST:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7
  ; FAST:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7

  ; FAST:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; FAST:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY8]](s32)
  ; FAST:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY8]](s32)

  ; FAST:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; FAST:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; FAST:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; FAST:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; FAST:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
  ; FAST:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)

  ; FAST:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; FAST:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; FAST: bb.2:
  ; FAST: bb.2:

  ; FAST:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; FAST:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 37 Linesdefine amdgpu_ps void @load_1d_sgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 inreg %s) {

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6

  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7
  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7

  ; GREEDY:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY8]](s32)
  ; GREEDY:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY8]](s32)

  ; GREEDY:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; GREEDY:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GREEDY: bb.2:
  ; GREEDY: bb.2:

  ; GREEDY:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; GREEDY:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
Show All 9 Linesdefine amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__sgpr_samp(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {

  ; FAST:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; FAST:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; FAST:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; FAST:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; FAST:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; FAST:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; FAST:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; FAST:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; FAST:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; FAST:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; FAST:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; FAST:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; FAST:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
  ; FAST:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8

  ; FAST:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
  ; FAST:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr10
  ; FAST:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr10

  ; FAST:   [[COPY9:%[0-9]+]]:sgpr(s32) = COPY $sgpr11
  ; FAST:   [[COPY9:%[0-9]+]]:sgpr(s32) = COPY $sgpr11

  ; FAST:   [[COPY10:%[0-9]+]]:sgpr(s32) = COPY $sgpr12
  ; FAST:   [[COPY10:%[0-9]+]]:sgpr(s32) = COPY $sgpr12

  ; FAST:   [[COPY11:%[0-9]+]]:sgpr(s32) = COPY $sgpr13
  ; FAST:   [[COPY11:%[0-9]+]]:sgpr(s32) = COPY $sgpr13

  ; FAST:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; FAST:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; FAST:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; FAST:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; FAST:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; FAST:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
  ; FAST:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)

  ; FAST:   S_ENDPGM 0
  ; FAST:   S_ENDPGM 0

  ; GREEDY-LABEL: name: sample_1d_vgpr_vaddr__sgpr_rsrc__sgpr_samp
  ; GREEDY-LABEL: name: sample_1d_vgpr_vaddr__sgpr_rsrc__sgpr_samp

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; GREEDY:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
  ; GREEDY:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8

  ; GREEDY:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
  ; GREEDY:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr10
  ; GREEDY:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr10

  ; GREEDY:   [[COPY9:%[0-9]+]]:sgpr(s32) = COPY $sgpr11
  ; GREEDY:   [[COPY9:%[0-9]+]]:sgpr(s32) = COPY $sgpr11

  ; GREEDY:   [[COPY10:%[0-9]+]]:sgpr(s32) = COPY $sgpr12
  ; GREEDY:   [[COPY10:%[0-9]+]]:sgpr(s32) = COPY $sgpr12

  ; GREEDY:   [[COPY11:%[0-9]+]]:sgpr(s32) = COPY $sgpr13
  ; GREEDY:   [[COPY11:%[0-9]+]]:sgpr(s32) = COPY $sgpr13

  ; GREEDY:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GREEDY:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GREEDY:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; GREEDY:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; GREEDY:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
  ; GREEDY:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)

  ; GREEDY:   S_ENDPGM 0
  ; GREEDY:   S_ENDPGM 0

  %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
  %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)

  store <4 x float> %v, <4 x float> addrspace(1)* undef
  store <4 x float> %v, <4 x float> addrspace(1)* undef

  ret void
  ret void

}
}




; Copy required for VGPR input
; Copy required for VGPR input

define amdgpu_ps void @sample_1d_sgpr_vaddr__sgpr_rsrc__sgpr_samp(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float inreg %s) {
define amdgpu_ps void @sample_1d_sgpr_vaddr__sgpr_rsrc__sgpr_samp(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float inreg %s) {

  ; FAST-LABEL: name: sample_1d_sgpr_vaddr__sgpr_rsrc__sgpr_samp
  ; FAST-LABEL: name: sample_1d_sgpr_vaddr__sgpr_rsrc__sgpr_samp

  ; FAST: bb.1 (%ir-block.0):
  ; FAST: bb.1 (%ir-block.0):

  ; FAST:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14
  ; FAST:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14

  ; FAST:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; FAST:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; FAST:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; FAST:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; FAST:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; FAST:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; FAST:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; FAST:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; FAST:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; FAST:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; FAST:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; FAST:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; FAST:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
  ; FAST:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8

  ; FAST:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
  ; FAST:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr10
  ; FAST:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr10

  ; FAST:   [[COPY9:%[0-9]+]]:sgpr(s32) = COPY $sgpr11
  ; FAST:   [[COPY9:%[0-9]+]]:sgpr(s32) = COPY $sgpr11

  ; FAST:   [[COPY10:%[0-9]+]]:sgpr(s32) = COPY $sgpr12
  ; FAST:   [[COPY10:%[0-9]+]]:sgpr(s32) = COPY $sgpr12

  ; FAST:   [[COPY11:%[0-9]+]]:sgpr(s32) = COPY $sgpr13
  ; FAST:   [[COPY11:%[0-9]+]]:sgpr(s32) = COPY $sgpr13

  ; FAST:   [[COPY12:%[0-9]+]]:sgpr(s32) = COPY $sgpr14

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; FAST:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; FAST:   [[COPY12:%[0-9]+]]:sgpr(s32) = COPY $sgpr14

  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; FAST:   [[COPY13:%[0-9]+]]:vgpr(s32) = COPY [[COPY12]](s32)
  ; FAST:   [[COPY13:%[0-9]+]]:vgpr(s32) = COPY [[COPY12]](s32)

  ; FAST:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY13]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; FAST:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY13]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; FAST:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
  ; FAST:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)

  ; FAST:   S_ENDPGM 0
  ; FAST:   S_ENDPGM 0

  ; GREEDY-LABEL: name: sample_1d_sgpr_vaddr__sgpr_rsrc__sgpr_samp
  ; GREEDY-LABEL: name: sample_1d_sgpr_vaddr__sgpr_rsrc__sgpr_samp

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; GREEDY:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
  ; GREEDY:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8

  ; GREEDY:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
  ; GREEDY:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr10
  ; GREEDY:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr10

  ; GREEDY:   [[COPY9:%[0-9]+]]:sgpr(s32) = COPY $sgpr11
  ; GREEDY:   [[COPY9:%[0-9]+]]:sgpr(s32) = COPY $sgpr11

  ; GREEDY:   [[COPY10:%[0-9]+]]:sgpr(s32) = COPY $sgpr12
  ; GREEDY:   [[COPY10:%[0-9]+]]:sgpr(s32) = COPY $sgpr12

  ; GREEDY:   [[COPY11:%[0-9]+]]:sgpr(s32) = COPY $sgpr13
  ; GREEDY:   [[COPY11:%[0-9]+]]:sgpr(s32) = COPY $sgpr13

  ; GREEDY:   [[COPY12:%[0-9]+]]:sgpr(s32) = COPY $sgpr14

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GREEDY:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GREEDY:   [[COPY12:%[0-9]+]]:sgpr(s32) = COPY $sgpr14

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[COPY13:%[0-9]+]]:vgpr(s32) = COPY [[COPY12]](s32)
  ; GREEDY:   [[COPY13:%[0-9]+]]:vgpr(s32) = COPY [[COPY12]](s32)

  ; GREEDY:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY13]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")
  ; GREEDY:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY13]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 0 :: (dereferenceable load 16 from custom "ImageResource")

  ; GREEDY:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
  ; GREEDY:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)

  ; GREEDY:   S_ENDPGM 0
  ; GREEDY:   S_ENDPGM 0

  %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
  %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)

  store <4 x float> %v, <4 x float> addrspace(1)* undef
  store <4 x float> %v, <4 x float> addrspace(1)* undef

  ret void
  ret void

}
}




; Waterfall loop for rsrc
; Waterfall loop for rsrc

define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__sgpr_samp(<8 x i32> %rsrc, <4 x i32> inreg %samp, float %s) {
define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__sgpr_samp(<8 x i32> %rsrc, <4 x i32> inreg %samp, float %s) {

  ; FAST-LABEL: name: sample_1d_vgpr_vaddr__vgpr_rsrc__sgpr_samp
  ; FAST-LABEL: name: sample_1d_vgpr_vaddr__vgpr_rsrc__sgpr_samp

  ; FAST: bb.1 (%ir-block.0):
  ; FAST: bb.1 (%ir-block.0):

  ; FAST:   successors: %bb.2(0x80000000)
  ; FAST:   successors: %bb.2(0x80000000)

  ; FAST:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8
  ; FAST:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8

  ; FAST:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; FAST:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; FAST:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; FAST:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; FAST:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; FAST:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; FAST:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; FAST:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; FAST:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; FAST:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; FAST:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
  ; FAST:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5

  ; FAST:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
  ; FAST:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6

  ; FAST:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7
  ; FAST:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; FAST:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; FAST:   [[COPY9:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; FAST:   [[COPY9:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; FAST:   [[COPY10:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; FAST:   [[COPY10:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; FAST:   [[COPY11:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; FAST:   [[COPY11:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; FAST:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr8

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; FAST:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; FAST:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr8

  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; FAST:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; FAST:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; FAST:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; FAST:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; FAST:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
  ; FAST:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)

  ; FAST:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; FAST:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; FAST: bb.2:
  ; FAST: bb.2:

  ; FAST:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; FAST:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; FAST:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF2]], %bb.1, %24, %bb.2
  ; FAST:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF2]], %bb.1, %24, %bb.2

Show All 35 Linesdefine amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__sgpr_samp(<8 x i32> %rsrc, <4 x i32> inreg %samp, float %s) {

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6

  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7
  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY8:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY9:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY9:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY10:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY10:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY11:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY11:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr8

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GREEDY:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GREEDY:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr8

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; GREEDY:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GREEDY: bb.2:
  ; GREEDY: bb.2:

  ; GREEDY:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; GREEDY:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; GREEDY:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF2]], %bb.1, %24, %bb.2
  ; GREEDY:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF2]], %bb.1, %24, %bb.2

▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesdefine amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__vgpr_samp(<8 x i32> inreg %rsrc, <4 x i32> %samp, float %s) {

  ; FAST:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; FAST:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; FAST:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; FAST:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; FAST:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; FAST:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; FAST:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; FAST:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; FAST:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; FAST:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; FAST:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; FAST:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; FAST:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
  ; FAST:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8

  ; FAST:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
  ; FAST:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; FAST:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; FAST:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; FAST:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; FAST:   [[COPY10:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; FAST:   [[COPY10:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; FAST:   [[COPY11:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; FAST:   [[COPY11:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; FAST:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[BUILD_VECTOR1:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; FAST:   [[BUILD_VECTOR1:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; FAST:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; FAST:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; FAST:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; FAST:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; FAST:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; FAST:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
  ; FAST:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)

  ; FAST:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; FAST:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; FAST: bb.2:
  ; FAST: bb.2:

  ; FAST:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; FAST:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; FAST:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF2]], %bb.1, %24, %bb.2
  ; FAST:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF2]], %bb.1, %24, %bb.2

Show All 25 Linesdefine amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__vgpr_samp(<8 x i32> inreg %rsrc, <4 x i32> %samp, float %s) {

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; GREEDY:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
  ; GREEDY:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8

  ; GREEDY:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
  ; GREEDY:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY10:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY10:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY11:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY11:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[BUILD_VECTOR1:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GREEDY:   [[BUILD_VECTOR1:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GREEDY:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; GREEDY:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GREEDY: bb.2:
  ; GREEDY: bb.2:

  ; GREEDY:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; GREEDY:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; GREEDY:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF2]], %bb.1, %24, %bb.2
  ; GREEDY:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF2]], %bb.1, %24, %bb.2

Show All 32 Linesdefine amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__vgpr_samp(<8 x i32> %rsrc, <4 x i32> %samp, float %s) {

  ; FAST:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; FAST:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; FAST:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; FAST:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; FAST:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; FAST:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; FAST:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; FAST:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; FAST:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; FAST:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; FAST:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
  ; FAST:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5

  ; FAST:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
  ; FAST:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6

  ; FAST:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7
  ; FAST:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr8
  ; FAST:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr8

  ; FAST:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY $vgpr9
  ; FAST:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY $vgpr9

  ; FAST:   [[COPY10:%[0-9]+]]:vgpr(s32) = COPY $vgpr10
  ; FAST:   [[COPY10:%[0-9]+]]:vgpr(s32) = COPY $vgpr10

  ; FAST:   [[COPY11:%[0-9]+]]:vgpr(s32) = COPY $vgpr11
  ; FAST:   [[COPY11:%[0-9]+]]:vgpr(s32) = COPY $vgpr11

  ; FAST:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr12

  ; FAST:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; FAST:   [[BUILD_VECTOR1:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; FAST:   [[BUILD_VECTOR1:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; FAST:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr12

  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; FAST:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; FAST:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; FAST:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; FAST:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; FAST:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; FAST:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
  ; FAST:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)

  ; FAST:   [[UV4:%[0-9]+]]:vreg_64(s64), [[UV5:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
  ; FAST:   [[UV4:%[0-9]+]]:vreg_64(s64), [[UV5:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)

  ; FAST:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; FAST:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; FAST: bb.2:
  ; FAST: bb.2:

  ; FAST:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; FAST:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Linesdefine amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__vgpr_samp(<8 x i32> %rsrc, <4 x i32> %samp, float %s) {

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6

  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7
  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $vgpr7

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr8
  ; GREEDY:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr8

  ; GREEDY:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY $vgpr9
  ; GREEDY:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY $vgpr9

  ; GREEDY:   [[COPY10:%[0-9]+]]:vgpr(s32) = COPY $vgpr10
  ; GREEDY:   [[COPY10:%[0-9]+]]:vgpr(s32) = COPY $vgpr10

  ; GREEDY:   [[COPY11:%[0-9]+]]:vgpr(s32) = COPY $vgpr11
  ; GREEDY:   [[COPY11:%[0-9]+]]:vgpr(s32) = COPY $vgpr11

  ; GREEDY:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr12

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)

  ; GREEDY:   [[BUILD_VECTOR1:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
  ; GREEDY:   [[BUILD_VECTOR1:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)

  ; GREEDY:   [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $vgpr12

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF1:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; GREEDY:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)

  ; GREEDY:   [[UV4:%[0-9]+]]:vreg_64(s64), [[UV5:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
  ; GREEDY:   [[UV4:%[0-9]+]]:vreg_64(s64), [[UV5:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GREEDY: bb.2:
  ; GREEDY: bb.2:

  ; GREEDY:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; GREEDY:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps float @raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY6]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY6]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




; Copies for VGPR arguments
; Copies for VGPR arguments

define amdgpu_ps float @raw_buffer_load__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32)
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY6]](s32), [[COPY7]], [[COPY5]], 0, 0, 0 :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY6]](s32), [[COPY7]], [[COPY5]], 0, 0, 0 :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




; Waterfall for rsrc
; Waterfall for rsrc

define amdgpu_ps float @raw_buffer_load__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 28 Linesdefine amdgpu_ps float @raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.1, %17, %bb.2
  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.1, %17, %bb.2

Show All 19 Linesdefine amdgpu_ps float @raw_buffer_load__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

Show All 30 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -simplify-mir -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s
; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -simplify-mir -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s

; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -simplify-mir -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s --check-prefix=GREEDY
; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -simplify-mir -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s --check-prefix=GREEDY




; Natural mapping
; Natural mapping

define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_i32
  ; CHECK-LABEL: name: s_buffer_load_i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(s32) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 4)
  ; CHECK:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(s32) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 4)

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[AMDGPU_S_BUFFER_LOAD]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[AMDGPU_S_BUFFER_LOAD]](s32)

  ; CHECK:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)
  ; CHECK:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)

  ; CHECK:   $sgpr0 = COPY [[INT]](s32)
  ; CHECK:   $sgpr0 = COPY [[INT]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0

  ; GREEDY-LABEL: name: s_buffer_load_i32
  ; GREEDY-LABEL: name: s_buffer_load_i32

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(s32) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 4)
  ; GREEDY:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(s32) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 4)

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[AMDGPU_S_BUFFER_LOAD]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[AMDGPU_S_BUFFER_LOAD]](s32)

  ; GREEDY:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)
  ; GREEDY:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)

  ; GREEDY:   $sgpr0 = COPY [[INT]](s32)
  ; GREEDY:   $sgpr0 = COPY [[INT]](s32)

  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $sgpr0
  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $sgpr0

  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret i32 %val
  ret i32 %val

}
}




define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v2i32
  ; CHECK-LABEL: name: s_buffer_load_v2i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 8, align 4)
  ; CHECK:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 8, align 4)

  ; CHECK:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<2 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<2 x s32>)

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)

  ; CHECK:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)
  ; CHECK:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)

  ; CHECK:   $sgpr0 = COPY [[INT]](s32)
  ; CHECK:   $sgpr0 = COPY [[INT]](s32)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)

  ; CHECK:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)
  ; CHECK:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)

  ; CHECK:   $sgpr1 = COPY [[INT1]](s32)
  ; CHECK:   $sgpr1 = COPY [[INT1]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1

  ; GREEDY-LABEL: name: s_buffer_load_v2i32
  ; GREEDY-LABEL: name: s_buffer_load_v2i32

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 8, align 4)
  ; GREEDY:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 8, align 4)

  ; GREEDY:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<2 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<2 x s32>)

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)

  ; GREEDY:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)
  ; GREEDY:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)

  ; GREEDY:   $sgpr0 = COPY [[INT]](s32)
  ; GREEDY:   $sgpr0 = COPY [[INT]](s32)

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)

  ; GREEDY:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)
  ; GREEDY:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)

  ; GREEDY:   $sgpr1 = COPY [[INT1]](s32)
  ; GREEDY:   $sgpr1 = COPY [[INT1]](s32)

  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1

  %val = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret <2 x i32> %val
  ret <2 x i32> %val

}
}




define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v3i32
  ; CHECK-LABEL: name: s_buffer_load_v3i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 12, align 4)
  ; CHECK:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 12, align 4)

  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:sgpr(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), [[DEF]](<4 x s32>), [[DEF]](<4 x s32>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:sgpr(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), [[DEF]](<4 x s32>), [[DEF]](<4 x s32>)

  ; CHECK:   [[BITCAST:%[0-9]+]]:sgpr(s384) = G_BITCAST [[CONCAT_VECTORS]](<12 x s32>)
  ; CHECK:   [[BITCAST:%[0-9]+]]:sgpr(s384) = G_BITCAST [[CONCAT_VECTORS]](<12 x s32>)

  ; CHECK:   [[TRUNC:%[0-9]+]]:sgpr(s96) = G_TRUNC [[BITCAST]](s384)
  ; CHECK:   [[TRUNC:%[0-9]+]]:sgpr(s96) = G_TRUNC [[BITCAST]](s384)

  ; CHECK:   [[BITCAST1:%[0-9]+]]:sgpr(<3 x s32>) = G_BITCAST [[TRUNC]](s96)
  ; CHECK:   [[BITCAST1:%[0-9]+]]:sgpr(<3 x s32>) = G_BITCAST [[TRUNC]](s96)

  ; CHECK:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[BITCAST1]](<3 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[BITCAST1]](<3 x s32>)

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)

  ; CHECK:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)
  ; CHECK:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)

  ; CHECK:   $sgpr0 = COPY [[INT]](s32)
  ; CHECK:   $sgpr0 = COPY [[INT]](s32)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)

  ; CHECK:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)
  ; CHECK:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)

  ; CHECK:   $sgpr1 = COPY [[INT1]](s32)
  ; CHECK:   $sgpr1 = COPY [[INT1]](s32)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[UV2]](s32)
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[UV2]](s32)

  ; CHECK:   [[INT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](s32)
  ; CHECK:   [[INT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](s32)

  ; CHECK:   $sgpr2 = COPY [[INT2]](s32)
  ; CHECK:   $sgpr2 = COPY [[INT2]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2

  ; GREEDY-LABEL: name: s_buffer_load_v3i32
  ; GREEDY-LABEL: name: s_buffer_load_v3i32

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 12, align 4)
  ; GREEDY:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 12, align 4)

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:sgpr(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), [[DEF]](<4 x s32>), [[DEF]](<4 x s32>)
  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:sgpr(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), [[DEF]](<4 x s32>), [[DEF]](<4 x s32>)

  ; GREEDY:   [[BITCAST:%[0-9]+]]:sgpr(s384) = G_BITCAST [[CONCAT_VECTORS]](<12 x s32>)
  ; GREEDY:   [[BITCAST:%[0-9]+]]:sgpr(s384) = G_BITCAST [[CONCAT_VECTORS]](<12 x s32>)

  ; GREEDY:   [[TRUNC:%[0-9]+]]:sgpr(s96) = G_TRUNC [[BITCAST]](s384)
  ; GREEDY:   [[TRUNC:%[0-9]+]]:sgpr(s96) = G_TRUNC [[BITCAST]](s384)

  ; GREEDY:   [[BITCAST1:%[0-9]+]]:sgpr(<3 x s32>) = G_BITCAST [[TRUNC]](s96)
  ; GREEDY:   [[BITCAST1:%[0-9]+]]:sgpr(<3 x s32>) = G_BITCAST [[TRUNC]](s96)

  ; GREEDY:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[BITCAST1]](<3 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[BITCAST1]](<3 x s32>)

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)

Show All 13 Lines
define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v8i32
  ; CHECK-LABEL: name: s_buffer_load_v8i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<8 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 32, align 4)
  ; CHECK:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<8 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 32, align 4)

  ; CHECK:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32), [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<8 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32), [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<8 x s32>)

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)

  ; CHECK:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)
  ; CHECK:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)

  ; CHECK:   $sgpr0 = COPY [[INT]](s32)
  ; CHECK:   $sgpr0 = COPY [[INT]](s32)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)

  ; CHECK:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)
  ; CHECK:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)

  ; CHECK:   $sgpr1 = COPY [[INT1]](s32)
  ; CHECK:   $sgpr1 = COPY [[INT1]](s32)

Show All 18 Linesdefine amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7

  ; GREEDY-LABEL: name: s_buffer_load_v8i32
  ; GREEDY-LABEL: name: s_buffer_load_v8i32

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<8 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 32, align 4)
  ; GREEDY:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<8 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 32, align 4)

  ; GREEDY:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32), [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<8 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32), [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<8 x s32>)

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)

  ; GREEDY:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)
  ; GREEDY:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)

  ; GREEDY:   $sgpr0 = COPY [[INT]](s32)
  ; GREEDY:   $sgpr0 = COPY [[INT]](s32)

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)

  ; GREEDY:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)
  ; GREEDY:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)

  ; GREEDY:   $sgpr1 = COPY [[INT1]](s32)
  ; GREEDY:   $sgpr1 = COPY [[INT1]](s32)

Show All 23 Lines
define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v16i32
  ; CHECK-LABEL: name: s_buffer_load_v16i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<16 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 64, align 4)
  ; CHECK:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<16 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 64, align 4)

  ; CHECK:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32), [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32), [[UV8:%[0-9]+]]:sgpr(s32), [[UV9:%[0-9]+]]:sgpr(s32), [[UV10:%[0-9]+]]:sgpr(s32), [[UV11:%[0-9]+]]:sgpr(s32), [[UV12:%[0-9]+]]:sgpr(s32), [[UV13:%[0-9]+]]:sgpr(s32), [[UV14:%[0-9]+]]:sgpr(s32), [[UV15:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<16 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32), [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32), [[UV8:%[0-9]+]]:sgpr(s32), [[UV9:%[0-9]+]]:sgpr(s32), [[UV10:%[0-9]+]]:sgpr(s32), [[UV11:%[0-9]+]]:sgpr(s32), [[UV12:%[0-9]+]]:sgpr(s32), [[UV13:%[0-9]+]]:sgpr(s32), [[UV14:%[0-9]+]]:sgpr(s32), [[UV15:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<16 x s32>)

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)

  ; CHECK:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)
  ; CHECK:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)

  ; CHECK:   $sgpr0 = COPY [[INT]](s32)
  ; CHECK:   $sgpr0 = COPY [[INT]](s32)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)

  ; CHECK:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)
  ; CHECK:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)

  ; CHECK:   $sgpr1 = COPY [[INT1]](s32)
  ; CHECK:   $sgpr1 = COPY [[INT1]](s32)

▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesdefine amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15

  ; GREEDY-LABEL: name: s_buffer_load_v16i32
  ; GREEDY-LABEL: name: s_buffer_load_v16i32

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<16 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 64, align 4)
  ; GREEDY:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<16 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load 64, align 4)

  ; GREEDY:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32), [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32), [[UV8:%[0-9]+]]:sgpr(s32), [[UV9:%[0-9]+]]:sgpr(s32), [[UV10:%[0-9]+]]:sgpr(s32), [[UV11:%[0-9]+]]:sgpr(s32), [[UV12:%[0-9]+]]:sgpr(s32), [[UV13:%[0-9]+]]:sgpr(s32), [[UV14:%[0-9]+]]:sgpr(s32), [[UV15:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<16 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32), [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32), [[UV8:%[0-9]+]]:sgpr(s32), [[UV9:%[0-9]+]]:sgpr(s32), [[UV10:%[0-9]+]]:sgpr(s32), [[UV11:%[0-9]+]]:sgpr(s32), [[UV12:%[0-9]+]]:sgpr(s32), [[UV13:%[0-9]+]]:sgpr(s32), [[UV14:%[0-9]+]]:sgpr(s32), [[UV15:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<16 x s32>)

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)

  ; GREEDY:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)
  ; GREEDY:   [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32)

  ; GREEDY:   $sgpr0 = COPY [[INT]](s32)
  ; GREEDY:   $sgpr0 = COPY [[INT]](s32)

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32)

  ; GREEDY:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)
  ; GREEDY:   [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32)

  ; GREEDY:   $sgpr1 = COPY [[INT1]](s32)
  ; GREEDY:   $sgpr1 = COPY [[INT1]](s32)

▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
define amdgpu_ps float @s_buffer_load_f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 4)

  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps <2 x float> @s_buffer_load_v2f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps <2 x float> @s_buffer_load_v2f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v2f32_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_v2f32_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 8, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 8, align 4)

  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<2 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<2 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  ; GREEDY-LABEL: name: s_buffer_load_v2f32_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_v2f32_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 8, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 8, align 4)

  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<2 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<2 x s32>)

  ; GREEDY:   $vgpr0 = COPY [[UV]](s32)
  ; GREEDY:   $vgpr0 = COPY [[UV]](s32)

  ; GREEDY:   $vgpr1 = COPY [[UV1]](s32)
  ; GREEDY:   $vgpr1 = COPY [[UV1]](s32)

  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

  %val = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret <2 x float> %val
  ret <2 x float> %val

}
}




define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v3f32_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_v3f32_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[DEF]](<4 x s32>)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[DEF]](<4 x s32>)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[DEF]](<4 x s32>)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[DEF]](<4 x s32>)

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[COPY5]](<4 x s32>), [[COPY6]](<4 x s32>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[COPY5]](<4 x s32>), [[COPY6]](<4 x s32>)

  ; CHECK:   [[BITCAST:%[0-9]+]]:vgpr(s384) = G_BITCAST [[CONCAT_VECTORS]](<12 x s32>)
  ; CHECK:   [[BITCAST:%[0-9]+]]:vgpr(s384) = G_BITCAST [[CONCAT_VECTORS]](<12 x s32>)

  ; CHECK:   [[TRUNC:%[0-9]+]]:vgpr(s96) = G_TRUNC [[BITCAST]](s384)
  ; CHECK:   [[TRUNC:%[0-9]+]]:vgpr(s96) = G_TRUNC [[BITCAST]](s384)

  ; CHECK:   [[BITCAST1:%[0-9]+]]:vgpr(<3 x s32>) = G_BITCAST [[TRUNC]](s96)
  ; CHECK:   [[BITCAST1:%[0-9]+]]:vgpr(<3 x s32>) = G_BITCAST [[TRUNC]](s96)

  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[BITCAST1]](<3 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[BITCAST1]](<3 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   $vgpr2 = COPY [[UV2]](s32)
  ; CHECK:   $vgpr2 = COPY [[UV2]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2

  ; GREEDY-LABEL: name: s_buffer_load_v3f32_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_v3f32_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(<4 x s32>) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(<4 x s32>) = G_IMPLICIT_DEF

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[DEF]](<4 x s32>)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[DEF]](<4 x s32>)

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[DEF]](<4 x s32>)
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[DEF]](<4 x s32>)

  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[COPY5]](<4 x s32>), [[COPY6]](<4 x s32>)
  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[COPY5]](<4 x s32>), [[COPY6]](<4 x s32>)

  ; GREEDY:   [[BITCAST:%[0-9]+]]:vgpr(s384) = G_BITCAST [[CONCAT_VECTORS]](<12 x s32>)
  ; GREEDY:   [[BITCAST:%[0-9]+]]:vgpr(s384) = G_BITCAST [[CONCAT_VECTORS]](<12 x s32>)

Show All 11 Lines
define amdgpu_ps <4 x float> @s_buffer_load_v4f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps <4 x float> @s_buffer_load_v4f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v4f32_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_v4f32_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<4 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   $vgpr2 = COPY [[UV2]](s32)
  ; CHECK:   $vgpr2 = COPY [[UV2]](s32)

  ; CHECK:   $vgpr3 = COPY [[UV3]](s32)
  ; CHECK:   $vgpr3 = COPY [[UV3]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  ; GREEDY-LABEL: name: s_buffer_load_v4f32_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_v4f32_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<4 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<4 x s32>)

  ; GREEDY:   $vgpr0 = COPY [[UV]](s32)
  ; GREEDY:   $vgpr0 = COPY [[UV]](s32)

  ; GREEDY:   $vgpr1 = COPY [[UV1]](s32)
  ; GREEDY:   $vgpr1 = COPY [[UV1]](s32)

  ; GREEDY:   $vgpr2 = COPY [[UV2]](s32)
  ; GREEDY:   $vgpr2 = COPY [[UV2]](s32)

  ; GREEDY:   $vgpr3 = COPY [[UV3]](s32)
  ; GREEDY:   $vgpr3 = COPY [[UV3]](s32)

  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3

  %val = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret <4 x float> %val
  ret <4 x float> %val

}
}




define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)

  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   $vgpr2 = COPY [[UV2]](s32)
  ; CHECK:   $vgpr2 = COPY [[UV2]](s32)

  ; CHECK:   $vgpr3 = COPY [[UV3]](s32)
  ; CHECK:   $vgpr3 = COPY [[UV3]](s32)

  ; CHECK:   $vgpr4 = COPY [[UV4]](s32)
  ; CHECK:   $vgpr4 = COPY [[UV4]](s32)

  ; CHECK:   $vgpr5 = COPY [[UV5]](s32)
  ; CHECK:   $vgpr5 = COPY [[UV5]](s32)

  ; CHECK:   $vgpr6 = COPY [[UV6]](s32)
  ; CHECK:   $vgpr6 = COPY [[UV6]](s32)

  ; CHECK:   $vgpr7 = COPY [[UV7]](s32)
  ; CHECK:   $vgpr7 = COPY [[UV7]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)

  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>)

  ; GREEDY:   $vgpr0 = COPY [[UV]](s32)
  ; GREEDY:   $vgpr0 = COPY [[UV]](s32)

  ; GREEDY:   $vgpr1 = COPY [[UV1]](s32)
  ; GREEDY:   $vgpr1 = COPY [[UV1]](s32)

Show All 11 Lines
define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v16f32_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_v16f32_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>), [[AMDGPU_BUFFER_LOAD2]](<4 x s32>), [[AMDGPU_BUFFER_LOAD3]](<4 x s32>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>), [[AMDGPU_BUFFER_LOAD2]](<4 x s32>), [[AMDGPU_BUFFER_LOAD3]](<4 x s32>)

  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32), [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32), [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s32>)

Show All 16 Linesdefine amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15

  ; GREEDY-LABEL: name: s_buffer_load_v16f32_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_v16f32_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)

  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>), [[AMDGPU_BUFFER_LOAD2]](<4 x s32>), [[AMDGPU_BUFFER_LOAD3]](<4 x s32>)
  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>), [[AMDGPU_BUFFER_LOAD2]](<4 x s32>), [[AMDGPU_BUFFER_LOAD3]](<4 x s32>)

  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32), [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32), [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s32>)

Show All 21 Lines
define amdgpu_ps void @s_buffer_load_i96_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps void @s_buffer_load_i96_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_i96_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_i96_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[TRUNC:%[0-9]+]]:vgpr(s96) = G_TRUNC [[AMDGPU_BUFFER_LOAD]](s128)
  ; CHECK:   [[TRUNC:%[0-9]+]]:vgpr(s96) = G_TRUNC [[AMDGPU_BUFFER_LOAD]](s128)

  ; CHECK:   G_STORE [[TRUNC]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)
  ; CHECK:   G_STORE [[TRUNC]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  ; GREEDY-LABEL: name: s_buffer_load_i96_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_i96_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[TRUNC:%[0-9]+]]:vgpr(s96) = G_TRUNC [[AMDGPU_BUFFER_LOAD]](s128)
  ; GREEDY:   [[TRUNC:%[0-9]+]]:vgpr(s96) = G_TRUNC [[AMDGPU_BUFFER_LOAD]](s128)

  ; GREEDY:   G_STORE [[TRUNC]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)
  ; GREEDY:   G_STORE [[TRUNC]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)

  ; GREEDY:   S_ENDPGM 0
  ; GREEDY:   S_ENDPGM 0

  %val = call i96 @llvm.amdgcn.s.buffer.load.i96(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call i96 @llvm.amdgcn.s.buffer.load.i96(<4 x i32> %rsrc, i32 %soffset, i32 0)

  store i96 %val, i96 addrspace(1)* undef
  store i96 %val, i96 addrspace(1)* undef

  ret void
  ret void

}
}




; Test split of a wide scalar
; Test split of a wide scalar

define amdgpu_ps void @s_buffer_load_i256_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps void @s_buffer_load_i256_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_i256_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_i256_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[MV:%[0-9]+]]:vgpr(s256) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFER_LOAD1]](s128)
  ; CHECK:   [[MV:%[0-9]+]]:vgpr(s256) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFER_LOAD1]](s128)

  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s128), [[UV1:%[0-9]+]]:vgpr(s128) = G_UNMERGE_VALUES [[MV]](s256)
  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s128), [[UV1:%[0-9]+]]:vgpr(s128) = G_UNMERGE_VALUES [[MV]](s256)

  ; CHECK:   G_STORE [[UV]](s128), [[DEF]](p1) :: (store 16 into `i256 addrspace(1)* undef`, align 8, addrspace 1)
  ; CHECK:   G_STORE [[UV]](s128), [[DEF]](p1) :: (store 16 into `i256 addrspace(1)* undef`, align 8, addrspace 1)

  ; CHECK:   [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16
  ; CHECK:   [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16

  ; CHECK:   [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64)
  ; CHECK:   [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64)

  ; CHECK:   G_STORE [[UV1]](s128), [[PTR_ADD]](p1) :: (store 16 into `i256 addrspace(1)* undef` + 16, align 8, addrspace 1)
  ; CHECK:   G_STORE [[UV1]](s128), [[PTR_ADD]](p1) :: (store 16 into `i256 addrspace(1)* undef` + 16, align 8, addrspace 1)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  ; GREEDY-LABEL: name: s_buffer_load_i256_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_i256_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[MV:%[0-9]+]]:vgpr(s256) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFER_LOAD1]](s128)
  ; GREEDY:   [[MV:%[0-9]+]]:vgpr(s256) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFER_LOAD1]](s128)

  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(s128), [[UV1:%[0-9]+]]:vgpr(s128) = G_UNMERGE_VALUES [[MV]](s256)
  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(s128), [[UV1:%[0-9]+]]:vgpr(s128) = G_UNMERGE_VALUES [[MV]](s256)

  ; GREEDY:   G_STORE [[UV]](s128), [[DEF]](p1) :: (store 16 into `i256 addrspace(1)* undef`, align 8, addrspace 1)
  ; GREEDY:   G_STORE [[UV]](s128), [[DEF]](p1) :: (store 16 into `i256 addrspace(1)* undef`, align 8, addrspace 1)

Show All 10 Lines
define amdgpu_ps void @s_buffer_load_i512_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps void @s_buffer_load_i512_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_i512_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_i512_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)

  ; CHECK:   [[MV:%[0-9]+]]:vgpr(s512) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFER_LOAD1]](s128), [[AMDGPU_BUFFER_LOAD2]](s128), [[AMDGPU_BUFFER_LOAD3]](s128)
  ; CHECK:   [[MV:%[0-9]+]]:vgpr(s512) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFER_LOAD1]](s128), [[AMDGPU_BUFFER_LOAD2]](s128), [[AMDGPU_BUFFER_LOAD3]](s128)

Show All 11 Linesdefine amdgpu_ps void @s_buffer_load_i512_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  ; GREEDY-LABEL: name: s_buffer_load_i512_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_i512_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)

  ; GREEDY:   [[MV:%[0-9]+]]:vgpr(s512) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFER_LOAD1]](s128), [[AMDGPU_BUFFER_LOAD2]](s128), [[AMDGPU_BUFFER_LOAD3]](s128)
  ; GREEDY:   [[MV:%[0-9]+]]:vgpr(s512) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFER_LOAD1]](s128), [[AMDGPU_BUFFER_LOAD2]](s128), [[AMDGPU_BUFFER_LOAD3]](s128)

Show All 18 Lines
define amdgpu_ps void @s_buffer_load_v16i16_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps void @s_buffer_load_v16i16_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v16i16_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_v16i16_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s16>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<8 x s16>), [[AMDGPU_BUFFER_LOAD1]](<8 x s16>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s16>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<8 x s16>), [[AMDGPU_BUFFER_LOAD1]](<8 x s16>)

  ; CHECK:   [[UV:%[0-9]+]]:vgpr(<8 x s16>), [[UV1:%[0-9]+]]:vgpr(<8 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s16>)
  ; CHECK:   [[UV:%[0-9]+]]:vgpr(<8 x s16>), [[UV1:%[0-9]+]]:vgpr(<8 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s16>)

  ; CHECK:   G_STORE [[UV]](<8 x s16>), [[DEF]](p1) :: (store 16 into `<16 x i16> addrspace(1)* undef`, align 32, addrspace 1)
  ; CHECK:   G_STORE [[UV]](<8 x s16>), [[DEF]](p1) :: (store 16 into `<16 x i16> addrspace(1)* undef`, align 32, addrspace 1)

  ; CHECK:   [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16
  ; CHECK:   [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16

  ; CHECK:   [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64)
  ; CHECK:   [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64)

  ; CHECK:   G_STORE [[UV1]](<8 x s16>), [[PTR_ADD]](p1) :: (store 16 into `<16 x i16> addrspace(1)* undef` + 16, basealign 32, addrspace 1)
  ; CHECK:   G_STORE [[UV1]](<8 x s16>), [[PTR_ADD]](p1) :: (store 16 into `<16 x i16> addrspace(1)* undef` + 16, basealign 32, addrspace 1)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  ; GREEDY-LABEL: name: s_buffer_load_v16i16_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_v16i16_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s16>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<8 x s16>), [[AMDGPU_BUFFER_LOAD1]](<8 x s16>)
  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s16>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<8 x s16>), [[AMDGPU_BUFFER_LOAD1]](<8 x s16>)

  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(<8 x s16>), [[UV1:%[0-9]+]]:vgpr(<8 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s16>)
  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(<8 x s16>), [[UV1:%[0-9]+]]:vgpr(<8 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s16>)

  ; GREEDY:   G_STORE [[UV]](<8 x s16>), [[DEF]](p1) :: (store 16 into `<16 x i16> addrspace(1)* undef`, align 32, addrspace 1)
  ; GREEDY:   G_STORE [[UV]](<8 x s16>), [[DEF]](p1) :: (store 16 into `<16 x i16> addrspace(1)* undef`, align 32, addrspace 1)

Show All 10 Lines
define amdgpu_ps void @s_buffer_load_v32i16_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps void @s_buffer_load_v32i16_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v32i16_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_v32i16_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<32 x s16>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<8 x s16>), [[AMDGPU_BUFFER_LOAD1]](<8 x s16>), [[AMDGPU_BUFFER_LOAD2]](<8 x s16>), [[AMDGPU_BUFFER_LOAD3]](<8 x s16>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<32 x s16>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<8 x s16>), [[AMDGPU_BUFFER_LOAD1]](<8 x s16>), [[AMDGPU_BUFFER_LOAD2]](<8 x s16>), [[AMDGPU_BUFFER_LOAD3]](<8 x s16>)

Show All 11 Linesdefine amdgpu_ps void @s_buffer_load_v32i16_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  ; GREEDY-LABEL: name: s_buffer_load_v32i16_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_v32i16_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)

  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<32 x s16>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<8 x s16>), [[AMDGPU_BUFFER_LOAD1]](<8 x s16>), [[AMDGPU_BUFFER_LOAD2]](<8 x s16>), [[AMDGPU_BUFFER_LOAD3]](<8 x s16>)
  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<32 x s16>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<8 x s16>), [[AMDGPU_BUFFER_LOAD1]](<8 x s16>), [[AMDGPU_BUFFER_LOAD2]](<8 x s16>), [[AMDGPU_BUFFER_LOAD3]](<8 x s16>)

Show All 18 Lines
define amdgpu_ps void @s_buffer_load_v4i64_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps void @s_buffer_load_v4i64_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v4i64_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_v4i64_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s64>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x s64>), [[AMDGPU_BUFFER_LOAD1]](<2 x s64>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s64>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x s64>), [[AMDGPU_BUFFER_LOAD1]](<2 x s64>)

  ; CHECK:   [[UV:%[0-9]+]]:vgpr(<2 x s64>), [[UV1:%[0-9]+]]:vgpr(<2 x s64>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x s64>)
  ; CHECK:   [[UV:%[0-9]+]]:vgpr(<2 x s64>), [[UV1:%[0-9]+]]:vgpr(<2 x s64>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x s64>)

  ; CHECK:   G_STORE [[UV]](<2 x s64>), [[DEF]](p1) :: (store 16 into `<4 x i64> addrspace(1)* undef`, align 32, addrspace 1)
  ; CHECK:   G_STORE [[UV]](<2 x s64>), [[DEF]](p1) :: (store 16 into `<4 x i64> addrspace(1)* undef`, align 32, addrspace 1)

  ; CHECK:   [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16
  ; CHECK:   [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16

  ; CHECK:   [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64)
  ; CHECK:   [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64)

  ; CHECK:   G_STORE [[UV1]](<2 x s64>), [[PTR_ADD]](p1) :: (store 16 into `<4 x i64> addrspace(1)* undef` + 16, basealign 32, addrspace 1)
  ; CHECK:   G_STORE [[UV1]](<2 x s64>), [[PTR_ADD]](p1) :: (store 16 into `<4 x i64> addrspace(1)* undef` + 16, basealign 32, addrspace 1)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  ; GREEDY-LABEL: name: s_buffer_load_v4i64_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_v4i64_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s64>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x s64>), [[AMDGPU_BUFFER_LOAD1]](<2 x s64>)
  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s64>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x s64>), [[AMDGPU_BUFFER_LOAD1]](<2 x s64>)

  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(<2 x s64>), [[UV1:%[0-9]+]]:vgpr(<2 x s64>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x s64>)
  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(<2 x s64>), [[UV1:%[0-9]+]]:vgpr(<2 x s64>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x s64>)

  ; GREEDY:   G_STORE [[UV]](<2 x s64>), [[DEF]](p1) :: (store 16 into `<4 x i64> addrspace(1)* undef`, align 32, addrspace 1)
  ; GREEDY:   G_STORE [[UV]](<2 x s64>), [[DEF]](p1) :: (store 16 into `<4 x i64> addrspace(1)* undef`, align 32, addrspace 1)

Show All 10 Lines
define amdgpu_ps void @s_buffer_load_v8i64_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps void @s_buffer_load_v8i64_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v8i64_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_v8i64_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s64>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x s64>), [[AMDGPU_BUFFER_LOAD1]](<2 x s64>), [[AMDGPU_BUFFER_LOAD2]](<2 x s64>), [[AMDGPU_BUFFER_LOAD3]](<2 x s64>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s64>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x s64>), [[AMDGPU_BUFFER_LOAD1]](<2 x s64>), [[AMDGPU_BUFFER_LOAD2]](<2 x s64>), [[AMDGPU_BUFFER_LOAD3]](<2 x s64>)

Show All 11 Linesdefine amdgpu_ps void @s_buffer_load_v8i64_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  ; GREEDY-LABEL: name: s_buffer_load_v8i64_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_v8i64_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)

  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s64>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x s64>), [[AMDGPU_BUFFER_LOAD1]](<2 x s64>), [[AMDGPU_BUFFER_LOAD2]](<2 x s64>), [[AMDGPU_BUFFER_LOAD3]](<2 x s64>)
  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s64>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x s64>), [[AMDGPU_BUFFER_LOAD1]](<2 x s64>), [[AMDGPU_BUFFER_LOAD2]](<2 x s64>), [[AMDGPU_BUFFER_LOAD3]](<2 x s64>)

Show All 18 Lines
define amdgpu_ps void @s_buffer_load_v4p1_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps void @s_buffer_load_v4p1_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v4p1_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_v4p1_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x p1>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x p1>), [[AMDGPU_BUFFER_LOAD1]](<2 x p1>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x p1>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x p1>), [[AMDGPU_BUFFER_LOAD1]](<2 x p1>)

  ; CHECK:   [[UV:%[0-9]+]]:vgpr(<2 x p1>), [[UV1:%[0-9]+]]:vgpr(<2 x p1>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x p1>)
  ; CHECK:   [[UV:%[0-9]+]]:vgpr(<2 x p1>), [[UV1:%[0-9]+]]:vgpr(<2 x p1>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x p1>)

  ; CHECK:   G_STORE [[UV]](<2 x p1>), [[DEF]](p1) :: (store 16 into `<4 x i8 addrspace(1)*> addrspace(1)* undef`, align 32, addrspace 1)
  ; CHECK:   G_STORE [[UV]](<2 x p1>), [[DEF]](p1) :: (store 16 into `<4 x i8 addrspace(1)*> addrspace(1)* undef`, align 32, addrspace 1)

  ; CHECK:   [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16
  ; CHECK:   [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16

  ; CHECK:   [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64)
  ; CHECK:   [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64)

  ; CHECK:   G_STORE [[UV1]](<2 x p1>), [[PTR_ADD]](p1) :: (store 16 into `<4 x i8 addrspace(1)*> addrspace(1)* undef` + 16, basealign 32, addrspace 1)
  ; CHECK:   G_STORE [[UV1]](<2 x p1>), [[PTR_ADD]](p1) :: (store 16 into `<4 x i8 addrspace(1)*> addrspace(1)* undef` + 16, basealign 32, addrspace 1)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  ; GREEDY-LABEL: name: s_buffer_load_v4p1_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_v4p1_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x p1>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x p1>), [[AMDGPU_BUFFER_LOAD1]](<2 x p1>)
  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x p1>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x p1>), [[AMDGPU_BUFFER_LOAD1]](<2 x p1>)

  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(<2 x p1>), [[UV1:%[0-9]+]]:vgpr(<2 x p1>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x p1>)
  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(<2 x p1>), [[UV1:%[0-9]+]]:vgpr(<2 x p1>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x p1>)

  ; GREEDY:   G_STORE [[UV]](<2 x p1>), [[DEF]](p1) :: (store 16 into `<4 x i8 addrspace(1)*> addrspace(1)* undef`, align 32, addrspace 1)
  ; GREEDY:   G_STORE [[UV]](<2 x p1>), [[DEF]](p1) :: (store 16 into `<4 x i8 addrspace(1)*> addrspace(1)* undef`, align 32, addrspace 1)

Show All 10 Lines
define amdgpu_ps void @s_buffer_load_v8p1_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
define amdgpu_ps void @s_buffer_load_v8p1_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_v8p1_vgpr_offset
  ; CHECK-LABEL: name: s_buffer_load_v8p1_vgpr_offset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x p1>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x p1>), [[AMDGPU_BUFFER_LOAD1]](<2 x p1>), [[AMDGPU_BUFFER_LOAD2]](<2 x p1>), [[AMDGPU_BUFFER_LOAD3]](<2 x p1>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x p1>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x p1>), [[AMDGPU_BUFFER_LOAD1]](<2 x p1>), [[AMDGPU_BUFFER_LOAD2]](<2 x p1>), [[AMDGPU_BUFFER_LOAD3]](<2 x p1>)

Show All 11 Linesdefine amdgpu_ps void @s_buffer_load_v8p1_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  ; GREEDY-LABEL: name: s_buffer_load_v8p1_vgpr_offset
  ; GREEDY-LABEL: name: s_buffer_load_v8p1_vgpr_offset

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)

  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x p1>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x p1>), [[AMDGPU_BUFFER_LOAD1]](<2 x p1>), [[AMDGPU_BUFFER_LOAD2]](<2 x p1>), [[AMDGPU_BUFFER_LOAD3]](<2 x p1>)
  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x p1>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x p1>), [[AMDGPU_BUFFER_LOAD1]](<2 x p1>), [[AMDGPU_BUFFER_LOAD2]](<2 x p1>), [[AMDGPU_BUFFER_LOAD3]](<2 x p1>)

Show All 17 Lines
define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4092(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4092(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092
  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4092
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4092

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4092, 0, 0 :: (dereferenceable invariant load 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4092, 0, 0 :: (dereferenceable invariant load 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092
  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4092
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4092

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4092, 0, 0 :: (dereferenceable invariant load 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4092, 0, 0 :: (dereferenceable invariant load 4)

  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %soffset = add i32 %soffset.base, 4092
  %soffset = add i32 %soffset.base, 4092

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4095(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4095(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095
  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4095
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4095

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4095, 0, 0 :: (dereferenceable invariant load 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4095, 0, 0 :: (dereferenceable invariant load 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095
  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4095
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4095

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4095, 0, 0 :: (dereferenceable invariant load 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4095, 0, 0 :: (dereferenceable invariant load 4)

  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %soffset = add i32 %soffset.base, 4095
  %soffset = add i32 %soffset.base, 4095

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4096(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4096(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096
  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096
  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 4)

  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %soffset = add i32 %soffset.base, 4096
  %soffset = add i32 %soffset.base, 4096

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




; Make sure the base offset is added to each split load.
; Make sure the base offset is added to each split load.

define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064
  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)

Show All 9 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064
  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)

Show All 16 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068
  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4068
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4068

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)

  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>)

  ; CHECK:   $vgpr0 = COPY [[UV]](s32)
  ; CHECK:   $vgpr0 = COPY [[UV]](s32)

  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)
  ; CHECK:   $vgpr1 = COPY [[UV1]](s32)

  ; CHECK:   $vgpr2 = COPY [[UV2]](s32)
  ; CHECK:   $vgpr2 = COPY [[UV2]](s32)

  ; CHECK:   $vgpr3 = COPY [[UV3]](s32)
  ; CHECK:   $vgpr3 = COPY [[UV3]](s32)

  ; CHECK:   $vgpr4 = COPY [[UV4]](s32)
  ; CHECK:   $vgpr4 = COPY [[UV4]](s32)

  ; CHECK:   $vgpr5 = COPY [[UV5]](s32)
  ; CHECK:   $vgpr5 = COPY [[UV5]](s32)

  ; CHECK:   $vgpr6 = COPY [[UV6]](s32)
  ; CHECK:   $vgpr6 = COPY [[UV6]](s32)

  ; CHECK:   $vgpr7 = COPY [[UV7]](s32)
  ; CHECK:   $vgpr7 = COPY [[UV7]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068
  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4068
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4068

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
  ; GREEDY:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)

  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>)

Show All 14 Lines
define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; CHECK-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032
  ; CHECK-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4032
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4032

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4032, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4032, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4048, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4048, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

Show All 19 Linesdefine amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15

  ; GREEDY-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032
  ; GREEDY-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4032
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4032

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4032, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4032, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4048, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4048, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

Show All 25 Lines
define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i32> inreg %rsrc, i32 %soffset.base) {
define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; CHECK-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036
  ; CHECK-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4036
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4036

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)

Show All 18 Linesdefine amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i32> inreg %rsrc, i32 %soffset.base) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15

  ; GREEDY-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036
  ; GREEDY-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4036
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4036

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load 16 + 16, align 4)

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load 16 + 48, align 4)

Show All 25 Lines
define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %soffset) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_rsrc
  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_rsrc

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32)

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

Show All 21 Linesdefine amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %soffset) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_rsrc
  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_rsrc

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GREEDY:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32)

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

  ; GREEDY:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GREEDY: bb.2:
  ; GREEDY: bb.2:

Show All 27 Lines
define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %rsrc, i32 inreg %soffset.base) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092
  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4092
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4092

  ; CHECK:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]
  ; CHECK:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

Show All 22 Linesdefine amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092
  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GREEDY:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4092
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4092

  ; GREEDY:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]
  ; GREEDY:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

  ; GREEDY:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

Show All 29 Lines
define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {
define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096
  ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096

  ; CHECK:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]
  ; CHECK:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)

  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

Show All 23 Linesdefine amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096
  ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GREEDY:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096

  ; GREEDY:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]
  ; GREEDY:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)

  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

  ; GREEDY:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

▲ Show 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %rsrc, i32 inreg %soffset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064
  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064

  ; CHECK:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]
  ; CHECK:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

Show All 30 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064
  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GREEDY:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064

  ; GREEDY:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]
  ; GREEDY:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GREEDY: bb.2:
  ; GREEDY: bb.2:

Show All 38 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %rsrc, i32 inreg %soffset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068
  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4068
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4068

  ; CHECK:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]
  ; CHECK:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)

  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

Show All 31 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068
  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GREEDY:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4068
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4068

  ; GREEDY:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]
  ; GREEDY:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)

  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

Show All 37 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096
  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096

  ; CHECK:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]
  ; CHECK:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)

  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

Show All 31 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096
  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GREEDY:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096

  ; GREEDY:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]
  ; GREEDY:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]]

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)

  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

Show All 37 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000(<4 x i32> %rsrc, i32 %offset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000(<4 x i32> %rsrc, i32 %offset.base) {

  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5000
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5000

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

Show All 30 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000(<4 x i32> %rsrc, i32 %offset.base) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GREEDY:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5000
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5000

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GREEDY: bb.2:
  ; GREEDY: bb.2:

Show All 36 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076(<4 x i32> %rsrc, i32 %offset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076(<4 x i32> %rsrc, i32 %offset.base) {

  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4076
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4076

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

Show All 30 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076(<4 x i32> %rsrc, i32 %offset.base) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GREEDY:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4076
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4076

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GREEDY: bb.2:
  ; GREEDY: bb.2:

Show All 36 Lines
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080(<4 x i32> %rsrc, i32 %offset.base) {
define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080(<4 x i32> %rsrc, i32 %offset.base) {

  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
  ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4080
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4080

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

Show All 30 Linesdefine amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080(<4 x i32> %rsrc, i32 %offset.base) {

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7

  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
  ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
  ; GREEDY:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; GREEDY:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; GREEDY:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; GREEDY:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4080
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4080

  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]]

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; GREEDY:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; GREEDY:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; GREEDY:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; GREEDY: bb.2:
  ; GREEDY: bb.2:

▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {

  ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr
  ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]

  ; CHECK:   [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr
  ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]

  ; GREEDY:   [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load 4)

  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %offset = add i32 %offset.v, %offset.s
  %offset = add i32 %offset.v, %offset.s

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {

  ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr
  ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]

  ; CHECK:   [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr
  ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]

  ; GREEDY:   [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load 4)

  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %offset = add i32 %offset.s, %offset.v
  %offset = add i32 %offset.s, %offset.v

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr_imm(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr_imm(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {

  ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm
  ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]
  ; CHECK:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]

  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[ADD]], [[C1]], 1024, 0, 0 :: (dereferenceable invariant load 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[ADD]], [[C1]], 1024, 0, 0 :: (dereferenceable invariant load 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm
  ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024

  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]
  ; GREEDY:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]

  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[ADD]], [[C1]], 1024, 0, 0 :: (dereferenceable invariant load 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[ADD]], [[C1]], 1024, 0, 0 :: (dereferenceable invariant load 4)

  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %offset.base = add i32 %offset.v, %offset.s
  %offset.base = add i32 %offset.v, %offset.s

  %offset = add i32 %offset.base, 1024
  %offset = add i32 %offset.base, 1024

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr_imm(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr_imm(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {

  ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm
  ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]
  ; CHECK:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]

  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[ADD]], [[C1]], 1024, 0, 0 :: (dereferenceable invariant load 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[ADD]], [[C1]], 1024, 0, 0 :: (dereferenceable invariant load 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm
  ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024

  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]
  ; GREEDY:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]

  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[ADD]], [[C1]], 1024, 0, 0 :: (dereferenceable invariant load 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[ADD]], [[C1]], 1024, 0, 0 :: (dereferenceable invariant load 4)

Show All 9 Lines
define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_sgpr_vgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_sgpr_vgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {

  ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr
  ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024

  ; CHECK:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY5]], [[C]]
  ; CHECK:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY5]], [[C]]

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)

  ; CHECK:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]
  ; CHECK:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[ADD]], 0, 0, 0 :: (dereferenceable invariant load 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[ADD]], 0, 0, 0 :: (dereferenceable invariant load 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr
  ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024

  ; GREEDY:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY5]], [[C]]
  ; GREEDY:   [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY5]], [[C]]

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)

  ; GREEDY:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]
  ; GREEDY:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[ADD]], 0, 0, 0 :: (dereferenceable invariant load 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[ADD]], 0, 0, 0 :: (dereferenceable invariant load 4)

  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; GREEDY:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %offset.base = add i32 %offset.s, 1024
  %offset.base = add i32 %offset.s, 1024

  %offset = add i32 %offset.base, %offset.v
  %offset = add i32 %offset.base, %offset.v

  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)

  ret float %val
  ret float %val

}
}




define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_vgpr_sgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_vgpr_sgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {

  ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr
  ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]
  ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)

  ; CHECK:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]
  ; CHECK:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]

  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; CHECK:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[ADD]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[ADD]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr
  ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr

  ; GREEDY: bb.1 (%ir-block.0):
  ; GREEDY: bb.1 (%ir-block.0):

  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; GREEDY:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; GREEDY:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; GREEDY:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; GREEDY:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; GREEDY:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GREEDY:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; GREEDY:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; GREEDY:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
  ; GREEDY:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024

  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
  ; GREEDY:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)

  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]
  ; GREEDY:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]

  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
  ; GREEDY:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)

  ; GREEDY:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]
  ; GREEDY:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]

  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
  ; GREEDY:   [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[ADD]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load 4)
  ; GREEDY:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[ADD]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load 4)

  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; GREEDY:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

Show All 33 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps float @struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), [[COPY5]], [[COPY6]], 0, 0, -1 :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), [[COPY5]], [[COPY6]], 0, 0, -1 :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




; Copies for VGPR arguments
; Copies for VGPR arguments

define amdgpu_ps float @struct_buffer_load__sgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load__sgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load__sgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load__sgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32)
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32)

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)

  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY8]], [[COPY6]], 0, 0, -1 :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY8]], [[COPY6]], 0, 0, -1 :: (dereferenceable load 4 from custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
  ; CHECK:   $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret float %val
  ret float %val

}
}




; Waterfall for rsrc
; Waterfall for rsrc

define amdgpu_ps float @struct_buffer_load__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.1, %16, %bb.2
  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.1, %16, %bb.2

  ; CHECK:   [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[DEF]](s32), %bb.1, %10(s32), %bb.2
  ; CHECK:   [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[DEF]](s32), %bb.1, %10(s32), %bb.2

Show All 26 Linesdefine amdgpu_ps float @struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex_vgpr_voffset__vgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex_vgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex_vgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.1, %16, %bb.2
  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.1, %16, %bb.2

  ; CHECK:   [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[DEF]](s32), %bb.1, %10(s32), %bb.2
  ; CHECK:   [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[DEF]](s32), %bb.1, %10(s32), %bb.2

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY6]](s32), implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY6]](s32), implicit $exec

Show All 17 Linesdefine amdgpu_ps float @struct_buffer_load__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.1, %16, %bb.2
  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.1, %16, %bb.2

  ; CHECK:   [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[DEF]](s32), %bb.1, %10(s32), %bb.2
  ; CHECK:   [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[DEF]](s32), %bb.1, %10(s32), %bb.2

Show All 28 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps void @struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; CHECK:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   G_AMDGPU_BUFFER_STORE [[COPY4]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY5]](s32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   G_AMDGPU_BUFFER_STORE [[COPY4]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY5]](s32), [[COPY6]], [[COPY7]], 0, 0, -1 :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; Copies for VGPR arguments
; Copies for VGPR arguments

define amdgpu_ps void @struct_buffer_store__sgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float inreg %val, i32 inreg %vindex, i32 inreg %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store__sgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float inreg %val, i32 inreg %vindex, i32 inreg %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store__sgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store__sgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
  ; CHECK:   [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6

  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7
  ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr7

  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
  ; CHECK:   [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr8

  ; CHECK:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
  ; CHECK:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr9

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32)
  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32)

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr(s32) = COPY [[COPY6]](s32)
  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr(s32) = COPY [[COPY6]](s32)

  ; CHECK:   G_AMDGPU_BUFFER_STORE [[COPY8]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY9]](s32), [[COPY10]], [[COPY7]], 0, 0, -1 :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   G_AMDGPU_BUFFER_STORE [[COPY8]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY9]](s32), [[COPY10]], [[COPY7]], 0, 0, -1 :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  call void @llvm.amdgcn.struct.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
  call void @llvm.amdgcn.struct.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)

  ret void
  ret void

}
}




; Waterfall for rsrc
; Waterfall for rsrc

define amdgpu_ps void @struct_buffer_store__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, float %val, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, float %val, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %14, %bb.2
  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %14, %bb.2

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub0(s64), implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub0(s64), implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub1(s64), implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub1(s64), implicit $exec

Show All 23 Linesdefine amdgpu_ps void @struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__vgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %vindex, i32 %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3

  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4

  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr3
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr3

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %14, %bb.2
  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %14, %bb.2

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY7]](s32), implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY7]](s32), implicit $exec

  ; CHECK:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](s32), [[COPY7]](s32), implicit $exec
  ; CHECK:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](s32), [[COPY7]](s32), implicit $exec

  ; CHECK:   G_AMDGPU_BUFFER_STORE [[COPY4]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY5]](s32), [[COPY6]], [[V_READFIRSTLANE_B32_]], 0, 0, -1 :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)
  ; CHECK:   G_AMDGPU_BUFFER_STORE [[COPY4]](s32), [[BUILD_VECTOR]](<4 x s32>), [[COPY5]](s32), [[COPY6]], [[V_READFIRSTLANE_B32_]], 0, 0, -1 :: (dereferenceable store 4 into custom "BufferResource", align 1, addrspace 4)

Show All 14 Linesdefine amdgpu_ps void @struct_buffer_store__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, float %val, i32 %vindex, i32 %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__vgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store__vgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr6

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr7
  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr7

  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)

  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF

  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
  ; CHECK:   [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %14, %bb.2
  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %14, %bb.2

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub0(s64), implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub0(s64), implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub1(s64), implicit $exec
  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub1(s64), implicit $exec

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll
Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %roundeven = call half @llvm.roundeven.f16(half %x)
  %roundeven = call half @llvm.roundeven.f16(half %x)

  ret half %roundeven
  ret half %roundeven

}
}




define <2 x half> @v_roundeven_v2f16(<2 x half> %x) {
define <2 x half> @v_roundeven_v2f16(<2 x half> %x) {

; GFX6-LABEL: v_roundeven_v2f16:
; GFX6-LABEL: v_roundeven_v2f16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-NEXT:    v_rndne_f32_e32 v1, v1
; GFX6-NEXT:    v_rndne_f32_e32 v0, v1

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_rndne_f32_e32 v1, v2

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX7-LABEL: v_roundeven_v2f16:
; GFX7-LABEL: v_roundeven_v2f16:

; GFX7:       ; %bb.0:
; GFX7:       ; %bb.0:

; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v0

; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1
; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX7-NEXT:    v_rndne_f32_e32 v1, v1
; GFX7-NEXT:    v_rndne_f32_e32 v0, v1

; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX7-NEXT:    v_rndne_f32_e32 v1, v2

; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX7-NEXT:    s_setpc_b64 s[30:31]
; GFX7-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_roundeven_v2f16:
; GFX8-LABEL: v_roundeven_v2f16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_rndne_f16_e32 v1, v0
; GFX8-NEXT:    v_rndne_f16_e32 v1, v0

; GFX8-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1

Show All 13 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %roundeven = call <2 x half> @llvm.roundeven.v2f16(<2 x half> %x)
  %roundeven = call <2 x half> @llvm.roundeven.v2f16(<2 x half> %x)

  ret <2 x half> %roundeven
  ret <2 x half> %roundeven

}
}




define <2 x half> @v_roundeven_v2f16_fneg(<2 x half> %x) {
define <2 x half> @v_roundeven_v2f16_fneg(<2 x half> %x) {

; GFX6-LABEL: v_roundeven_v2f16_fneg:
; GFX6-LABEL: v_roundeven_v2f16_fneg:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0

; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0

; GFX6-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
; GFX6-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v0
; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX6-NEXT:    v_rndne_f32_e32 v0, v1
; GFX6-NEXT:    v_rndne_f32_e32 v0, v1

; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX6-NEXT:    v_rndne_f32_e32 v1, v2
; GFX6-NEXT:    v_rndne_f32_e32 v1, v2

; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX7-LABEL: v_roundeven_v2f16_fneg:
; GFX7-LABEL: v_roundeven_v2f16_fneg:

; GFX7:       ; %bb.0:
; GFX7:       ; %bb.0:

; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff, v0

; GFX7-NEXT:    v_or_b32_e32 v0, v1, v0

; GFX7-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
; GFX7-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0

; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v0
; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v0

; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v0
; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v0

; GFX7-NEXT:    v_rndne_f32_e32 v0, v1
; GFX7-NEXT:    v_rndne_f32_e32 v0, v1

; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0

; GFX7-NEXT:    v_rndne_f32_e32 v1, v2
; GFX7-NEXT:    v_rndne_f32_e32 v1, v2

; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1
; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1

▲ Show 20 Lines • Show All 316 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,696 Lines • ▼ Show 20 Lines; GFX10-NEXT:    ; return to shader part epilog

  %cast = bitcast i16 %result to half
  %cast = bitcast i16 %result to half

  ret half %cast
  ret half %cast

}
}




define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {

; GFX6-LABEL: v_saddsat_v2i16:
; GFX6-LABEL: v_saddsat_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    s_brev_b32 s5, 1
; GFX6-NEXT:    s_brev_b32 s5, 1

; GFX6-NEXT:    v_min_i32_e32 v5, 0, v0
; GFX6-NEXT:    v_min_i32_e32 v5, 0, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s5, v5
; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s5, v5

; GFX6-NEXT:    s_brev_b32 s4, -2
; GFX6-NEXT:    s_brev_b32 s4, -2

; GFX6-NEXT:    v_max_i32_e32 v4, 0, v0
; GFX6-NEXT:    v_max_i32_e32 v4, 0, v0

; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s4, v4
; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s4, v4

; GFX6-NEXT:    v_max_i32_e32 v2, v5, v2
; GFX6-NEXT:    v_max_i32_e32 v1, v5, v1

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_min_i32_e32 v1, v1, v4

; GFX6-NEXT:    v_min_i32_e32 v2, v2, v4
; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v2

; GFX6-NEXT:    v_min_i32_e32 v4, 0, v1
; GFX6-NEXT:    v_min_i32_e32 v4, 0, v1

; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2

; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3

; GFX6-NEXT:    v_max_i32_e32 v3, 0, v1
; GFX6-NEXT:    v_max_i32_e32 v3, 0, v1

; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s5, v4
; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s5, v4

; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s4, v3

; GFX6-NEXT:    v_max_i32_e32 v2, v4, v2
; GFX6-NEXT:    v_max_i32_e32 v2, v4, v2

; GFX6-NEXT:    v_min_i32_e32 v2, v2, v3
; GFX6-NEXT:    v_min_i32_e32 v2, v2, v3

; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v2

; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 16, v0

Show All 37 Lines
; GFX10-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]

  %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
  %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)

  ret <2 x i16> %result
  ret <2 x i16> %result

}
}




define amdgpu_ps i32 @s_saddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
define amdgpu_ps i32 @s_saddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {

; GFX6-LABEL: s_saddsat_v2i16:
; GFX6-LABEL: s_saddsat_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_lshr_b32 s2, s0, 16

; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

; GFX6-NEXT:    s_brev_b32 s5, 1
; GFX6-NEXT:    s_brev_b32 s5, 1

; GFX6-NEXT:    s_min_i32 s7, s0, 0
; GFX6-NEXT:    s_min_i32 s7, s0, 0

; GFX6-NEXT:    s_lshl_b32 s2, s2, 16
; GFX6-NEXT:    s_lshr_b32 s3, s1, 16

; GFX6-NEXT:    s_lshl_b32 s1, s1, 16

; GFX6-NEXT:    s_sub_i32 s7, s5, s7
; GFX6-NEXT:    s_sub_i32 s7, s5, s7

; GFX6-NEXT:    s_brev_b32 s4, -2
; GFX6-NEXT:    s_brev_b32 s4, -2

; GFX6-NEXT:    s_max_i32 s6, s0, 0
; GFX6-NEXT:    s_max_i32 s6, s0, 0

; GFX6-NEXT:    s_sub_i32 s6, s4, s6
; GFX6-NEXT:    s_sub_i32 s6, s4, s6

; GFX6-NEXT:    s_max_i32 s2, s7, s2
; GFX6-NEXT:    s_max_i32 s1, s7, s1

; GFX6-NEXT:    s_min_i32 s2, s2, s6
; GFX6-NEXT:    s_min_i32 s1, s1, s6

; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
; GFX6-NEXT:    s_add_i32 s0, s0, s1

; GFX6-NEXT:    s_add_i32 s0, s0, s2
; GFX6-NEXT:    s_lshl_b32 s1, s2, 16

; GFX6-NEXT:    s_lshl_b32 s2, s3, 16
; GFX6-NEXT:    s_lshl_b32 s2, s3, 16

; GFX6-NEXT:    s_max_i32 s3, s1, 0
; GFX6-NEXT:    s_max_i32 s3, s1, 0

; GFX6-NEXT:    s_sub_i32 s3, s4, s3
; GFX6-NEXT:    s_sub_i32 s3, s4, s3

; GFX6-NEXT:    s_min_i32 s4, s1, 0
; GFX6-NEXT:    s_min_i32 s4, s1, 0

; GFX6-NEXT:    s_sub_i32 s4, s5, s4
; GFX6-NEXT:    s_sub_i32 s4, s5, s4

; GFX6-NEXT:    s_max_i32 s2, s4, s2
; GFX6-NEXT:    s_max_i32 s2, s4, s2

; GFX6-NEXT:    s_min_i32 s2, s2, s3
; GFX6-NEXT:    s_min_i32 s2, s2, s3

; GFX6-NEXT:    s_add_i32 s1, s1, s2
; GFX6-NEXT:    s_add_i32 s1, s1, s2

▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines; GFX10-NEXT:    ; return to shader part epilog

  %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
  %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)

  %cast = bitcast <2 x i16> %result to i32
  %cast = bitcast <2 x i16> %result to i32

  ret i32 %cast
  ret i32 %cast

}
}




define amdgpu_ps float @saddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
define amdgpu_ps float @saddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {

; GFX6-LABEL: saddsat_v2i16_sv:
; GFX6-LABEL: saddsat_v2i16_sv:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

; GFX6-NEXT:    s_brev_b32 s3, 1
; GFX6-NEXT:    s_brev_b32 s3, 1

; GFX6-NEXT:    s_min_i32 s5, s0, 0
; GFX6-NEXT:    s_min_i32 s5, s0, 0

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    s_sub_i32 s5, s3, s5
; GFX6-NEXT:    s_sub_i32 s5, s3, s5

; GFX6-NEXT:    s_brev_b32 s2, -2
; GFX6-NEXT:    s_brev_b32 s2, -2

; GFX6-NEXT:    s_max_i32 s4, s0, 0
; GFX6-NEXT:    s_max_i32 s4, s0, 0

; GFX6-NEXT:    s_sub_i32 s4, s2, s4
; GFX6-NEXT:    s_sub_i32 s4, s2, s4

; GFX6-NEXT:    v_max_i32_e32 v0, s5, v0
; GFX6-NEXT:    v_max_i32_e32 v0, s5, v0

; GFX6-NEXT:    v_min_i32_e32 v0, s4, v0
; GFX6-NEXT:    v_min_i32_e32 v0, s4, v0

; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v0

▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines; GFX10-NEXT:    ; return to shader part epilog

  %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
  %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)

  %cast = bitcast <2 x i16> %result to float
  %cast = bitcast <2 x i16> %result to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {

; GFX6-LABEL: saddsat_v2i16_vs:
; GFX6-LABEL: saddsat_v2i16_vs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    s_brev_b32 s3, 1
; GFX6-NEXT:    s_brev_b32 s3, 1

; GFX6-NEXT:    v_min_i32_e32 v3, 0, v0
; GFX6-NEXT:    v_min_i32_e32 v3, 0, v0

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s3, v3
; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s3, v3

; GFX6-NEXT:    s_brev_b32 s2, -2
; GFX6-NEXT:    s_brev_b32 s2, -2

; GFX6-NEXT:    v_max_i32_e32 v2, 0, v0
; GFX6-NEXT:    v_max_i32_e32 v2, 0, v0

; GFX6-NEXT:    v_max_i32_e32 v3, s0, v3
; GFX6-NEXT:    v_max_i32_e32 v3, s0, v3

; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_min_i32_e32 v2, v3, v2
; GFX6-NEXT:    v_min_i32_e32 v2, v3, v2

▲ Show 20 Lines • Show All 3,857 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
Show First 20 Lines • Show All 448 Lines • ▼ Show 20 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %ext = zext i16 %and to i32
  %ext = zext i16 %and to i32

  %shl = shl i32 %ext, 2
  %shl = shl i32 %ext, 2

  ret i32 %shl
  ret i32 %shl

}
}




define amdgpu_ps <2 x i32> @s_shl_v2i32_zext_v2i16(<2 x i16> inreg %x) {
define amdgpu_ps <2 x i32> @s_shl_v2i32_zext_v2i16(<2 x i16> inreg %x) {

; GFX7-LABEL: s_shl_v2i32_zext_v2i16:
; GFX7-LABEL: s_shl_v2i32_zext_v2i16:

; GFX7:       ; %bb.0:
; GFX7:       ; %bb.0:

; GFX7-NEXT:    s_mov_b32 s2, 0xffff

; GFX7-NEXT:    s_lshl_b32 s1, s1, 16

; GFX7-NEXT:    s_and_b32 s0, s0, s2

; GFX7-NEXT:    s_or_b32 s0, s1, s0

; GFX7-NEXT:    s_and_b32 s0, s0, 0x3fff3fff
; GFX7-NEXT:    s_and_b32 s0, s0, 0x3fff3fff

; GFX7-NEXT:    s_lshr_b32 s1, s0, 16
; GFX7-NEXT:    s_lshr_b32 s1, s0, 16

; GFX7-NEXT:    s_and_b32 s0, s0, s2
; GFX7-NEXT:    s_and_b32 s0, s0, 0xffff

; GFX7-NEXT:    s_lshl_b32 s0, s0, 2
; GFX7-NEXT:    s_lshl_b32 s0, s0, 2

; GFX7-NEXT:    s_lshl_b32 s1, s1, 2
; GFX7-NEXT:    s_lshl_b32 s1, s1, 2

; GFX7-NEXT:    ; return to shader part epilog
; GFX7-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: s_shl_v2i32_zext_v2i16:
; GFX8-LABEL: s_shl_v2i32_zext_v2i16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_movk_i32 s2, 0x3fff
; GFX8-NEXT:    s_movk_i32 s2, 0x3fff

; GFX8-NEXT:    s_mov_b32 s4, 0xffff
; GFX8-NEXT:    s_mov_b32 s4, 0xffff

Show All 25 Lines
; fails to handle the vector splat. The post-legalizer sees the zext
; fails to handle the vector splat. The post-legalizer sees the zext

; legalized into the and. This is probably not that important, since
; legalized into the and. This is probably not that important, since

; we really do this combine in the machine level for lowered
; we really do this combine in the machine level for lowered

; getelementptrs.
; getelementptrs.

define <2 x i32> @v_shl_v2i32_zext_v2i16(<2 x i16> %x) {
define <2 x i32> @v_shl_v2i32_zext_v2i16(<2 x i16> %x) {

; GFX7-LABEL: v_shl_v2i32_zext_v2i16:
; GFX7-LABEL: v_shl_v2i32_zext_v2i16:

; GFX7:       ; %bb.0:
; GFX7:       ; %bb.0:

; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX7-NEXT:    v_mov_b32_e32 v2, 0xffff

; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX7-NEXT:    v_and_b32_e32 v0, v0, v2

; GFX7-NEXT:    v_or_b32_e32 v0, v1, v0

; GFX7-NEXT:    v_and_b32_e32 v0, 0x3fff3fff, v0
; GFX7-NEXT:    v_and_b32_e32 v0, 0x3fff3fff, v0

; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX7-NEXT:    v_and_b32_e32 v0, v0, v2
; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff, v0

; GFX7-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 2, v1

; GFX7-NEXT:    s_setpc_b64 s[30:31]
; GFX7-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_shl_v2i32_zext_v2i16:
; GFX8-LABEL: v_shl_v2i32_zext_v2i16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_and_b32_e32 v1, 0x3fff3fff, v0
; GFX8-NEXT:    v_and_b32_e32 v1, 0x3fff3fff, v0

Show All 22 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
Show First 20 Lines • Show All 479 Lines • ▼ Show 20 Lines; GFX9-NEXT:    ; return to shader part epilog

  %cast = bitcast i16 %result to half
  %cast = bitcast i16 %result to half

  ret half %cast
  ret half %cast

}
}




define <2 x i16> @v_shl_v2i16(<2 x i16> %value, <2 x i16> %amount) {
define <2 x i16> @v_shl_v2i16(<2 x i16> %value, <2 x i16> %amount) {

; GFX6-LABEL: v_shl_v2i16:
; GFX6-LABEL: v_shl_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    s_mov_b32 s4, 0xffff
; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1

; GFX6-NEXT:    v_and_b32_e32 v2, s4, v2
; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1

; GFX6-NEXT:    v_and_b32_e32 v2, s4, v3
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v1, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v3, v2

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_shl_v2i16:
; GFX8-LABEL: v_shl_v2i16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_lshlrev_b16_e32 v2, v1, v0
; GFX8-NEXT:    v_lshlrev_b16_e32 v2, v1, v0

; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1

; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0

; GFX8-NEXT:    s_setpc_b64 s[30:31]
; GFX8-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX9-LABEL: v_shl_v2i16:
; GFX9-LABEL: v_shl_v2i16:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v1, v0
; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v1, v0

; GFX9-NEXT:    s_setpc_b64 s[30:31]
; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %result = shl <2 x i16> %value, %amount
  %result = shl <2 x i16> %value, %amount

  ret <2 x i16> %result
  ret <2 x i16> %result

}
}




define <2 x i16> @v_shl_v2i16_15(<2 x i16> %value) {
define <2 x i16> @v_shl_v2i16_15(<2 x i16> %value) {

; GFX6-LABEL: v_shl_v2i16_15:
; GFX6-LABEL: v_shl_v2i16_15:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 15, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 15, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 15, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_shl_v2i16_15:
; GFX8-LABEL: v_shl_v2i16_15:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-NEXT:    v_mov_b32_e32 v2, 15
; GFX8-NEXT:    v_mov_b32_e32 v2, 15

Show All 10 Lines; GFX9-NEXT:    s_setpc_b64 s[30:31]

  %result = shl <2 x i16> %value, <i16 15, i16 15>
  %result = shl <2 x i16> %value, <i16 15, i16 15>

  ret <2 x i16> %result
  ret <2 x i16> %result

}
}




define amdgpu_ps i32 @s_shl_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {
define amdgpu_ps i32 @s_shl_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {

; GFX6-LABEL: s_shl_v2i16:
; GFX6-LABEL: s_shl_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_mov_b32 s4, 0xffff
; GFX6-NEXT:    s_mov_b32 s4, 0xffff

; GFX6-NEXT:    s_and_b32 s2, s2, s4
; GFX6-NEXT:    s_lshr_b32 s3, s1, 16

; GFX6-NEXT:    s_lshl_b32 s0, s0, s2
; GFX6-NEXT:    s_lshr_b32 s2, s0, 16

; GFX6-NEXT:    s_and_b32 s2, s3, s4
; GFX6-NEXT:    s_and_b32 s1, s1, s4

; GFX6-NEXT:    s_lshl_b32 s1, s1, s2
; GFX6-NEXT:    s_lshl_b32 s0, s0, s1

; GFX6-NEXT:    s_lshl_b32 s1, s2, s3

; GFX6-NEXT:    s_and_b32 s1, s1, s4
; GFX6-NEXT:    s_and_b32 s1, s1, s4

; GFX6-NEXT:    s_and_b32 s0, s0, s4
; GFX6-NEXT:    s_and_b32 s0, s0, s4

; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
; GFX6-NEXT:    s_lshl_b32 s1, s1, 16

; GFX6-NEXT:    s_or_b32 s0, s0, s1
; GFX6-NEXT:    s_or_b32 s0, s0, s1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: s_shl_v2i16:
; GFX8-LABEL: s_shl_v2i16:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

Show All 20 Lines; GFX9-NEXT:    ; return to shader part epilog

  %result = shl <2 x i16> %value, %amount
  %result = shl <2 x i16> %value, %amount

  %cast = bitcast <2 x i16> %result to i32
  %cast = bitcast <2 x i16> %result to i32

  ret i32 %cast
  ret i32 %cast

}
}




define amdgpu_ps float @shl_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {
define amdgpu_ps float @shl_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {

; GFX6-LABEL: shl_v2i16_sv:
; GFX6-LABEL: shl_v2i16_sv:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    s_mov_b32 s2, 0xffff
; GFX6-NEXT:    s_mov_b32 s2, 0xffff

; GFX6-NEXT:    v_and_b32_e32 v1, s2, v1

; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0
; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0

; GFX6-NEXT:    v_lshl_b32_e32 v1, s1, v1
; GFX6-NEXT:    v_lshl_b32_e32 v1, s1, v1

; GFX6-NEXT:    v_lshl_b32_e32 v0, s0, v0
; GFX6-NEXT:    v_lshl_b32_e32 v0, s0, v0

; GFX6-NEXT:    v_and_b32_e32 v1, s2, v1
; GFX6-NEXT:    v_and_b32_e32 v1, s2, v1

; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0
; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

Show All 14 Lines; GFX9-NEXT:    ; return to shader part epilog

  %result = shl <2 x i16> %value, %amount
  %result = shl <2 x i16> %value, %amount

  %cast = bitcast <2 x i16> %result to float
  %cast = bitcast <2 x i16> %result to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @shl_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {
define amdgpu_ps float @shl_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {

; GFX6-LABEL: shl_v2i16_vs:
; GFX6-LABEL: shl_v2i16_vs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    s_mov_b32 s2, 0xffff
; GFX6-NEXT:    s_mov_b32 s2, 0xffff

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s1, v1

; GFX6-NEXT:    s_and_b32 s0, s0, s2
; GFX6-NEXT:    s_and_b32 s0, s0, s2

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s0, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s0, v0

; GFX6-NEXT:    s_and_b32 s0, s1, s2

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s0, v1

; GFX6-NEXT:    v_and_b32_e32 v1, s2, v1
; GFX6-NEXT:    v_and_b32_e32 v1, s2, v1

; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0
; GFX6-NEXT:    v_and_b32_e32 v0, s2, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: shl_v2i16_vs:
; GFX8-LABEL: shl_v2i16_vs:

; GFX8:       ; %bb.0:
; GFX8:       ; %bb.0:

▲ Show 20 Lines • Show All 559 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,682 Lines • ▼ Show 20 Lines; GFX10-NEXT:    ; return to shader part epilog

  %cast = bitcast i16 %result to half
  %cast = bitcast i16 %result to half

  ret half %cast
  ret half %cast

}
}




define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {

; GFX6-LABEL: v_ssubsat_v2i16:
; GFX6-LABEL: v_ssubsat_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    s_brev_b32 s4, -2
; GFX6-NEXT:    s_brev_b32 s4, -2

; GFX6-NEXT:    v_max_i32_e32 v4, -1, v0
; GFX6-NEXT:    v_max_i32_e32 v4, -1, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s4, v4
; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s4, v4

; GFX6-NEXT:    s_brev_b32 s5, 1
; GFX6-NEXT:    s_brev_b32 s5, 1

; GFX6-NEXT:    v_min_i32_e32 v5, -1, v0
; GFX6-NEXT:    v_min_i32_e32 v5, -1, v0

; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s5, v5
; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s5, v5

; GFX6-NEXT:    v_max_i32_e32 v2, v4, v2
; GFX6-NEXT:    v_max_i32_e32 v1, v4, v1

; GFX6-NEXT:    v_min_i32_e32 v2, v2, v5
; GFX6-NEXT:    v_min_i32_e32 v1, v1, v5

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1

; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v2

; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3

; GFX6-NEXT:    v_max_i32_e32 v3, -1, v1
; GFX6-NEXT:    v_max_i32_e32 v3, -1, v1

; GFX6-NEXT:    v_min_i32_e32 v4, -1, v1
; GFX6-NEXT:    v_min_i32_e32 v4, -1, v1

; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s4, v3

; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s5, v4
; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s5, v4

; GFX6-NEXT:    v_max_i32_e32 v2, v3, v2
; GFX6-NEXT:    v_max_i32_e32 v2, v3, v2

; GFX6-NEXT:    v_min_i32_e32 v2, v2, v4
; GFX6-NEXT:    v_min_i32_e32 v2, v2, v4

; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2

Show All 38 Lines
; GFX10-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]

  %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
  %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)

  ret <2 x i16> %result
  ret <2 x i16> %result

}
}




define amdgpu_ps i32 @s_ssubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
define amdgpu_ps i32 @s_ssubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {

; GFX6-LABEL: s_ssubsat_v2i16:
; GFX6-LABEL: s_ssubsat_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_lshr_b32 s2, s0, 16

; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

; GFX6-NEXT:    s_brev_b32 s4, -2
; GFX6-NEXT:    s_brev_b32 s4, -2

; GFX6-NEXT:    s_max_i32 s6, s0, -1
; GFX6-NEXT:    s_max_i32 s6, s0, -1

; GFX6-NEXT:    s_lshl_b32 s2, s2, 16
; GFX6-NEXT:    s_lshr_b32 s3, s1, 16

; GFX6-NEXT:    s_lshl_b32 s1, s1, 16

; GFX6-NEXT:    s_sub_i32 s6, s6, s4
; GFX6-NEXT:    s_sub_i32 s6, s6, s4

; GFX6-NEXT:    s_brev_b32 s5, 1
; GFX6-NEXT:    s_brev_b32 s5, 1

; GFX6-NEXT:    s_min_i32 s7, s0, -1
; GFX6-NEXT:    s_min_i32 s7, s0, -1

; GFX6-NEXT:    s_sub_i32 s7, s7, s5
; GFX6-NEXT:    s_sub_i32 s7, s7, s5

; GFX6-NEXT:    s_max_i32 s2, s6, s2
; GFX6-NEXT:    s_max_i32 s1, s6, s1

; GFX6-NEXT:    s_min_i32 s2, s2, s7
; GFX6-NEXT:    s_min_i32 s1, s1, s7

; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
; GFX6-NEXT:    s_sub_i32 s0, s0, s1

; GFX6-NEXT:    s_sub_i32 s0, s0, s2
; GFX6-NEXT:    s_lshl_b32 s1, s2, 16

; GFX6-NEXT:    s_lshl_b32 s2, s3, 16
; GFX6-NEXT:    s_lshl_b32 s2, s3, 16

; GFX6-NEXT:    s_max_i32 s3, s1, -1
; GFX6-NEXT:    s_max_i32 s3, s1, -1

; GFX6-NEXT:    s_sub_i32 s3, s3, s4
; GFX6-NEXT:    s_sub_i32 s3, s3, s4

; GFX6-NEXT:    s_min_i32 s4, s1, -1
; GFX6-NEXT:    s_min_i32 s4, s1, -1

; GFX6-NEXT:    s_sub_i32 s4, s4, s5
; GFX6-NEXT:    s_sub_i32 s4, s4, s5

; GFX6-NEXT:    s_max_i32 s2, s3, s2
; GFX6-NEXT:    s_max_i32 s2, s3, s2

; GFX6-NEXT:    s_min_i32 s2, s2, s4
; GFX6-NEXT:    s_min_i32 s2, s2, s4

; GFX6-NEXT:    s_sub_i32 s1, s1, s2
; GFX6-NEXT:    s_sub_i32 s1, s1, s2

▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines; GFX10-NEXT:    ; return to shader part epilog

  %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
  %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)

  %cast = bitcast <2 x i16> %result to i32
  %cast = bitcast <2 x i16> %result to i32

  ret i32 %cast
  ret i32 %cast

}
}




define amdgpu_ps float @ssubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
define amdgpu_ps float @ssubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {

; GFX6-LABEL: ssubsat_v2i16_sv:
; GFX6-LABEL: ssubsat_v2i16_sv:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

; GFX6-NEXT:    s_brev_b32 s2, -2
; GFX6-NEXT:    s_brev_b32 s2, -2

; GFX6-NEXT:    s_max_i32 s4, s0, -1
; GFX6-NEXT:    s_max_i32 s4, s0, -1

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    s_sub_i32 s4, s4, s2
; GFX6-NEXT:    s_sub_i32 s4, s4, s2

; GFX6-NEXT:    s_brev_b32 s3, 1
; GFX6-NEXT:    s_brev_b32 s3, 1

; GFX6-NEXT:    s_min_i32 s5, s0, -1
; GFX6-NEXT:    s_min_i32 s5, s0, -1

; GFX6-NEXT:    s_sub_i32 s5, s5, s3
; GFX6-NEXT:    s_sub_i32 s5, s5, s3

; GFX6-NEXT:    v_max_i32_e32 v0, s4, v0
; GFX6-NEXT:    v_max_i32_e32 v0, s4, v0

; GFX6-NEXT:    v_min_i32_e32 v0, s5, v0
; GFX6-NEXT:    v_min_i32_e32 v0, s5, v0

; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0

▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines; GFX10-NEXT:    ; return to shader part epilog

  %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
  %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)

  %cast = bitcast <2 x i16> %result to float
  %cast = bitcast <2 x i16> %result to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @ssubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
define amdgpu_ps float @ssubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {

; GFX6-LABEL: ssubsat_v2i16_vs:
; GFX6-LABEL: ssubsat_v2i16_vs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    s_brev_b32 s2, -2
; GFX6-NEXT:    s_brev_b32 s2, -2

; GFX6-NEXT:    v_max_i32_e32 v2, -1, v0
; GFX6-NEXT:    v_max_i32_e32 v2, -1, v0

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s2, v2
; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s2, v2

; GFX6-NEXT:    s_brev_b32 s3, 1
; GFX6-NEXT:    s_brev_b32 s3, 1

; GFX6-NEXT:    v_min_i32_e32 v3, -1, v0
; GFX6-NEXT:    v_min_i32_e32 v3, -1, v0

; GFX6-NEXT:    v_max_i32_e32 v2, s0, v2
; GFX6-NEXT:    v_max_i32_e32 v2, s0, v2

; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s3, v3
; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s3, v3

; GFX6-NEXT:    v_min_i32_e32 v2, v2, v3
; GFX6-NEXT:    v_min_i32_e32 v2, v2, v3

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

▲ Show 20 Lines • Show All 3,857 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
Show First 20 Lines • Show All 1,742 Lines • ▼ Show 20 Lines; GFX10-NEXT:    ; return to shader part epilog

  %cast = bitcast i16 %result to half
  %cast = bitcast i16 %result to half

  ret half %cast
  ret half %cast

}
}




define <2 x i16> @v_uaddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
define <2 x i16> @v_uaddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {

; GFX6-LABEL: v_uaddsat_v2i16:
; GFX6-LABEL: v_uaddsat_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1

; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v0

; GFX6-NEXT:    v_min_u32_e32 v2, v4, v2

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v0

; GFX6-NEXT:    v_min_u32_e32 v1, v4, v1

; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v2

; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3

; GFX6-NEXT:    v_xor_b32_e32 v3, -1, v1
; GFX6-NEXT:    v_xor_b32_e32 v3, -1, v1

; GFX6-NEXT:    v_min_u32_e32 v2, v3, v2
; GFX6-NEXT:    v_min_u32_e32 v2, v3, v2

; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v2

; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

Show All 21 Lines
; GFX10-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]

  %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
  %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)

  ret <2 x i16> %result
  ret <2 x i16> %result

}
}




define amdgpu_ps i32 @s_uaddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
define amdgpu_ps i32 @s_uaddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {

; GFX6-LABEL: s_uaddsat_v2i16:
; GFX6-LABEL: s_uaddsat_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_lshr_b32 s2, s0, 16

; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

; GFX6-NEXT:    s_lshl_b32 s2, s2, 16
; GFX6-NEXT:    s_lshr_b32 s3, s1, 16

; GFX6-NEXT:    s_not_b32 s4, s0

; GFX6-NEXT:    s_min_u32 s2, s4, s2

; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
; GFX6-NEXT:    s_lshl_b32 s1, s1, 16

; GFX6-NEXT:    s_add_i32 s0, s0, s2
; GFX6-NEXT:    s_not_b32 s4, s0

; GFX6-NEXT:    s_min_u32 s1, s4, s1

; GFX6-NEXT:    s_add_i32 s0, s0, s1

; GFX6-NEXT:    s_lshl_b32 s1, s2, 16

; GFX6-NEXT:    s_lshl_b32 s2, s3, 16
; GFX6-NEXT:    s_lshl_b32 s2, s3, 16

; GFX6-NEXT:    s_not_b32 s3, s1
; GFX6-NEXT:    s_not_b32 s3, s1

; GFX6-NEXT:    s_min_u32 s2, s3, s2
; GFX6-NEXT:    s_min_u32 s2, s3, s2

; GFX6-NEXT:    s_add_i32 s1, s1, s2
; GFX6-NEXT:    s_add_i32 s1, s1, s2

; GFX6-NEXT:    s_lshr_b32 s1, s1, 16
; GFX6-NEXT:    s_lshr_b32 s1, s1, 16

; GFX6-NEXT:    s_lshr_b32 s0, s0, 16
; GFX6-NEXT:    s_lshr_b32 s0, s0, 16

; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
; GFX6-NEXT:    s_lshl_b32 s1, s1, 16

; GFX6-NEXT:    s_or_b32 s0, s0, s1
; GFX6-NEXT:    s_or_b32 s0, s0, s1

Show All 28 Lines; GFX10-NEXT:    ; return to shader part epilog

  %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
  %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)

  %cast = bitcast <2 x i16> %result to i32
  %cast = bitcast <2 x i16> %result to i32

  ret i32 %cast
  ret i32 %cast

}
}




define amdgpu_ps float @uaddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
define amdgpu_ps float @uaddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {

; GFX6-LABEL: uaddsat_v2i16_sv:
; GFX6-LABEL: uaddsat_v2i16_sv:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    s_not_b32 s2, s0
; GFX6-NEXT:    s_not_b32 s2, s0

; GFX6-NEXT:    v_min_u32_e32 v0, s2, v0
; GFX6-NEXT:    v_min_u32_e32 v0, s2, v0

; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v0

; GFX6-NEXT:    s_lshl_b32 s0, s1, 16
; GFX6-NEXT:    s_lshl_b32 s0, s1, 16

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    s_not_b32 s1, s0
; GFX6-NEXT:    s_not_b32 s1, s0

; GFX6-NEXT:    v_min_u32_e32 v1, s1, v1
; GFX6-NEXT:    v_min_u32_e32 v1, s1, v1

Show All 27 Lines; GFX10-NEXT:    ; return to shader part epilog

  %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
  %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)

  %cast = bitcast <2 x i16> %result to float
  %cast = bitcast <2 x i16> %result to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @uaddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
define amdgpu_ps float @uaddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {

; GFX6-LABEL: uaddsat_v2i16_vs:
; GFX6-LABEL: uaddsat_v2i16_vs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v0
; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v0

; GFX6-NEXT:    v_min_u32_e32 v2, s0, v2
; GFX6-NEXT:    v_min_u32_e32 v2, s0, v2

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2

; GFX6-NEXT:    s_lshl_b32 s0, s1, 16
; GFX6-NEXT:    s_lshl_b32 s0, s1, 16

; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v1
; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v1

; GFX6-NEXT:    v_min_u32_e32 v2, s0, v2
; GFX6-NEXT:    v_min_u32_e32 v2, s0, v2

▲ Show 20 Lines • Show All 1,925 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
Show First 20 Lines • Show All 1,656 Lines • ▼ Show 20 Lines; GFX10-NEXT:    ; return to shader part epilog

  %cast = bitcast i16 %result to half
  %cast = bitcast i16 %result to half

  ret half %cast
  ret half %cast

}
}




define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {

; GFX6-LABEL: v_usubsat_v2i16:
; GFX6-LABEL: v_usubsat_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v1

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2

; GFX6-NEXT:    v_min_u32_e32 v2, v0, v2

; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_min_u32_e32 v1, v0, v1

; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v2

; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3

; GFX6-NEXT:    v_min_u32_e32 v2, v1, v2
; GFX6-NEXT:    v_min_u32_e32 v2, v1, v2

; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2

; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    s_setpc_b64 s[30:31]
; GFX6-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX8-LABEL: v_usubsat_v2i16:
; GFX8-LABEL: v_usubsat_v2i16:

Show All 20 Lines
; GFX10-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]

  %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
  %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)

  ret <2 x i16> %result
  ret <2 x i16> %result

}
}




define amdgpu_ps i32 @s_usubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
define amdgpu_ps i32 @s_usubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {

; GFX6-LABEL: s_usubsat_v2i16:
; GFX6-LABEL: s_usubsat_v2i16:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    s_lshr_b32 s2, s0, 16

; GFX6-NEXT:    s_lshr_b32 s3, s1, 16

; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

; GFX6-NEXT:    s_lshl_b32 s2, s2, 16

; GFX6-NEXT:    s_min_u32 s2, s0, s2

; GFX6-NEXT:    s_sub_i32 s0, s0, s2

; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
; GFX6-NEXT:    s_lshl_b32 s1, s1, 16

; GFX6-NEXT:    s_min_u32 s1, s0, s1

; GFX6-NEXT:    s_sub_i32 s0, s0, s1

; GFX6-NEXT:    s_lshl_b32 s1, s2, 16

; GFX6-NEXT:    s_lshl_b32 s2, s3, 16
; GFX6-NEXT:    s_lshl_b32 s2, s3, 16

; GFX6-NEXT:    s_min_u32 s2, s1, s2
; GFX6-NEXT:    s_min_u32 s2, s1, s2

; GFX6-NEXT:    s_sub_i32 s1, s1, s2
; GFX6-NEXT:    s_sub_i32 s1, s1, s2

; GFX6-NEXT:    s_lshr_b32 s1, s1, 16
; GFX6-NEXT:    s_lshr_b32 s1, s1, 16

; GFX6-NEXT:    s_lshr_b32 s0, s0, 16
; GFX6-NEXT:    s_lshr_b32 s0, s0, 16

; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
; GFX6-NEXT:    s_lshl_b32 s1, s1, 16

; GFX6-NEXT:    s_or_b32 s0, s0, s1
; GFX6-NEXT:    s_or_b32 s0, s0, s1

; GFX6-NEXT:    ; return to shader part epilog
; GFX6-NEXT:    ; return to shader part epilog

Show All 27 Lines; GFX10-NEXT:    ; return to shader part epilog

  %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
  %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)

  %cast = bitcast <2 x i16> %result to i32
  %cast = bitcast <2 x i16> %result to i32

  ret i32 %cast
  ret i32 %cast

}
}




define amdgpu_ps float @usubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
define amdgpu_ps float @usubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {

; GFX6-LABEL: usubsat_v2i16_sv:
; GFX6-LABEL: usubsat_v2i16_sv:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    v_min_u32_e32 v0, s0, v0
; GFX6-NEXT:    v_min_u32_e32 v0, s0, v0

; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0

; GFX6-NEXT:    s_lshl_b32 s0, s1, 16
; GFX6-NEXT:    s_lshl_b32 s0, s1, 16

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    v_min_u32_e32 v1, s0, v1
; GFX6-NEXT:    v_min_u32_e32 v1, s0, v1

; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s0, v1

Show All 26 Lines; GFX10-NEXT:    ; return to shader part epilog

  %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
  %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)

  %cast = bitcast <2 x i16> %result to float
  %cast = bitcast <2 x i16> %result to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @usubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
define amdgpu_ps float @usubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {

; GFX6-LABEL: usubsat_v2i16_vs:
; GFX6-LABEL: usubsat_v2i16_vs:

; GFX6:       ; %bb.0:
; GFX6:       ; %bb.0:

; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0

; GFX6-NEXT:    s_lshr_b32 s1, s0, 16

; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0

; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

; GFX6-NEXT:    v_min_u32_e32 v2, s0, v0
; GFX6-NEXT:    v_min_u32_e32 v2, s0, v0

; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; GFX6-NEXT:    s_lshl_b32 s0, s1, 16
; GFX6-NEXT:    s_lshl_b32 s0, s1, 16

; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2

; GFX6-NEXT:    v_min_u32_e32 v2, s0, v1
; GFX6-NEXT:    v_min_u32_e32 v2, s0, v1

; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2

▲ Show 20 Lines • Show All 1,888 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
Show All 13 Linesentry:

  %r0.val = xor i32 %xor, -1
  %r0.val = xor i32 %xor, -1

  ret i32 %r0.val
  ret i32 %r0.val

}
}




; FIXME: fails to match
; FIXME: fails to match

define amdgpu_ps i32 @scalar_xnor_v2i16_one_use(<2 x i16> inreg %a, <2 x i16> inreg %b) {
define amdgpu_ps i32 @scalar_xnor_v2i16_one_use(<2 x i16> inreg %a, <2 x i16> inreg %b) {

; GFX7-LABEL: scalar_xnor_v2i16_one_use:
; GFX7-LABEL: scalar_xnor_v2i16_one_use:

; GFX7:       ; %bb.0: ; %entry
; GFX7:       ; %bb.0: ; %entry

; GFX7-NEXT:    s_mov_b32 s4, 0xffff

; GFX7-NEXT:    s_lshl_b32 s1, s1, 16

; GFX7-NEXT:    s_and_b32 s0, s0, s4

; GFX7-NEXT:    s_or_b32 s0, s1, s0

; GFX7-NEXT:    s_lshl_b32 s1, s3, 16

; GFX7-NEXT:    s_and_b32 s2, s2, s4

; GFX7-NEXT:    s_or_b32 s1, s1, s2

; GFX7-NEXT:    s_xor_b32 s0, s0, s1
; GFX7-NEXT:    s_xor_b32 s0, s0, s1

; GFX7-NEXT:    s_xor_b32 s0, s0, -1
; GFX7-NEXT:    s_xor_b32 s0, s0, -1

; GFX7-NEXT:    ; return to shader part epilog
; GFX7-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: scalar_xnor_v2i16_one_use:
; GFX8-LABEL: scalar_xnor_v2i16_one_use:

; GFX8:       ; %bb.0: ; %entry
; GFX8:       ; %bb.0: ; %entry

; GFX8-NEXT:    s_xor_b32 s0, s0, s1
; GFX8-NEXT:    s_xor_b32 s0, s0, s1

; GFX8-NEXT:    s_mov_b32 s2, 0xffff
; GFX8-NEXT:    s_mov_b32 s2, 0xffff

▲ Show 20 Lines • Show All 328 Lines • Show Last 20 Lines