diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -746,6 +746,8 @@ defm vfwnmsac : RISCVTernaryWide; defm vfsqrt : RISCVUnaryAA; + defm vfrsqrte7 : RISCVUnaryAA; + defm vfrece7 : RISCVUnaryAA; defm vfmin : RISCVBinaryAAX; defm vfmax : RISCVBinaryAAX; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -2877,6 +2877,16 @@ defm PseudoVFSQRT : VPseudoUnaryV_V; //===----------------------------------------------------------------------===// +// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction +//===----------------------------------------------------------------------===// +defm PseudoVFRSQRTE7 : VPseudoUnaryV_V; + +//===----------------------------------------------------------------------===// +// 14.10. Vector Floating-Point Reciprocal Estimate Instruction +//===----------------------------------------------------------------------===// +defm PseudoVFRECE7 : VPseudoUnaryV_V; + +//===----------------------------------------------------------------------===// // 14.11. Vector Floating-Point Min/Max Instructions //===----------------------------------------------------------------------===// defm PseudoVFMIN : VPseudoBinaryV_VV_VX; @@ -3532,6 +3542,16 @@ defm "" : VPatUnaryV_V<"int_riscv_vfsqrt", "PseudoVFSQRT", AllFloatVectors>; //===----------------------------------------------------------------------===// +// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction +//===----------------------------------------------------------------------===// +defm "" : VPatUnaryV_V<"int_riscv_vfrsqrte7", "PseudoVFRSQRTE7", AllFloatVectors>; + +//===----------------------------------------------------------------------===// +// 14.10. Vector Floating-Point Reciprocal Estimate Instruction +//===----------------------------------------------------------------------===// +defm "" : VPatUnaryV_V<"int_riscv_vfrece7", "PseudoVFRECE7", AllFloatVectors>; + +//===----------------------------------------------------------------------===// // 14.11. Vector Floating-Point Min/Max Instructions //===----------------------------------------------------------------------===// defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmin", "PseudoVFMIN", AllFloatVectors>; diff --git a/llvm/test/CodeGen/RISCV/vfrece7-rv32.ll b/llvm/test/CodeGen/RISCV/vfrece7-rv32.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/vfrece7-rv32.ll @@ -0,0 +1,608 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: --riscv-no-aliases < %s | FileCheck %s +declare @llvm.riscv.vfrece7.nxv1f16( + , + i32); + +define @intrinsic_vfrece7_v_nxv1f16_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv1f16( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv1f16( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv1f16_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfrece7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv1f16( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv2f16( + , + i32); + +define @intrinsic_vfrece7_v_nxv2f16_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv2f16( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv2f16( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv2f16_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfrece7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv2f16( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv4f16( + , + i32); + +define @intrinsic_vfrece7_v_nxv4f16_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv4f16( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv4f16( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv4f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfrece7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv4f16( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv8f16( + , + i32); + +define @intrinsic_vfrece7_v_nxv8f16_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv8f16( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv8f16( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv8f16_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfrece7.v v16, v18, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv8f16( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv16f16( + , + i32); + +define @intrinsic_vfrece7_v_nxv16f16_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv16f16( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv16f16( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfrece7.v v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv16f16( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv32f16( + , + i32); + +define @intrinsic_vfrece7_v_nxv32f16_nxv32f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv32f16( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv32f16( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv32f16_nxv32f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfrece7.v v16, v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv32f16( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv1f32( + , + i32); + +define @intrinsic_vfrece7_v_nxv1f32_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv1f32( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv1f32( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv1f32_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfrece7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv1f32( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv2f32( + , + i32); + +define @intrinsic_vfrece7_v_nxv2f32_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv2f32( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv2f32( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv2f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfrece7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv2f32( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv4f32( + , + i32); + +define @intrinsic_vfrece7_v_nxv4f32_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv4f32( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv4f32( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv4f32_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfrece7.v v16, v18, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv4f32( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv8f32( + , + i32); + +define @intrinsic_vfrece7_v_nxv8f32_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv8f32( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv8f32( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfrece7.v v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv8f32( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv16f32( + , + i32); + +define @intrinsic_vfrece7_v_nxv16f32_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv16f32( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv16f32( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv16f32_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfrece7.v v16, v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv16f32( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv1f64( + , + i32); + +define @intrinsic_vfrece7_v_nxv1f64_nxv1f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv1f64( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv1f64( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv1f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfrece7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv1f64( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv2f64( + , + i32); + +define @intrinsic_vfrece7_v_nxv2f64_nxv2f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv2f64( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv2f64( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv2f64_nxv2f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfrece7.v v16, v18, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv2f64( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv4f64( + , + i32); + +define @intrinsic_vfrece7_v_nxv4f64_nxv4f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv4f64( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv4f64( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfrece7.v v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv4f64( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv8f64( + , + i32); + +define @intrinsic_vfrece7_v_nxv8f64_nxv8f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv8f64( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv8f64( + , + , + , + i32); + +define @intrinsic_vfrece7_mask_v_nxv8f64_nxv8f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfrece7.v v16, v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv8f64( + %1, + %2, + %0, + i32 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/vfrece7-rv64.ll b/llvm/test/CodeGen/RISCV/vfrece7-rv64.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/vfrece7-rv64.ll @@ -0,0 +1,608 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: --riscv-no-aliases < %s | FileCheck %s +declare @llvm.riscv.vfrece7.nxv1f16( + , + i64); + +define @intrinsic_vfrece7_v_nxv1f16_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv1f16( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv1f16( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv1f16_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfrece7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv1f16( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv2f16( + , + i64); + +define @intrinsic_vfrece7_v_nxv2f16_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv2f16( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv2f16( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv2f16_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfrece7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv2f16( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv4f16( + , + i64); + +define @intrinsic_vfrece7_v_nxv4f16_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv4f16( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv4f16( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv4f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfrece7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv4f16( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv8f16( + , + i64); + +define @intrinsic_vfrece7_v_nxv8f16_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv8f16( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv8f16( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv8f16_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfrece7.v v16, v18, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv8f16( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv16f16( + , + i64); + +define @intrinsic_vfrece7_v_nxv16f16_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv16f16( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv16f16( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfrece7.v v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv16f16( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv32f16( + , + i64); + +define @intrinsic_vfrece7_v_nxv32f16_nxv32f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv32f16( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv32f16( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv32f16_nxv32f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfrece7.v v16, v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv32f16( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv1f32( + , + i64); + +define @intrinsic_vfrece7_v_nxv1f32_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv1f32( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv1f32( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv1f32_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfrece7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv1f32( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv2f32( + , + i64); + +define @intrinsic_vfrece7_v_nxv2f32_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv2f32( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv2f32( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv2f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfrece7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv2f32( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv4f32( + , + i64); + +define @intrinsic_vfrece7_v_nxv4f32_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv4f32( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv4f32( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv4f32_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfrece7.v v16, v18, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv4f32( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv8f32( + , + i64); + +define @intrinsic_vfrece7_v_nxv8f32_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv8f32( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv8f32( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfrece7.v v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv8f32( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv16f32( + , + i64); + +define @intrinsic_vfrece7_v_nxv16f32_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv16f32( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv16f32( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv16f32_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfrece7.v v16, v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv16f32( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv1f64( + , + i64); + +define @intrinsic_vfrece7_v_nxv1f64_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv1f64( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv1f64( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv1f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfrece7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv1f64( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv2f64( + , + i64); + +define @intrinsic_vfrece7_v_nxv2f64_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv2f64( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv2f64( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv2f64_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfrece7.v v16, v18, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv2f64( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv4f64( + , + i64); + +define @intrinsic_vfrece7_v_nxv4f64_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv4f64( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv4f64( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfrece7.v v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv4f64( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrece7.nxv8f64( + , + i64); + +define @intrinsic_vfrece7_v_nxv8f64_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfrece7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.nxv8f64( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrece7.mask.nxv8f64( + , + , + , + i64); + +define @intrinsic_vfrece7_mask_v_nxv8f64_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfrece7.v v16, v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrece7.mask.nxv8f64( + %1, + %2, + %0, + i64 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/vfrsqrte7-rv32.ll b/llvm/test/CodeGen/RISCV/vfrsqrte7-rv32.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/vfrsqrte7-rv32.ll @@ -0,0 +1,608 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: --riscv-no-aliases < %s | FileCheck %s +declare @llvm.riscv.vfrsqrte7.nxv1f16( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv1f16_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv1f16( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv1f16( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv1f16_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv1f16( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv2f16( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv2f16_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv2f16( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv2f16( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv2f16_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv2f16( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv4f16( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv4f16_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv4f16( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv4f16( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv4f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv4f16( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv8f16( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv8f16_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv8f16( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv8f16( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv8f16_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v18, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv8f16( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv16f16( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv16f16_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv16f16( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv16f16( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv16f16( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv32f16( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv32f16_nxv32f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv32f16( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv32f16( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv32f16_nxv32f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv32f16( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv1f32( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv1f32_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv1f32( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv1f32( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv1f32_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv1f32( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv2f32( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv2f32_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv2f32( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv2f32( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv2f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv2f32( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv4f32( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv4f32_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv4f32( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv4f32( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv4f32_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v18, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv4f32( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv8f32( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv8f32_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv8f32( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv8f32( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv8f32( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv16f32( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv16f32_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv16f32( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv16f32( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv16f32_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv16f32( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv1f64( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv1f64_nxv1f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv1f64( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv1f64( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv1f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv1f64( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv2f64( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv2f64_nxv2f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv2f64( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv2f64( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv2f64_nxv2f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v18, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv2f64( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv4f64( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv4f64_nxv4f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv4f64( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv4f64( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv4f64( + %1, + %2, + %0, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv8f64( + , + i32); + +define @intrinsic_vfrsqrte7_v_nxv8f64_nxv8f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv8f64( + %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv8f64( + , + , + , + i32); + +define @intrinsic_vfrsqrte7_mask_v_nxv8f64_nxv8f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv8f64( + %1, + %2, + %0, + i32 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/vfrsqrte7-rv64.ll b/llvm/test/CodeGen/RISCV/vfrsqrte7-rv64.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/vfrsqrte7-rv64.ll @@ -0,0 +1,608 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ +; RUN: --riscv-no-aliases < %s | FileCheck %s +declare @llvm.riscv.vfrsqrte7.nxv1f16( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv1f16_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv1f16( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv1f16( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv1f16_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv1f16( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv2f16( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv2f16_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv2f16( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv2f16( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv2f16_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv2f16( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv4f16( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv4f16_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv4f16( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv4f16( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv4f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv4f16( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv8f16( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv8f16_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv8f16( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv8f16( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv8f16_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v18, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv8f16( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv16f16( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv16f16_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv16f16( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv16f16( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv16f16( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv32f16( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv32f16_nxv32f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv32f16( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv32f16( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv32f16_nxv32f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv32f16( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv1f32( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv1f32_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv1f32( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv1f32( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv1f32_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv1f32( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv2f32( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv2f32_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv2f32( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv2f32( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv2f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv2f32( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv4f32( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv4f32_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv4f32( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv4f32( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv4f32_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v18, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv4f32( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv8f32( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv8f32_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv8f32( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv8f32( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv8f32( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv16f32( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv16f32_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv16f32( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv16f32( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv16f32_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv16f32( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv1f64( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv1f64_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv1f64( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv1f64( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv1f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v17, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv1f64( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv2f64( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv2f64_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv2f64( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv2f64( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv2f64_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v18, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv2f64( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv4f64( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv4f64_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv4f64( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv4f64( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv4f64( + %1, + %2, + %0, + i64 %3) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.nxv8f64( + , + i64); + +define @intrinsic_vfrsqrte7_v_nxv8f64_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfrsqrte7.v v16, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.nxv8f64( + %0, + i64 %1) + + ret %a +} + +declare @llvm.riscv.vfrsqrte7.mask.nxv8f64( + , + , + , + i64); + +define @intrinsic_vfrsqrte7_mask_v_nxv8f64_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfrsqrte7.v v16, v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vfrsqrte7.mask.nxv8f64( + %1, + %2, + %0, + i64 %3) + + ret %a +}