diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -332,6 +332,42 @@
       case 'c':
         Features.AddFeature(Arch.take_front());
         break;
+      case 'b':
+        Features.AddFeature("experimental-b");
+        break;
+      case 'v':
+        Features.AddFeature("experimental-v");
+        break;
+      case 'z':
+        // Test for multi-letter extensions
+        StringRef Ext = Arch.take_until([](char c) { return ::isdigit(c); });
+        if (Ext == "zbb")
+          Features.AddFeature("experimental-zbb");
+        else if (Ext == "zbc")
+          Features.AddFeature("experimental-zbc");
+        else if (Ext == "zbe")
+          Features.AddFeature("experimental-zbe");
+        else if (Ext == "zbf")
+          Features.AddFeature("experimental-zbf");
+        else if (Ext == "zbm")
+          Features.AddFeature("experimental-zbm");
+        else if (Ext == "zbp")
+          Features.AddFeature("experimental-zbp");
+        else if (Ext == "zbproposedc")
+          Features.AddFeature("experimental-zbproposedc");
+        else if (Ext == "zbr")
+          Features.AddFeature("experimental-zbr");
+        else if (Ext == "zbs")
+          Features.AddFeature("experimental-zbs");
+        else if (Ext == "zbt")
+          Features.AddFeature("experimental-zbt");
+        else if (Ext == "zfh")
+          Features.AddFeature("experimental-zfh");
+        else if (Ext == "zvamo")
+          Features.AddFeature("experimental-zvamo");
+        else if (Ext == "zvlsseg")
+          Features.AddFeature("experimental-zvlsseg");
+        break;
       }
 
       // FIXME: Handle version numbers.
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1998,7 +1998,32 @@
     else
       return Error(ValueExprLoc, "bad arch string " + Arch);
 
+    // .attribute arch overrides the current architecture, so unset all
+    // currently enabled extensions
+    clearFeatureBits(RISCV::FeatureRV32E, "e");
+    clearFeatureBits(RISCV::FeatureStdExtM, "m");
+    clearFeatureBits(RISCV::FeatureStdExtA, "a");
+    clearFeatureBits(RISCV::FeatureStdExtF, "f");
+    clearFeatureBits(RISCV::FeatureStdExtD, "d");
+    clearFeatureBits(RISCV::FeatureStdExtC, "c");
+    clearFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
+    clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
+    clearFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
+    clearFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
+    clearFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe");
+    clearFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf");
+    clearFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm");
+    clearFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp");
+    clearFeatureBits(RISCV::FeatureExtZbproposedc, "experimental-zbproposedc");
+    clearFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
+    clearFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
+    clearFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
+    clearFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
+    clearFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
+    clearFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
+
     while (!Arch.empty()) {
+      bool DropFirst = true;
       if (Arch[0] == 'i')
         clearFeatureBits(RISCV::FeatureRV32E, "e");
       else if (Arch[0] == 'e')
@@ -2020,10 +2045,48 @@
         setFeatureBits(RISCV::FeatureStdExtD, "d");
       } else if (Arch[0] == 'c') {
         setFeatureBits(RISCV::FeatureStdExtC, "c");
+      } else if (Arch[0] == 'b') {
+        setFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
+      } else if (Arch[0] == 'v') {
+        setFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
+      } else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') {
+        StringRef Ext = Arch.take_until([](char c) { return ::isdigit(c); });
+        if (Ext == "zbb")
+          setFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
+        else if (Ext == "zbc")
+          setFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
+        else if (Ext == "zbe")
+          setFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe");
+        else if (Ext == "zbf")
+          setFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf");
+        else if (Ext == "zbm")
+          setFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm");
+        else if (Ext == "zbp")
+          setFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp");
+        else if (Ext == "zbproposedc")
+          setFeatureBits(RISCV::FeatureExtZbproposedc,
+                         "experimental-zbproposedc");
+        else if (Ext == "zbr")
+          setFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
+        else if (Ext == "zbs")
+          setFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
+        else if (Ext == "zbt")
+          setFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
+        else if (Ext == "zfh")
+          setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
+        else if (Ext == "zvamo")
+          setFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
+        else if (Ext == "zvlsseg")
+          setFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
+        else
+          return Error(ValueExprLoc, "bad arch string " + Ext);
+        Arch = Arch.drop_until([](char c) { return ::isdigit(c); });
+        DropFirst = false;
       } else
         return Error(ValueExprLoc, "bad arch string " + Arch);
 
-      Arch = Arch.drop_front(1);
+      if (DropFirst)
+        Arch = Arch.drop_front(1);
       int major = 0;
       int minor = 0;
       Arch.consumeInteger(10, major);
@@ -2060,6 +2123,36 @@
         formalArchStr = (Twine(formalArchStr) + "_d2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtC))
         formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
+      if (getFeatureBits(RISCV::FeatureStdExtB))
+        formalArchStr = (Twine(formalArchStr) + "_b0p92").str();
+      if (getFeatureBits(RISCV::FeatureStdExtV))
+        formalArchStr = (Twine(formalArchStr) + "_v0p9").str();
+      if (getFeatureBits(RISCV::FeatureExtZbb))
+        formalArchStr = (Twine(formalArchStr) + "_zbb0p92").str();
+      if (getFeatureBits(RISCV::FeatureExtZbc))
+        formalArchStr = (Twine(formalArchStr) + "_zbc0p92").str();
+      if (getFeatureBits(RISCV::FeatureExtZbe))
+        formalArchStr = (Twine(formalArchStr) + "_zbe0p92").str();
+      if (getFeatureBits(RISCV::FeatureExtZbf))
+        formalArchStr = (Twine(formalArchStr) + "_zbf0p92").str();
+      if (getFeatureBits(RISCV::FeatureExtZbm))
+        formalArchStr = (Twine(formalArchStr) + "_zbm0p92").str();
+      if (getFeatureBits(RISCV::FeatureExtZbp))
+        formalArchStr = (Twine(formalArchStr) + "_zbp0p92").str();
+      if (getFeatureBits(RISCV::FeatureExtZbproposedc))
+        formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p92").str();
+      if (getFeatureBits(RISCV::FeatureExtZbr))
+        formalArchStr = (Twine(formalArchStr) + "_zbr0p92").str();
+      if (getFeatureBits(RISCV::FeatureExtZbs))
+        formalArchStr = (Twine(formalArchStr) + "_zbs0p92").str();
+      if (getFeatureBits(RISCV::FeatureExtZbt))
+        formalArchStr = (Twine(formalArchStr) + "_zbt0p92").str();
+      if (getFeatureBits(RISCV::FeatureExtZfh))
+        formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
+      if (getFeatureBits(RISCV::FeatureExtZvamo))
+        formalArchStr = (Twine(formalArchStr) + "_zvamo0p9").str();
+      if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
+        formalArchStr = (Twine(formalArchStr) + "_zvlsseg0p9").str();
 
       getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
     }
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -60,6 +60,36 @@
     Arch += "_d2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtC))
     Arch += "_c2p0";
+  if (STI.hasFeature(RISCV::FeatureStdExtB))
+    Arch += "_b0p92";
+  if (STI.hasFeature(RISCV::FeatureStdExtV))
+    Arch += "_v0p9";
+  if (STI.hasFeature(RISCV::FeatureExtZbb))
+    Arch += "_zbb0p92";
+  if (STI.hasFeature(RISCV::FeatureExtZbc))
+    Arch += "_zbc0p92";
+  if (STI.hasFeature(RISCV::FeatureExtZbe))
+    Arch += "_zbe0p92";
+  if (STI.hasFeature(RISCV::FeatureExtZbf))
+    Arch += "_zbf0p92";
+  if (STI.hasFeature(RISCV::FeatureExtZbm))
+    Arch += "_zbm0p92";
+  if (STI.hasFeature(RISCV::FeatureExtZbp))
+    Arch += "_zbp0p92";
+  if (STI.hasFeature(RISCV::FeatureExtZbproposedc))
+    Arch += "_zbproposedc0p92";
+  if (STI.hasFeature(RISCV::FeatureExtZbr))
+    Arch += "_zbr0p92";
+  if (STI.hasFeature(RISCV::FeatureExtZbs))
+    Arch += "_zbs0p92";
+  if (STI.hasFeature(RISCV::FeatureExtZbt))
+    Arch += "_zbt0p92";
+  if (STI.hasFeature(RISCV::FeatureExtZfh))
+    Arch += "_zfh0p1";
+  if (STI.hasFeature(RISCV::FeatureExtZvamo))
+    Arch += "_zvamo0p9";
+  if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
+    Arch += "_zvlsseg0p9";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -5,22 +5,82 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefix=RV32F %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV32B %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV32V %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV32ZBB %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV32ZBE %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV32ZBF %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV32ZBM %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV32ZBP %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV32ZBPROPOSEDC %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvamo %s -o - | FileCheck --check-prefix=RV32ZVAMO %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32ZVLSSEG %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV64B %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV64V %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV64ZBB %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV64ZBE %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV64ZBF %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV64ZBM %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV64ZBP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV64ZBPROPOSEDC %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvamo %s -o - | FileCheck --check-prefix=RV64ZVAMO %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64ZVLSSEG %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
+; RV32B: .attribute 5, "rv32i2p0_b0p92_zbb0p92_zbc0p92_zbe0p92_zbf0p92_zbm0p92_zbp0p92_zbr0p92_zbs0p92_zbt0p92"
+; RV32V: .attribute 5, "rv32i2p0_v0p9"
+; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p92"
+; RV32ZBC: .attribute 5, "rv32i2p0_zbc0p92"
+; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p92"
+; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p92"
+; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p92"
+; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p92"
+; RV32ZBPROPOSEDC: .attribute 5, "rv32i2p0_zbproposedc0p92"
+; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p92"
+; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p92"
+; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p92"
+; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
+; RV32ZVAMO: .attribute 5, "rv32i2p0_v0p9_zvamo0p9"
+; RV32ZVLSSEG: .attribute 5, "rv32i2p0_v0p9_zvlsseg0p9"
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
+; RV64B: .attribute 5, "rv64i2p0_b0p92_zbb0p92_zbc0p92_zbe0p92_zbf0p92_zbm0p92_zbp0p92_zbr0p92_zbs0p92_zbt0p92"
+; RV64V: .attribute 5, "rv64i2p0_v0p9"
+; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p92"
+; RV64ZBC: .attribute 5, "rv64i2p0_zbc0p92"
+; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p92"
+; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p92"
+; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p92"
+; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p92"
+; RV64ZBPROPOSEDC: .attribute 5, "rv64i2p0_zbproposedc0p92"
+; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p92"
+; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p92"
+; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p92"
+; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1"
+; RV64ZVAMO: .attribute 5, "rv64i2p0_v0p9_zvamo0p9"
+; RV64ZVLSSEG: .attribute 5, "rv64i2p0_v0p9_zvlsseg0p9"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -35,3 +35,48 @@
 
 .attribute arch, "rv32ima2p_fdc"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+
+.attribute arch, "rv32ib"
+# CHECK: attribute      5, "rv32i2p0_b0p92_zbb0p92_zbc0p92_zbe0p92_zbf0p92_zbm0p92_zbp0p92_zbr0p92_zbs0p92_zbt0p92"
+
+.attribute arch, "rv32iv"
+# CHECK: attribute      5, "rv32i2p0_v0p9"
+
+.attribute arch, "rv32izbb"
+# CHECK: attribute      5, "rv32i2p0_zbb0p92"
+
+.attribute arch, "rv32izbc"
+# CHECK: attribute      5, "rv32i2p0_zbc0p92"
+
+.attribute arch, "rv32izbe"
+# CHECK: attribute      5, "rv32i2p0_zbe0p92"
+
+.attribute arch, "rv32izbf"
+# CHECK: attribute      5, "rv32i2p0_zbf0p92"
+
+.attribute arch, "rv32izbm"
+# CHECK: attribute      5, "rv32i2p0_zbm0p92"
+
+.attribute arch, "rv32izbp"
+# CHECK: attribute      5, "rv32i2p0_zbp0p92"
+
+.attribute arch, "rv32izbproposedc"
+# CHECK: attribute      5, "rv32i2p0_zbproposedc0p92"
+
+.attribute arch, "rv32izbr"
+# CHECK: attribute      5, "rv32i2p0_zbr0p92"
+
+.attribute arch, "rv32izbs"
+# CHECK: attribute      5, "rv32i2p0_zbs0p92"
+
+.attribute arch, "rv32izbt"
+# CHECK: attribute      5, "rv32i2p0_zbt0p92"
+
+.attribute arch, "rv32izfh"
+# CHECK: attribute      5, "rv32i2p0_f2p0_zfh0p1"
+
+.attribute arch, "rv32izvamo"
+# CHECK: attribute      5, "rv32i2p0_v0p9_zvamo0p9"
+
+.attribute arch, "rv32izvlsseg"
+# CHECK: attribute      5, "rv32i2p0_v0p9_zvlsseg0p9"
diff --git a/llvm/test/MC/RISCV/attribute-with-insts.s b/llvm/test/MC/RISCV/attribute-with-insts.s
--- a/llvm/test/MC/RISCV/attribute-with-insts.s
+++ b/llvm/test/MC/RISCV/attribute-with-insts.s
@@ -10,7 +10,7 @@
 # RUN:   | llvm-objdump --triple=riscv64 -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefix=CHECK-INST %s
 
-.attribute arch, "rv64i2p0_m2p0_a2p0_d2p0_c2p0"
+.attribute arch, "rv64i2p0_m2p0_a2p0_d2p0_c2p0_b0p92_v0p9_zfh0p1"
 
 # CHECK-INST: lr.w t0, (t1)
 lr.w t0, (t1)
@@ -32,3 +32,12 @@
 
 # CHECK-INST: addw a2, a3, a4
 addw a2, a3, a4
+
+# CHECK-INST: andn a0, a1, a2
+andn a0, a1, a2
+
+# CHECK-INST: vadd.vv v8, v4, v20, v0.t
+vadd.vv v8, v4, v20, v0.t
+
+# CHECK-INST: flh ft0, 12(a0)
+flh ft0, 12(a0)