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[RISCV] Implement vssseg intrinsics.
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Authored by HsiangKai on Jan 16 2021, 5:43 AM.

Details

Summary

Define vlsseg intrinsics and pseudo instructions. Lower vlsseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.

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Event Timeline

HsiangKai created this revision.Jan 16 2021, 5:43 AM
HsiangKai requested review of this revision.Jan 16 2021, 5:43 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 16 2021, 5:43 AM
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HsiangKai updated this revision to Diff 317291.Jan 18 2021, 1:59 AM

Add test cases for floating point types.

HsiangKai updated this revision to Diff 317748.Jan 19 2021, 6:42 PM

Add test cases for rv32.

HsiangKai updated this revision to Diff 317755.Jan 19 2021, 7:11 PM

clang format.

craig.topper accepted this revision.Jan 20 2021, 10:30 AM

LGTM

llvm/include/llvm/IR/IntrinsicsRISCV.td
543

stride -> strided

This revision is now accepted and ready to land.Jan 20 2021, 10:30 AM
This revision was landed with ongoing or failed builds.Jan 20 2021, 7:53 PM
This revision was automatically updated to reflect the committed changes.