[RISCV] Add scalable vector truncate patterns

[frasercrmck]

Summary

Original patch by @rogfer01.

This patch supports vector truncates, which on RVV must be done in a
series of instructions truncating by one power-of-two at a time. This is
done through custom-lowering and a custom node to avoid LLVM
re-combining the split TRUNCATE nodes.

Authored-by: Roger Ferrer Ibanez <[e-mail]>
Co-Authored-by: Fraser Cormack <[e-mail]>

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.h

94

Worth just making this VNSRL? Will we end up with a DAG combine to combine shifts+truncate?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.h

94

Worth just making this VNSRL? Will we end up with a DAG combine to combine shifts+truncate?

94

Though I guess then you have to use splat vector and deal with type legalization there. So maybe its not worth that complexity yet.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   // Vector Extension
   // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT
   // sign extended from the vector element size. NOTE: The result size will
   // never be less than the vector element size.
   VMV_X_S,
   // Splats an i64 scalar to a vector type (with element type i64) where the
   // scalar is a sign-extended i32.
   SPLAT_VECTOR_I64,
   // Read VLENB CSR
   READ_VLENB,
+  // Truncates a RVV integer vector by one power-of-two.
+  TRUNCATE_VECTOR,
 };
 } // namespace RISCVISD
 
 class RISCVTargetLowering : public TargetLowering {
   const RISCVSubtarget &Subtarget;
 
 public:
   explicit RISCVTargetLowering(const TargetMachine &TM,

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.hasStdExtV()) {
 
     for (auto VT : MVT::integer_scalable_vector_valuetypes()) {
       setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
 
       setOperationAction(ISD::SMIN, VT, Legal);
       setOperationAction(ISD::SMAX, VT, Legal);
       setOperationAction(ISD::UMIN, VT, Legal);
       setOperationAction(ISD::UMAX, VT, Legal);
+
+      // Lower RVV truncates as a series of "RISCVISD::TRUNCATE_VECTOR"
+      // nodes which truncate by one power of two at a time.
+      setOperationAction(ISD::TRUNCATE, VT, Custom);
     }
 
     // We must custom-lower SPLAT_VECTOR vXi64 on RV32
     if (!Subtarget.is64Bit())
       setOperationAction(ISD::SPLAT_VECTOR, MVT::i64, Custom);
 
     // Expand various CCs to best match the RVV ISA, which natively supports UNE
     // but no other unordered comparisons, and supports all ordered comparisons
case ISD::BITREVERSE: {
     // Start with the maximum immediate value which is the bitwidth - 1.
     unsigned Imm = VT.getSizeInBits() - 1;
     // If this is BSWAP rather than BITREVERSE, clear the lower 3 bits.
     if (Op.getOpcode() == ISD::BSWAP)
       Imm &= ~0x7U;
     return DAG.getNode(RISCVISD::GREVI, DL, VT, Op.getOperand(0),
                        DAG.getTargetConstant(Imm, DL, Subtarget.getXLenVT()));
   }
+  case ISD::TRUNCATE: {
+    // RVV only has truncates which operate from SEW*2->SEW, so lower arbitrary
+    // truncates as a series of "RISCVISD::TRUNCATE_VECTOR" nodes which
+    // truncate by one power of two at a time.
+    SDLoc DL(Op);
+    EVT VT = Op.getValueType();
+    // Only custom-lower non-mask truncates
+    if (!VT.isVector() || VT.getVectorElementType() == MVT::i1)
+      return Op;
+
+    EVT DstEltVT = VT.getVectorElementType();
+
+    SDValue Src = Op.getOperand(0);
+    EVT SrcVT = Src.getValueType();
+    EVT SrcEltVT = SrcVT.getVectorElementType();
+
+    assert(DstEltVT.bitsLT(SrcEltVT) &&
+           isPowerOf2_64(DstEltVT.getSizeInBits()) &&
+           isPowerOf2_64(SrcEltVT.getSizeInBits()) &&
+           "Unexpected vector truncate lowering");
+
+    SDValue Result = Src;
+    LLVMContext &Context = *DAG.getContext();
+    const ElementCount Count = SrcVT.getVectorElementCount();
+    do {
+      SrcEltVT = EVT::getIntegerVT(Context, SrcEltVT.getSizeInBits() / 2);
+      EVT ResultVT = EVT::getVectorVT(Context, SrcEltVT, Count);
+      Result = DAG.getNode(RISCVISD::TRUNCATE_VECTOR, DL, ResultVT, Result);
+    } while (SrcEltVT != DstEltVT);
+
+    return Result;
+  }
   case ISD::SPLAT_VECTOR:
     return lowerSPLATVECTOR(Op, DAG);
   case ISD::VSCALE: {
     MVT VT = Op.getSimpleValueType();
     SDLoc DL(Op);
     SDValue VLENB = DAG.getNode(RISCVISD::READ_VLENB, DL, VT);
     // We define our scalable vector types for lmul=1 to use a 64 bit known
     // minimum size. e.g. <vscale x 2 x i32>. VLENB is in bytes so we calculate
#define NODE_NAME_CASE(NODE)                                                   \
   NODE_NAME_CASE(READ_CYCLE_WIDE)
   NODE_NAME_CASE(GREVI)
   NODE_NAME_CASE(GREVIW)
   NODE_NAME_CASE(GORCI)
   NODE_NAME_CASE(GORCIW)
   NODE_NAME_CASE(VMV_X_S)
   NODE_NAME_CASE(SPLAT_VECTOR_I64)
   NODE_NAME_CASE(READ_VLENB)
+  NODE_NAME_CASE(TRUNCATE_VECTOR)
   }
   // clang-format on
   return nullptr;
 #undef NODE_NAME_CASE
 }
 
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

 //===----------------------------------------------------------------------===//
 
 def SDTSplatI64 : SDTypeProfile<1, 1, [
   SDTCVecEltisVT<0, i64>, SDTCisVT<1, i32>
 ]>;
 
 def rv32_splat_i64 : SDNode<"RISCVISD::SPLAT_VECTOR_I64", SDTSplatI64>;
 
+def riscv_trunc_vector : SDNode<"RISCVISD::TRUNCATE_VECTOR",
+                                SDTypeProfile<1, 1,
+                                 [SDTCisVec<0>, SDTCisVec<1>]>>;
+
 // Penalize the generic form with Complexity=1 to give the simm5/uimm5 variants
 // precedence
 def SplatPat       : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>;
 
 def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", []>;
 def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", []>;
 
 class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {

 defm "" : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">;
 defm "" : VPatBinarySDNode_VV_VX_VI<xor, "PseudoVXOR">;
 
 // 12.6. Vector Single-Width Bit Shift Instructions
 defm "" : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
 defm "" : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
 defm "" : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>;
 
+// 12.7. Vector Narrowing Integer Right Shift Instructions
+foreach vtiTofti = AllFractionableVF2IntVectors in {
+  defvar vti = vtiTofti.Vti;
+  defvar fti = vtiTofti.Fti;
+  def : Pat<(fti.Vector (riscv_trunc_vector (vti.Vector vti.RegClass:$rs1))),
+            (!cast<Instruction>("PseudoVNSRL_WI_"#fti.LMul.MX)
+                vti.RegClass:$rs1, 0, VLMax, fti.SEW)>;
+}
+
 // 12.8. Vector Integer Comparison Instructions
 defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ,  "PseudoVMSEQ">;
 defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE,  "PseudoVMSNE">;
 
 // FIXME: Support immediate forms of these by choosing SLE decrementing the
 // immediate
 defm "" : VPatIntegerSetCCSDNode_VV_VX<SETLT,  "PseudoVMSLT">;
 defm "" : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">;

llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vtrunc_nxv1i16_nxv1i8(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vtrunc_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 1 x i16> %va to <vscale x 1 x i8>
+  ret <vscale x 1 x i8> %tvec
+}
+
+define <vscale x 2 x i8> @vtrunc_nxv2i16_nxv2i8(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vtrunc_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 2 x i16> %va to <vscale x 2 x i8>
+  ret <vscale x 2 x i8> %tvec
+}
+
+define <vscale x 4 x i8> @vtrunc_nxv4i16_nxv4i8(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vtrunc_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 4 x i16> %va to <vscale x 4 x i8>
+  ret <vscale x 4 x i8> %tvec
+}
+
+define <vscale x 8 x i8> @vtrunc_nxv8i16_nxv8i8(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vtrunc_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 8 x i16> %va to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %tvec
+}
+
+define <vscale x 16 x i8> @vtrunc_nxv16i16_nxv16i8(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vtrunc_nxv16i16_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v16, 0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 16 x i16> %va to <vscale x 16 x i8>
+  ret <vscale x 16 x i8> %tvec
+}
+
+define <vscale x 1 x i8> @vtrunc_nxv1i32_nxv1i8(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v25, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i8>
+  ret <vscale x 1 x i8> %tvec
+}
+
+define <vscale x 1 x i16> @vtrunc_nxv1i32_nxv1i16(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i16>
+  ret <vscale x 1 x i16> %tvec
+}
+
+define <vscale x 2 x i8> @vtrunc_nxv2i32_nxv2i8(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v25, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i8>
+  ret <vscale x 2 x i8> %tvec
+}
+
+define <vscale x 2 x i16> @vtrunc_nxv2i32_nxv2i16(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i16>
+  ret <vscale x 2 x i16> %tvec
+}
+
+define <vscale x 4 x i8> @vtrunc_nxv4i32_nxv4i8(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v25, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i8>
+  ret <vscale x 4 x i8> %tvec
+}
+
+define <vscale x 4 x i16> @vtrunc_nxv4i32_nxv4i16(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i16>
+  ret <vscale x 4 x i16> %tvec
+}
+
+define <vscale x 8 x i8> @vtrunc_nxv8i32_nxv8i8(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v26, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %tvec
+}
+
+define <vscale x 8 x i16> @vtrunc_nxv8i32_nxv8i16(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v16, 0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %tvec
+}
+
+define <vscale x 16 x i8> @vtrunc_nxv16i32_nxv16i8(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v28, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v28, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i8>
+  ret <vscale x 16 x i8> %tvec
+}
+
+define <vscale x 16 x i16> @vtrunc_nxv16i32_nxv16i16(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v28, v16, 0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i16>
+  ret <vscale x 16 x i16> %tvec
+}
+
+define <vscale x 1 x i8> @vtrunc_nxv1i64_nxv1i8(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v26, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i8>
+  ret <vscale x 1 x i8> %tvec
+}
+
+define <vscale x 1 x i16> @vtrunc_nxv1i64_nxv1i16(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v25, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i16>
+  ret <vscale x 1 x i16> %tvec
+}
+
+define <vscale x 1 x i32> @vtrunc_nxv1i64_nxv1i32(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %tvec
+}
+
+define <vscale x 2 x i8> @vtrunc_nxv2i64_nxv2i8(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v26, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i8>
+  ret <vscale x 2 x i8> %tvec
+}
+
+define <vscale x 2 x i16> @vtrunc_nxv2i64_nxv2i16(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v25, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i16>
+  ret <vscale x 2 x i16> %tvec
+}
+
+define <vscale x 2 x i32> @vtrunc_nxv2i64_nxv2i32(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %tvec
+}
+
+define <vscale x 4 x i8> @vtrunc_nxv4i64_nxv4i8(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v26, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v25, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i8>
+  ret <vscale x 4 x i8> %tvec
+}
+
+define <vscale x 4 x i16> @vtrunc_nxv4i64_nxv4i16(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v26, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i16>
+  ret <vscale x 4 x i16> %tvec
+}
+
+define <vscale x 4 x i32> @vtrunc_nxv4i64_nxv4i32(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v16, 0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %tvec
+}
+
+define <vscale x 8 x i8> @vtrunc_nxv8i64_nxv8i8(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v28, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v28, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v26, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %tvec
+}
+
+define <vscale x 8 x i16> @vtrunc_nxv8i64_nxv8i16(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v28, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v28, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %tvec
+}
+
+define <vscale x 8 x i32> @vtrunc_nxv8i64_nxv8i32(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v28, v16, 0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %tvec
+}
+

llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vtrunc_nxv1i16_nxv1i8(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vtrunc_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 1 x i16> %va to <vscale x 1 x i8>
+  ret <vscale x 1 x i8> %tvec
+}
+
+define <vscale x 2 x i8> @vtrunc_nxv2i16_nxv2i8(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vtrunc_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 2 x i16> %va to <vscale x 2 x i8>
+  ret <vscale x 2 x i8> %tvec
+}
+
+define <vscale x 4 x i8> @vtrunc_nxv4i16_nxv4i8(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vtrunc_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 4 x i16> %va to <vscale x 4 x i8>
+  ret <vscale x 4 x i8> %tvec
+}
+
+define <vscale x 8 x i8> @vtrunc_nxv8i16_nxv8i8(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vtrunc_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 8 x i16> %va to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %tvec
+}
+
+define <vscale x 16 x i8> @vtrunc_nxv16i16_nxv16i8(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vtrunc_nxv16i16_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v16, 0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 16 x i16> %va to <vscale x 16 x i8>
+  ret <vscale x 16 x i8> %tvec
+}
+
+define <vscale x 1 x i8> @vtrunc_nxv1i32_nxv1i8(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v25, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i8>
+  ret <vscale x 1 x i8> %tvec
+}
+
+define <vscale x 1 x i16> @vtrunc_nxv1i32_nxv1i16(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i16>
+  ret <vscale x 1 x i16> %tvec
+}
+
+define <vscale x 2 x i8> @vtrunc_nxv2i32_nxv2i8(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v25, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i8>
+  ret <vscale x 2 x i8> %tvec
+}
+
+define <vscale x 2 x i16> @vtrunc_nxv2i32_nxv2i16(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i16>
+  ret <vscale x 2 x i16> %tvec
+}
+
+define <vscale x 4 x i8> @vtrunc_nxv4i32_nxv4i8(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v25, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i8>
+  ret <vscale x 4 x i8> %tvec
+}
+
+define <vscale x 4 x i16> @vtrunc_nxv4i32_nxv4i16(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i16>
+  ret <vscale x 4 x i16> %tvec
+}
+
+define <vscale x 8 x i8> @vtrunc_nxv8i32_nxv8i8(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v26, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %tvec
+}
+
+define <vscale x 8 x i16> @vtrunc_nxv8i32_nxv8i16(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v16, 0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %tvec
+}
+
+define <vscale x 16 x i8> @vtrunc_nxv16i32_nxv16i8(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v28, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v28, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i8>
+  ret <vscale x 16 x i8> %tvec
+}
+
+define <vscale x 16 x i16> @vtrunc_nxv16i32_nxv16i16(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vtrunc_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v28, v16, 0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i16>
+  ret <vscale x 16 x i16> %tvec
+}
+
+define <vscale x 1 x i8> @vtrunc_nxv1i64_nxv1i8(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v26, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i8>
+  ret <vscale x 1 x i8> %tvec
+}
+
+define <vscale x 1 x i16> @vtrunc_nxv1i64_nxv1i16(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v25, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i16>
+  ret <vscale x 1 x i16> %tvec
+}
+
+define <vscale x 1 x i32> @vtrunc_nxv1i64_nxv1i32(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %tvec
+}
+
+define <vscale x 2 x i8> @vtrunc_nxv2i64_nxv2i8(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v25, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v26, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i8>
+  ret <vscale x 2 x i8> %tvec
+}
+
+define <vscale x 2 x i16> @vtrunc_nxv2i64_nxv2i16(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v25, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i16>
+  ret <vscale x 2 x i16> %tvec
+}
+
+define <vscale x 2 x i32> @vtrunc_nxv2i64_nxv2i32(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v16, 0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %tvec
+}
+
+define <vscale x 4 x i8> @vtrunc_nxv4i64_nxv4i8(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v26, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v25, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i8>
+  ret <vscale x 4 x i8> %tvec
+}
+
+define <vscale x 4 x i16> @vtrunc_nxv4i64_nxv4i16(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v26, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i16>
+  ret <vscale x 4 x i16> %tvec
+}
+
+define <vscale x 4 x i32> @vtrunc_nxv4i64_nxv4i32(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v16, 0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %tvec
+}
+
+define <vscale x 8 x i8> @vtrunc_nxv8i64_nxv8i8(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v28, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v26, v28, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v26, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %tvec
+}
+
+define <vscale x 8 x i16> @vtrunc_nxv8i64_nxv8i16(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v28, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v16, v28, 0
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %tvec
+}
+
+define <vscale x 8 x i32> @vtrunc_nxv8i64_nxv8i32(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vtrunc_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vnsrl.wi v28, v16, 0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    ret
+  %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %tvec
+}
+