diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3966,16 +3966,16 @@
     (void)Legalized;
     assert(Legalized && "Can't legalize BR_CC with legal condition!");
 
-    assert(!NeedInvert && "Don't know how to invert BR_CC!");
-
     // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
     // node.
     if (Tmp4.getNode()) {
+      assert(!NeedInvert && "Don't know how to invert BR_CC!");
+
       Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
                          Tmp4, Tmp2, Tmp3, Node->getOperand(4));
     } else {
       Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
-      Tmp4 = DAG.getCondCode(ISD::SETNE);
+      Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE);
       Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
                          Tmp2, Tmp3, Node->getOperand(4));
     }
diff --git a/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll b/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O1 -mtriple powerpc -mattr=+spe -o - %s | FileCheck %s
+
+; This used to hit an assert
+;
+;   ../lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:3971: bool {anonymous}::SelectionDAGLegalize::ExpandNode(llvm::SDNode*): Assertion `!NeedInvert && "Don't know how to invert BR_CC!"' failed.
+
+define void @test_fcmpueq_legalize_br_cc_with_invert(float %a) {
+; CHECK-LABEL: test_fcmpueq_legalize_br_cc_with_invert:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lis 4, .LCPI0_0@ha
+; CHECK-NEXT:    lwz 4, .LCPI0_0@l(4)
+; CHECK-NEXT:  .LBB0_1: # %l1
+; CHECK-NEXT:    #
+; CHECK-NEXT:    efscmplt 7, 3, 4
+; CHECK-NEXT:    efscmpgt 0, 3, 4
+; CHECK-NEXT:    mfcr 5 # cr7
+; CHECK-NEXT:    mcrf 7, 0
+; CHECK-NEXT:    mfcr 6 # cr7
+; CHECK-NEXT:    rlwinm 5, 5, 30, 31, 31
+; CHECK-NEXT:    rlwinm 6, 6, 30, 31, 31
+; CHECK-NEXT:    or. 5, 6, 5
+; CHECK-NEXT:    beq 0, .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %l2
+; CHECK-NEXT:    blr
+entry:
+  br label %l1
+l1:
+  %fcmp = fcmp ueq float %a, 0xC6306B3440000000
+  br i1 %fcmp, label %l1, label %l2
+l2:
+  ret void
+}