This is an archive of the discontinued LLVM Phabricator instance.

Show First 20 Lines • Show All 377 Lines • ▼ Show 20 Lines	let RegAltNameIndices = [ABIRegAltName] in {
}		}

def VTYPE : RISCVReg<0, "vtype", ["vtype"]>;		def VTYPE : RISCVReg<0, "vtype", ["vtype"]>;
def VL : RISCVReg<0, "vl", ["vl"]>;		def VL : RISCVReg<0, "vl", ["vl"]>;
def VXSAT : RISCVReg<0, "vxsat", ["vxsat"]>;		def VXSAT : RISCVReg<0, "vxsat", ["vxsat"]>;
def VXRM : RISCVReg<0, "vxrm", ["vxrm"]>;		def VXRM : RISCVReg<0, "vxrm", ["vxrm"]>;
}		}

class RegisterTypes<list<ValueType> reg_types> {
list<ValueType> types = reg_types;
}

class VReg<list<ValueType> regTypes, dag regList, int Vlmul>		class VReg<list<ValueType> regTypes, dag regList, int Vlmul>
: RegisterClass<"RISCV",		: RegisterClass<"RISCV",
regTypes,		regTypes,
// FIXME: Spill alignment set to 16 bytes.		// FIXME: Spill alignment set to 16 bytes.
128,		128,
regList> {		regList> {
int VLMul = Vlmul;		int VLMul = Vlmul;
int Size = !mul(Vlmul, 64); // FIXME: assuming ELEN=64		int Size = !mul(Vlmul, 64); // FIXME: assuming ELEN=64
▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines

[NFC][RISCV] Remove useless code in RISCVRegisterInfo.td.ClosedPublic